WebAssemblyInstrInfo.td revision 353358
1// WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*- 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly Instruction definitions. 11/// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// WebAssembly Instruction Predicate Definitions. 16//===----------------------------------------------------------------------===// 17 18def IsPIC : Predicate<"TM.isPositionIndependent()">; 19def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; 20 21def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">; 22 23def HasAddr64 : Predicate<"Subtarget->hasAddr64()">; 24 25def HasSIMD128 : 26 Predicate<"Subtarget->hasSIMD128()">, 27 AssemblerPredicate<"FeatureSIMD128", "simd128">; 28 29def HasUnimplementedSIMD128 : 30 Predicate<"Subtarget->hasUnimplementedSIMD128()">, 31 AssemblerPredicate<"FeatureUnimplementedSIMD128", "unimplemented-simd128">; 32 33def HasAtomics : 34 Predicate<"Subtarget->hasAtomics()">, 35 AssemblerPredicate<"FeatureAtomics", "atomics">; 36 37def HasMultivalue : 38 Predicate<"Subtarget->hasMultivalue()">, 39 AssemblerPredicate<"FeatureMultivalue", "multivalue">; 40 41def HasNontrappingFPToInt : 42 Predicate<"Subtarget->hasNontrappingFPToInt()">, 43 AssemblerPredicate<"FeatureNontrappingFPToInt", "nontrapping-fptoint">; 44 45def NotHasNontrappingFPToInt : 46 Predicate<"!Subtarget->hasNontrappingFPToInt()">, 47 AssemblerPredicate<"!FeatureNontrappingFPToInt", "nontrapping-fptoint">; 48 49def HasSignExt : 50 Predicate<"Subtarget->hasSignExt()">, 51 AssemblerPredicate<"FeatureSignExt", "sign-ext">; 52 53def HasTailCall : 54 Predicate<"Subtarget->hasTailCall()">, 55 AssemblerPredicate<"FeatureTailCall", "tail-call">; 56 57def HasExceptionHandling : 58 Predicate<"Subtarget->hasExceptionHandling()">, 59 AssemblerPredicate<"FeatureExceptionHandling", "exception-handling">; 60 61def HasBulkMemory : 62 Predicate<"Subtarget->hasBulkMemory()">, 63 AssemblerPredicate<"FeatureBulkMemory", "bulk-memory">; 64 65//===----------------------------------------------------------------------===// 66// WebAssembly-specific DAG Node Types. 67//===----------------------------------------------------------------------===// 68 69def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>, 70 SDTCisVT<1, iPTR>]>; 71def SDT_WebAssemblyCallSeqEnd : 72 SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 73def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 74def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>; 75def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 76def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>; 77def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>; 78def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 79 SDTCisPtrTy<0>]>; 80def SDT_WebAssemblyWrapperPIC : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 81 SDTCisPtrTy<0>]>; 82def SDT_WebAssemblyThrow : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 83 84//===----------------------------------------------------------------------===// 85// WebAssembly-specific DAG Nodes. 86//===----------------------------------------------------------------------===// 87 88def WebAssemblycallseq_start : 89 SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart, 90 [SDNPHasChain, SDNPOutGlue]>; 91def WebAssemblycallseq_end : 92 SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd, 93 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 94def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0", 95 SDT_WebAssemblyCall0, 96 [SDNPHasChain, SDNPVariadic]>; 97def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1", 98 SDT_WebAssemblyCall1, 99 [SDNPHasChain, SDNPVariadic]>; 100def WebAssemblyretcall : SDNode<"WebAssemblyISD::RET_CALL", 101 SDT_WebAssemblyCall0, 102 [SDNPHasChain, SDNPVariadic]>; 103def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE", 104 SDT_WebAssemblyBrTable, 105 [SDNPHasChain, SDNPVariadic]>; 106def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT", 107 SDT_WebAssemblyArgument>; 108def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN", 109 SDT_WebAssemblyReturn, [SDNPHasChain]>; 110def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper", 111 SDT_WebAssemblyWrapper>; 112def WebAssemblywrapperPIC : SDNode<"WebAssemblyISD::WrapperPIC", 113 SDT_WebAssemblyWrapperPIC>; 114def WebAssemblythrow : SDNode<"WebAssemblyISD::THROW", SDT_WebAssemblyThrow, 115 [SDNPHasChain, SDNPVariadic]>; 116 117//===----------------------------------------------------------------------===// 118// WebAssembly-specific Operands. 119//===----------------------------------------------------------------------===// 120 121// Default Operand has AsmOperandClass "Imm" which is for integers (and 122// symbols), so specialize one for floats: 123def FPImmAsmOperand : AsmOperandClass { 124 let Name = "FPImm"; 125 let PredicateMethod = "isFPImm"; 126} 127 128class FPOperand<ValueType ty> : Operand<ty> { 129 AsmOperandClass ParserMatchClass = FPImmAsmOperand; 130} 131 132let OperandNamespace = "WebAssembly" in { 133 134let OperandType = "OPERAND_BASIC_BLOCK" in 135def bb_op : Operand<OtherVT>; 136 137let OperandType = "OPERAND_LOCAL" in 138def local_op : Operand<i32>; 139 140let OperandType = "OPERAND_GLOBAL" in 141def global_op : Operand<i32>; 142 143let OperandType = "OPERAND_I32IMM" in 144def i32imm_op : Operand<i32>; 145 146let OperandType = "OPERAND_I64IMM" in 147def i64imm_op : Operand<i64>; 148 149let OperandType = "OPERAND_F32IMM" in 150def f32imm_op : FPOperand<f32>; 151 152let OperandType = "OPERAND_F64IMM" in 153def f64imm_op : FPOperand<f64>; 154 155let OperandType = "OPERAND_VEC_I8IMM" in 156def vec_i8imm_op : Operand<i32>; 157 158let OperandType = "OPERAND_VEC_I16IMM" in 159def vec_i16imm_op : Operand<i32>; 160 161let OperandType = "OPERAND_VEC_I32IMM" in 162def vec_i32imm_op : Operand<i32>; 163 164let OperandType = "OPERAND_VEC_I64IMM" in 165def vec_i64imm_op : Operand<i64>; 166 167let OperandType = "OPERAND_FUNCTION32" in 168def function32_op : Operand<i32>; 169 170let OperandType = "OPERAND_OFFSET32" in 171def offset32_op : Operand<i32>; 172 173let OperandType = "OPERAND_P2ALIGN" in { 174def P2Align : Operand<i32> { 175 let PrintMethod = "printWebAssemblyP2AlignOperand"; 176} 177 178let OperandType = "OPERAND_EVENT" in 179def event_op : Operand<i32>; 180 181} // OperandType = "OPERAND_P2ALIGN" 182 183let OperandType = "OPERAND_SIGNATURE" in 184def Signature : Operand<i32> { 185 let PrintMethod = "printWebAssemblySignatureOperand"; 186} 187 188let OperandType = "OPERAND_TYPEINDEX" in 189def TypeIndex : Operand<i32>; 190 191} // OperandNamespace = "WebAssembly" 192 193//===----------------------------------------------------------------------===// 194// WebAssembly Register to Stack instruction mapping 195//===----------------------------------------------------------------------===// 196 197class StackRel; 198def getStackOpcode : InstrMapping { 199 let FilterClass = "StackRel"; 200 let RowFields = ["BaseName"]; 201 let ColFields = ["StackBased"]; 202 let KeyCol = ["false"]; 203 let ValueCols = [["true"]]; 204} 205 206//===----------------------------------------------------------------------===// 207// WebAssembly Instruction Format Definitions. 208//===----------------------------------------------------------------------===// 209 210include "WebAssemblyInstrFormats.td" 211 212//===----------------------------------------------------------------------===// 213// Additional instructions. 214//===----------------------------------------------------------------------===// 215 216multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> { 217 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = []<Register>, 218 Uses = [ARGUMENTS] in 219 defm ARGUMENT_#vt : 220 I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno), 221 [(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>; 222} 223defm "": ARGUMENT<I32, i32>; 224defm "": ARGUMENT<I64, i64>; 225defm "": ARGUMENT<F32, f32>; 226defm "": ARGUMENT<F64, f64>; 227defm "": ARGUMENT<EXNREF, exnref>; 228 229// local.get and local.set are not generated by instruction selection; they 230// are implied by virtual register uses and defs. 231multiclass LOCAL<WebAssemblyRegClass vt> { 232 let hasSideEffects = 0 in { 233 // COPY is not an actual instruction in wasm, but since we allow local.get and 234 // local.set to be implicit during most of codegen, we can have a COPY which 235 // is actually a no-op because all the work is done in the implied local.get 236 // and local.set. COPYs are eliminated (and replaced with 237 // local.get/local.set) in the ExplicitLocals pass. 238 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in 239 defm COPY_#vt : I<(outs vt:$res), (ins vt:$src), (outs), (ins), [], 240 "local.copy\t$res, $src", "local.copy">; 241 242 // TEE is similar to COPY, but writes two copies of its result. Typically 243 // this would be used to stackify one result and write the other result to a 244 // local. 245 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in 246 defm TEE_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), (outs), (ins), [], 247 "local.tee\t$res, $also, $src", "local.tee">; 248 249 // This is the actual local.get instruction in wasm. These are made explicit 250 // by the ExplicitLocals pass. It has mayLoad because it reads from a wasm 251 // local, which is a side effect not otherwise modeled in LLVM. 252 let mayLoad = 1, isAsCheapAsAMove = 1 in 253 defm LOCAL_GET_#vt : I<(outs vt:$res), (ins local_op:$local), 254 (outs), (ins local_op:$local), [], 255 "local.get\t$res, $local", "local.get\t$local", 0x20>; 256 257 // This is the actual local.set instruction in wasm. These are made explicit 258 // by the ExplicitLocals pass. It has mayStore because it writes to a wasm 259 // local, which is a side effect not otherwise modeled in LLVM. 260 let mayStore = 1, isAsCheapAsAMove = 1 in 261 defm LOCAL_SET_#vt : I<(outs), (ins local_op:$local, vt:$src), 262 (outs), (ins local_op:$local), [], 263 "local.set\t$local, $src", "local.set\t$local", 0x21>; 264 265 // This is the actual local.tee instruction in wasm. TEEs are turned into 266 // LOCAL_TEEs by the ExplicitLocals pass. It has mayStore for the same reason 267 // as LOCAL_SET. 268 let mayStore = 1, isAsCheapAsAMove = 1 in 269 defm LOCAL_TEE_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src), 270 (outs), (ins local_op:$local), [], 271 "local.tee\t$res, $local, $src", "local.tee\t$local", 272 0x22>; 273 274 // Unused values must be dropped in some contexts. 275 defm DROP_#vt : I<(outs), (ins vt:$src), (outs), (ins), [], 276 "drop\t$src", "drop", 0x1a>; 277 278 let mayLoad = 1 in 279 defm GLOBAL_GET_#vt : I<(outs vt:$res), (ins global_op:$local), 280 (outs), (ins global_op:$local), [], 281 "global.get\t$res, $local", "global.get\t$local", 282 0x23>; 283 284 let mayStore = 1 in 285 defm GLOBAL_SET_#vt : I<(outs), (ins global_op:$local, vt:$src), 286 (outs), (ins global_op:$local), [], 287 "global.set\t$local, $src", "global.set\t$local", 288 0x24>; 289 290} // hasSideEffects = 0 291} 292defm "" : LOCAL<I32>; 293defm "" : LOCAL<I64>; 294defm "" : LOCAL<F32>; 295defm "" : LOCAL<F64>; 296defm "" : LOCAL<V128>, Requires<[HasSIMD128]>; 297defm "" : LOCAL<EXNREF>, Requires<[HasExceptionHandling]>; 298 299let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in { 300defm CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm), 301 (outs), (ins i32imm_op:$imm), 302 [(set I32:$res, imm:$imm)], 303 "i32.const\t$res, $imm", "i32.const\t$imm", 0x41>; 304defm CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm), 305 (outs), (ins i64imm_op:$imm), 306 [(set I64:$res, imm:$imm)], 307 "i64.const\t$res, $imm", "i64.const\t$imm", 0x42>; 308defm CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm), 309 (outs), (ins f32imm_op:$imm), 310 [(set F32:$res, fpimm:$imm)], 311 "f32.const\t$res, $imm", "f32.const\t$imm", 0x43>; 312defm CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm), 313 (outs), (ins f64imm_op:$imm), 314 [(set F64:$res, fpimm:$imm)], 315 "f64.const\t$res, $imm", "f64.const\t$imm", 0x44>; 316} // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 317 318def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)), 319 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsNotPIC]>; 320 321def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)), 322 (GLOBAL_GET_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>; 323 324def : Pat<(i32 (WebAssemblywrapperPIC tglobaladdr:$addr)), 325 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>; 326 327def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)), 328 (GLOBAL_GET_I32 texternalsym:$addr)>, Requires<[IsPIC]>; 329 330def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)), 331 (CONST_I32 texternalsym:$addr)>, Requires<[IsNotPIC]>; 332 333def : Pat<(i32 (WebAssemblywrapper mcsym:$sym)), (CONST_I32 mcsym:$sym)>; 334def : Pat<(i64 (WebAssemblywrapper mcsym:$sym)), (CONST_I64 mcsym:$sym)>; 335 336//===----------------------------------------------------------------------===// 337// Additional sets of instructions. 338//===----------------------------------------------------------------------===// 339 340include "WebAssemblyInstrMemory.td" 341include "WebAssemblyInstrCall.td" 342include "WebAssemblyInstrControl.td" 343include "WebAssemblyInstrInteger.td" 344include "WebAssemblyInstrConv.td" 345include "WebAssemblyInstrFloat.td" 346include "WebAssemblyInstrAtomics.td" 347include "WebAssemblyInstrSIMD.td" 348include "WebAssemblyInstrRef.td" 349include "WebAssemblyInstrBulkMemory.td" 350