SystemZISelDAGToDAG.cpp revision 341825
1251607Sdim//===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===// 2251607Sdim// 3251607Sdim// The LLVM Compiler Infrastructure 4251607Sdim// 5251607Sdim// This file is distributed under the University of Illinois Open Source 6251607Sdim// License. See LICENSE.TXT for details. 7251607Sdim// 8251607Sdim//===----------------------------------------------------------------------===// 9251607Sdim// 10251607Sdim// This file defines an instruction selector for the SystemZ target. 11251607Sdim// 12251607Sdim//===----------------------------------------------------------------------===// 13251607Sdim 14251607Sdim#include "SystemZTargetMachine.h" 15261991Sdim#include "llvm/Analysis/AliasAnalysis.h" 16251607Sdim#include "llvm/CodeGen/SelectionDAGISel.h" 17251607Sdim#include "llvm/Support/Debug.h" 18321369Sdim#include "llvm/Support/KnownBits.h" 19251607Sdim#include "llvm/Support/raw_ostream.h" 20251607Sdim 21251607Sdimusing namespace llvm; 22251607Sdim 23276479Sdim#define DEBUG_TYPE "systemz-isel" 24276479Sdim 25251607Sdimnamespace { 26251607Sdim// Used to build addressing modes. 27251607Sdimstruct SystemZAddressingMode { 28251607Sdim // The shape of the address. 29251607Sdim enum AddrForm { 30251607Sdim // base+displacement 31251607Sdim FormBD, 32251607Sdim 33251607Sdim // base+displacement+index for load and store operands 34251607Sdim FormBDXNormal, 35251607Sdim 36251607Sdim // base+displacement+index for load address operands 37251607Sdim FormBDXLA, 38251607Sdim 39251607Sdim // base+displacement+index+ADJDYNALLOC 40251607Sdim FormBDXDynAlloc 41251607Sdim }; 42251607Sdim AddrForm Form; 43251607Sdim 44251607Sdim // The type of displacement. The enum names here correspond directly 45251607Sdim // to the definitions in SystemZOperand.td. We could split them into 46251607Sdim // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it. 47251607Sdim enum DispRange { 48251607Sdim Disp12Only, 49251607Sdim Disp12Pair, 50251607Sdim Disp20Only, 51251607Sdim Disp20Only128, 52251607Sdim Disp20Pair 53251607Sdim }; 54251607Sdim DispRange DR; 55251607Sdim 56251607Sdim // The parts of the address. The address is equivalent to: 57251607Sdim // 58251607Sdim // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0) 59251607Sdim SDValue Base; 60251607Sdim int64_t Disp; 61251607Sdim SDValue Index; 62251607Sdim bool IncludesDynAlloc; 63251607Sdim 64251607Sdim SystemZAddressingMode(AddrForm form, DispRange dr) 65251607Sdim : Form(form), DR(dr), Base(), Disp(0), Index(), 66251607Sdim IncludesDynAlloc(false) {} 67251607Sdim 68251607Sdim // True if the address can have an index register. 69251607Sdim bool hasIndexField() { return Form != FormBD; } 70251607Sdim 71251607Sdim // True if the address can (and must) include ADJDYNALLOC. 72251607Sdim bool isDynAlloc() { return Form == FormBDXDynAlloc; } 73251607Sdim 74251607Sdim void dump() { 75251607Sdim errs() << "SystemZAddressingMode " << this << '\n'; 76251607Sdim 77251607Sdim errs() << " Base "; 78276479Sdim if (Base.getNode()) 79251607Sdim Base.getNode()->dump(); 80251607Sdim else 81251607Sdim errs() << "null\n"; 82251607Sdim 83251607Sdim if (hasIndexField()) { 84251607Sdim errs() << " Index "; 85276479Sdim if (Index.getNode()) 86251607Sdim Index.getNode()->dump(); 87251607Sdim else 88251607Sdim errs() << "null\n"; 89251607Sdim } 90251607Sdim 91251607Sdim errs() << " Disp " << Disp; 92251607Sdim if (IncludesDynAlloc) 93251607Sdim errs() << " + ADJDYNALLOC"; 94251607Sdim errs() << '\n'; 95251607Sdim } 96251607Sdim}; 97251607Sdim 98261991Sdim// Return a mask with Count low bits set. 99261991Sdimstatic uint64_t allOnes(unsigned int Count) { 100288943Sdim assert(Count <= 64); 101288943Sdim if (Count > 63) 102288943Sdim return UINT64_MAX; 103288943Sdim return (uint64_t(1) << Count) - 1; 104261991Sdim} 105261991Sdim 106261991Sdim// Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation 107261991Sdim// given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and 108261991Sdim// Rotate (I5). The combined operand value is effectively: 109261991Sdim// 110261991Sdim// (or (rotl Input, Rotate), ~Mask) 111261991Sdim// 112261991Sdim// for RNSBG and: 113261991Sdim// 114261991Sdim// (and (rotl Input, Rotate), Mask) 115261991Sdim// 116261991Sdim// otherwise. The output value has BitSize bits, although Input may be 117309124Sdim// narrower (in which case the upper bits are don't care), or wider (in which 118309124Sdim// case the result will be truncated as part of the operation). 119261991Sdimstruct RxSBGOperands { 120261991Sdim RxSBGOperands(unsigned Op, SDValue N) 121314564Sdim : Opcode(Op), BitSize(N.getValueSizeInBits()), 122261991Sdim Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63), 123261991Sdim Rotate(0) {} 124261991Sdim 125261991Sdim unsigned Opcode; 126261991Sdim unsigned BitSize; 127261991Sdim uint64_t Mask; 128261991Sdim SDValue Input; 129261991Sdim unsigned Start; 130261991Sdim unsigned End; 131261991Sdim unsigned Rotate; 132261991Sdim}; 133261991Sdim 134251607Sdimclass SystemZDAGToDAGISel : public SelectionDAGISel { 135288943Sdim const SystemZSubtarget *Subtarget; 136251607Sdim 137251607Sdim // Used by SystemZOperands.td to create integer constants. 138261991Sdim inline SDValue getImm(const SDNode *Node, uint64_t Imm) const { 139288943Sdim return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0)); 140251607Sdim } 141251607Sdim 142261991Sdim const SystemZTargetMachine &getTargetMachine() const { 143261991Sdim return static_cast<const SystemZTargetMachine &>(TM); 144261991Sdim } 145261991Sdim 146261991Sdim const SystemZInstrInfo *getInstrInfo() const { 147288943Sdim return Subtarget->getInstrInfo(); 148261991Sdim } 149261991Sdim 150251607Sdim // Try to fold more of the base or index of AM into AM, where IsBase 151251607Sdim // selects between the base and index. 152261991Sdim bool expandAddress(SystemZAddressingMode &AM, bool IsBase) const; 153251607Sdim 154251607Sdim // Try to describe N in AM, returning true on success. 155261991Sdim bool selectAddress(SDValue N, SystemZAddressingMode &AM) const; 156251607Sdim 157251607Sdim // Extract individual target operands from matched address AM. 158251607Sdim void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 159261991Sdim SDValue &Base, SDValue &Disp) const; 160251607Sdim void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 161261991Sdim SDValue &Base, SDValue &Disp, SDValue &Index) const; 162251607Sdim 163251607Sdim // Try to match Addr as a FormBD address with displacement type DR. 164251607Sdim // Return true on success, storing the base and displacement in 165251607Sdim // Base and Disp respectively. 166251607Sdim bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 167261991Sdim SDValue &Base, SDValue &Disp) const; 168251607Sdim 169261991Sdim // Try to match Addr as a FormBDX address with displacement type DR. 170261991Sdim // Return true on success and if the result had no index. Store the 171261991Sdim // base and displacement in Base and Disp respectively. 172261991Sdim bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 173261991Sdim SDValue &Base, SDValue &Disp) const; 174261991Sdim 175251607Sdim // Try to match Addr as a FormBDX* address of form Form with 176251607Sdim // displacement type DR. Return true on success, storing the base, 177251607Sdim // displacement and index in Base, Disp and Index respectively. 178251607Sdim bool selectBDXAddr(SystemZAddressingMode::AddrForm Form, 179251607Sdim SystemZAddressingMode::DispRange DR, SDValue Addr, 180261991Sdim SDValue &Base, SDValue &Disp, SDValue &Index) const; 181251607Sdim 182251607Sdim // PC-relative address matching routines used by SystemZOperands.td. 183261991Sdim bool selectPCRelAddress(SDValue Addr, SDValue &Target) const { 184261991Sdim if (SystemZISD::isPCREL(Addr.getOpcode())) { 185251607Sdim Target = Addr.getOperand(0); 186251607Sdim return true; 187251607Sdim } 188251607Sdim return false; 189251607Sdim } 190251607Sdim 191251607Sdim // BD matching routines used by SystemZOperands.td. 192261991Sdim bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) const { 193251607Sdim return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp); 194251607Sdim } 195261991Sdim bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 196251607Sdim return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp); 197251607Sdim } 198261991Sdim bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) const { 199251607Sdim return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp); 200251607Sdim } 201261991Sdim bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 202251607Sdim return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp); 203251607Sdim } 204251607Sdim 205261991Sdim // MVI matching routines used by SystemZOperands.td. 206261991Sdim bool selectMVIAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 207261991Sdim return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp); 208261991Sdim } 209261991Sdim bool selectMVIAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 210261991Sdim return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp); 211261991Sdim } 212261991Sdim 213251607Sdim // BDX matching routines used by SystemZOperands.td. 214251607Sdim bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 215261991Sdim SDValue &Index) const { 216251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 217251607Sdim SystemZAddressingMode::Disp12Only, 218251607Sdim Addr, Base, Disp, Index); 219251607Sdim } 220251607Sdim bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 221261991Sdim SDValue &Index) const { 222251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 223251607Sdim SystemZAddressingMode::Disp12Pair, 224251607Sdim Addr, Base, Disp, Index); 225251607Sdim } 226251607Sdim bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 227261991Sdim SDValue &Index) const { 228251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc, 229251607Sdim SystemZAddressingMode::Disp12Only, 230251607Sdim Addr, Base, Disp, Index); 231251607Sdim } 232251607Sdim bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp, 233261991Sdim SDValue &Index) const { 234251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 235251607Sdim SystemZAddressingMode::Disp20Only, 236251607Sdim Addr, Base, Disp, Index); 237251607Sdim } 238251607Sdim bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp, 239261991Sdim SDValue &Index) const { 240251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 241251607Sdim SystemZAddressingMode::Disp20Only128, 242251607Sdim Addr, Base, Disp, Index); 243251607Sdim } 244251607Sdim bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 245261991Sdim SDValue &Index) const { 246251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 247251607Sdim SystemZAddressingMode::Disp20Pair, 248251607Sdim Addr, Base, Disp, Index); 249251607Sdim } 250251607Sdim bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 251261991Sdim SDValue &Index) const { 252251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 253251607Sdim SystemZAddressingMode::Disp12Pair, 254251607Sdim Addr, Base, Disp, Index); 255251607Sdim } 256251607Sdim bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 257261991Sdim SDValue &Index) const { 258251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 259251607Sdim SystemZAddressingMode::Disp20Pair, 260251607Sdim Addr, Base, Disp, Index); 261251607Sdim } 262251607Sdim 263288943Sdim // Try to match Addr as an address with a base, 12-bit displacement 264288943Sdim // and index, where the index is element Elem of a vector. 265288943Sdim // Return true on success, storing the base, displacement and vector 266288943Sdim // in Base, Disp and Index respectively. 267288943Sdim bool selectBDVAddr12Only(SDValue Addr, SDValue Elem, SDValue &Base, 268288943Sdim SDValue &Disp, SDValue &Index) const; 269288943Sdim 270261991Sdim // Check whether (or Op (and X InsertMask)) is effectively an insertion 271261991Sdim // of X into bits InsertMask of some Y != Op. Return true if so and 272261991Sdim // set Op to that Y. 273261991Sdim bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask) const; 274261991Sdim 275261991Sdim // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used. 276261991Sdim // Return true on success. 277261991Sdim bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) const; 278261991Sdim 279261991Sdim // Try to fold some of RxSBG.Input into other fields of RxSBG. 280261991Sdim // Return true on success. 281261991Sdim bool expandRxSBG(RxSBGOperands &RxSBG) const; 282261991Sdim 283261991Sdim // Return an undefined value of type VT. 284309124Sdim SDValue getUNDEF(const SDLoc &DL, EVT VT) const; 285261991Sdim 286261991Sdim // Convert N to VT, if it isn't already. 287309124Sdim SDValue convertTo(const SDLoc &DL, EVT VT, SDValue N) const; 288261991Sdim 289261991Sdim // Try to implement AND or shift node N using RISBG with the zero flag set. 290261991Sdim // Return the selected node on success, otherwise return null. 291309124Sdim bool tryRISBGZero(SDNode *N); 292261991Sdim 293261991Sdim // Try to use RISBG or Opcode to implement OR or XOR node N. 294261991Sdim // Return the selected node on success, otherwise return null. 295309124Sdim bool tryRxSBG(SDNode *N, unsigned Opcode); 296261991Sdim 297251607Sdim // If Op0 is null, then Node is a constant that can be loaded using: 298251607Sdim // 299251607Sdim // (Opcode UpperVal LowerVal) 300251607Sdim // 301251607Sdim // If Op0 is nonnull, then Node can be implemented using: 302251607Sdim // 303251607Sdim // (Opcode (Opcode Op0 UpperVal) LowerVal) 304309124Sdim void splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 305309124Sdim uint64_t UpperVal, uint64_t LowerVal); 306251607Sdim 307288943Sdim // Try to use gather instruction Opcode to implement vector insertion N. 308309124Sdim bool tryGather(SDNode *N, unsigned Opcode); 309288943Sdim 310288943Sdim // Try to use scatter instruction Opcode to implement store Store. 311309124Sdim bool tryScatter(StoreSDNode *Store, unsigned Opcode); 312288943Sdim 313341825Sdim // Change a chain of {load; op; store} of the same value into a simple op 314341825Sdim // through memory of that value, if the uses of the modified value and its 315341825Sdim // address are suitable. 316341825Sdim bool tryFoldLoadStoreIntoMemOperand(SDNode *Node); 317341825Sdim 318261991Sdim // Return true if Load and Store are loads and stores of the same size 319261991Sdim // and are guaranteed not to overlap. Such operations can be implemented 320261991Sdim // using block (SS-format) instructions. 321261991Sdim // 322261991Sdim // Partial overlap would lead to incorrect code, since the block operations 323261991Sdim // are logically bytewise, even though they have a fast path for the 324261991Sdim // non-overlapping case. We also need to avoid full overlap (i.e. two 325261991Sdim // addresses that might be equal at run time) because although that case 326261991Sdim // would be handled correctly, it might be implemented by millicode. 327261991Sdim bool canUseBlockOperation(StoreSDNode *Store, LoadSDNode *Load) const; 328261991Sdim 329261991Sdim // N is a (store (load Y), X) pattern. Return true if it can use an MVC 330261991Sdim // from Y to X. 331261991Sdim bool storeLoadCanUseMVC(SDNode *N) const; 332261991Sdim 333261991Sdim // N is a (store (op (load A[0]), (load A[1])), X) pattern. Return true 334261991Sdim // if A[1 - I] == X and if N can use a block operation like NC from A[I] 335261991Sdim // to X. 336261991Sdim bool storeLoadCanUseBlockBinary(SDNode *N, unsigned I) const; 337261991Sdim 338341825Sdim // Try to expand a boolean SELECT_CCMASK using an IPM sequence. 339341825Sdim SDValue expandSelectBoolean(SDNode *Node); 340341825Sdim 341251607Sdimpublic: 342251607Sdim SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) 343288943Sdim : SelectionDAGISel(TM, OptLevel) {} 344251607Sdim 345288943Sdim bool runOnMachineFunction(MachineFunction &MF) override { 346288943Sdim Subtarget = &MF.getSubtarget<SystemZSubtarget>(); 347288943Sdim return SelectionDAGISel::runOnMachineFunction(MF); 348288943Sdim } 349288943Sdim 350251607Sdim // Override MachineFunctionPass. 351314564Sdim StringRef getPassName() const override { 352251607Sdim return "SystemZ DAG->DAG Pattern Instruction Selection"; 353251607Sdim } 354251607Sdim 355251607Sdim // Override SelectionDAGISel. 356309124Sdim void Select(SDNode *Node) override; 357288943Sdim bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 358276479Sdim std::vector<SDValue> &OutOps) override; 359341825Sdim bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override; 360341825Sdim void PreprocessISelDAG() override; 361251607Sdim 362251607Sdim // Include the pieces autogenerated from the target description. 363251607Sdim #include "SystemZGenDAGISel.inc" 364251607Sdim}; 365251607Sdim} // end anonymous namespace 366251607Sdim 367251607SdimFunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, 368251607Sdim CodeGenOpt::Level OptLevel) { 369251607Sdim return new SystemZDAGToDAGISel(TM, OptLevel); 370251607Sdim} 371251607Sdim 372251607Sdim// Return true if Val should be selected as a displacement for an address 373251607Sdim// with range DR. Here we're interested in the range of both the instruction 374251607Sdim// described by DR and of any pairing instruction. 375251607Sdimstatic bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 376251607Sdim switch (DR) { 377251607Sdim case SystemZAddressingMode::Disp12Only: 378251607Sdim return isUInt<12>(Val); 379251607Sdim 380251607Sdim case SystemZAddressingMode::Disp12Pair: 381251607Sdim case SystemZAddressingMode::Disp20Only: 382251607Sdim case SystemZAddressingMode::Disp20Pair: 383251607Sdim return isInt<20>(Val); 384251607Sdim 385251607Sdim case SystemZAddressingMode::Disp20Only128: 386251607Sdim return isInt<20>(Val) && isInt<20>(Val + 8); 387251607Sdim } 388251607Sdim llvm_unreachable("Unhandled displacement range"); 389251607Sdim} 390251607Sdim 391251607Sdim// Change the base or index in AM to Value, where IsBase selects 392251607Sdim// between the base and index. 393251607Sdimstatic void changeComponent(SystemZAddressingMode &AM, bool IsBase, 394251607Sdim SDValue Value) { 395251607Sdim if (IsBase) 396251607Sdim AM.Base = Value; 397251607Sdim else 398251607Sdim AM.Index = Value; 399251607Sdim} 400251607Sdim 401251607Sdim// The base or index of AM is equivalent to Value + ADJDYNALLOC, 402251607Sdim// where IsBase selects between the base and index. Try to fold the 403251607Sdim// ADJDYNALLOC into AM. 404251607Sdimstatic bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, 405251607Sdim SDValue Value) { 406251607Sdim if (AM.isDynAlloc() && !AM.IncludesDynAlloc) { 407251607Sdim changeComponent(AM, IsBase, Value); 408251607Sdim AM.IncludesDynAlloc = true; 409251607Sdim return true; 410251607Sdim } 411251607Sdim return false; 412251607Sdim} 413251607Sdim 414251607Sdim// The base of AM is equivalent to Base + Index. Try to use Index as 415251607Sdim// the index register. 416251607Sdimstatic bool expandIndex(SystemZAddressingMode &AM, SDValue Base, 417251607Sdim SDValue Index) { 418251607Sdim if (AM.hasIndexField() && !AM.Index.getNode()) { 419251607Sdim AM.Base = Base; 420251607Sdim AM.Index = Index; 421251607Sdim return true; 422251607Sdim } 423251607Sdim return false; 424251607Sdim} 425251607Sdim 426251607Sdim// The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 427251607Sdim// between the base and index. Try to fold Op1 into AM's displacement. 428251607Sdimstatic bool expandDisp(SystemZAddressingMode &AM, bool IsBase, 429261991Sdim SDValue Op0, uint64_t Op1) { 430251607Sdim // First try adjusting the displacement. 431261991Sdim int64_t TestDisp = AM.Disp + Op1; 432251607Sdim if (selectDisp(AM.DR, TestDisp)) { 433251607Sdim changeComponent(AM, IsBase, Op0); 434251607Sdim AM.Disp = TestDisp; 435251607Sdim return true; 436251607Sdim } 437251607Sdim 438251607Sdim // We could consider forcing the displacement into a register and 439251607Sdim // using it as an index, but it would need to be carefully tuned. 440251607Sdim return false; 441251607Sdim} 442251607Sdim 443251607Sdimbool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM, 444261991Sdim bool IsBase) const { 445251607Sdim SDValue N = IsBase ? AM.Base : AM.Index; 446251607Sdim unsigned Opcode = N.getOpcode(); 447251607Sdim if (Opcode == ISD::TRUNCATE) { 448251607Sdim N = N.getOperand(0); 449251607Sdim Opcode = N.getOpcode(); 450251607Sdim } 451251607Sdim if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) { 452251607Sdim SDValue Op0 = N.getOperand(0); 453251607Sdim SDValue Op1 = N.getOperand(1); 454251607Sdim 455251607Sdim unsigned Op0Code = Op0->getOpcode(); 456251607Sdim unsigned Op1Code = Op1->getOpcode(); 457251607Sdim 458251607Sdim if (Op0Code == SystemZISD::ADJDYNALLOC) 459251607Sdim return expandAdjDynAlloc(AM, IsBase, Op1); 460251607Sdim if (Op1Code == SystemZISD::ADJDYNALLOC) 461251607Sdim return expandAdjDynAlloc(AM, IsBase, Op0); 462251607Sdim 463251607Sdim if (Op0Code == ISD::Constant) 464261991Sdim return expandDisp(AM, IsBase, Op1, 465261991Sdim cast<ConstantSDNode>(Op0)->getSExtValue()); 466251607Sdim if (Op1Code == ISD::Constant) 467261991Sdim return expandDisp(AM, IsBase, Op0, 468261991Sdim cast<ConstantSDNode>(Op1)->getSExtValue()); 469251607Sdim 470251607Sdim if (IsBase && expandIndex(AM, Op0, Op1)) 471251607Sdim return true; 472251607Sdim } 473261991Sdim if (Opcode == SystemZISD::PCREL_OFFSET) { 474261991Sdim SDValue Full = N.getOperand(0); 475261991Sdim SDValue Base = N.getOperand(1); 476261991Sdim SDValue Anchor = Base.getOperand(0); 477261991Sdim uint64_t Offset = (cast<GlobalAddressSDNode>(Full)->getOffset() - 478261991Sdim cast<GlobalAddressSDNode>(Anchor)->getOffset()); 479261991Sdim return expandDisp(AM, IsBase, Base, Offset); 480261991Sdim } 481251607Sdim return false; 482251607Sdim} 483251607Sdim 484251607Sdim// Return true if an instruction with displacement range DR should be 485251607Sdim// used for displacement value Val. selectDisp(DR, Val) must already hold. 486251607Sdimstatic bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 487251607Sdim assert(selectDisp(DR, Val) && "Invalid displacement"); 488251607Sdim switch (DR) { 489251607Sdim case SystemZAddressingMode::Disp12Only: 490251607Sdim case SystemZAddressingMode::Disp20Only: 491251607Sdim case SystemZAddressingMode::Disp20Only128: 492251607Sdim return true; 493251607Sdim 494251607Sdim case SystemZAddressingMode::Disp12Pair: 495251607Sdim // Use the other instruction if the displacement is too large. 496251607Sdim return isUInt<12>(Val); 497251607Sdim 498251607Sdim case SystemZAddressingMode::Disp20Pair: 499251607Sdim // Use the other instruction if the displacement is small enough. 500251607Sdim return !isUInt<12>(Val); 501251607Sdim } 502251607Sdim llvm_unreachable("Unhandled displacement range"); 503251607Sdim} 504251607Sdim 505251607Sdim// Return true if Base + Disp + Index should be performed by LA(Y). 506251607Sdimstatic bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) { 507251607Sdim // Don't use LA(Y) for constants. 508251607Sdim if (!Base) 509251607Sdim return false; 510251607Sdim 511251607Sdim // Always use LA(Y) for frame addresses, since we know that the destination 512251607Sdim // register is almost always (perhaps always) going to be different from 513251607Sdim // the frame register. 514251607Sdim if (Base->getOpcode() == ISD::FrameIndex) 515251607Sdim return true; 516251607Sdim 517251607Sdim if (Disp) { 518251607Sdim // Always use LA(Y) if there is a base, displacement and index. 519251607Sdim if (Index) 520251607Sdim return true; 521251607Sdim 522251607Sdim // Always use LA if the displacement is small enough. It should always 523251607Sdim // be no worse than AGHI (and better if it avoids a move). 524251607Sdim if (isUInt<12>(Disp)) 525251607Sdim return true; 526251607Sdim 527251607Sdim // For similar reasons, always use LAY if the constant is too big for AGHI. 528251607Sdim // LAY should be no worse than AGFI. 529251607Sdim if (!isInt<16>(Disp)) 530251607Sdim return true; 531251607Sdim } else { 532251607Sdim // Don't use LA for plain registers. 533251607Sdim if (!Index) 534251607Sdim return false; 535251607Sdim 536251607Sdim // Don't use LA for plain addition if the index operand is only used 537251607Sdim // once. It should be a natural two-operand addition in that case. 538251607Sdim if (Index->hasOneUse()) 539251607Sdim return false; 540251607Sdim 541251607Sdim // Prefer addition if the second operation is sign-extended, in the 542251607Sdim // hope of using AGF. 543251607Sdim unsigned IndexOpcode = Index->getOpcode(); 544251607Sdim if (IndexOpcode == ISD::SIGN_EXTEND || 545251607Sdim IndexOpcode == ISD::SIGN_EXTEND_INREG) 546251607Sdim return false; 547251607Sdim } 548251607Sdim 549251607Sdim // Don't use LA for two-operand addition if either operand is only 550251607Sdim // used once. The addition instructions are better in that case. 551251607Sdim if (Base->hasOneUse()) 552251607Sdim return false; 553251607Sdim 554251607Sdim return true; 555251607Sdim} 556251607Sdim 557251607Sdim// Return true if Addr is suitable for AM, updating AM if so. 558251607Sdimbool SystemZDAGToDAGISel::selectAddress(SDValue Addr, 559261991Sdim SystemZAddressingMode &AM) const { 560251607Sdim // Start out assuming that the address will need to be loaded separately, 561251607Sdim // then try to extend it as much as we can. 562251607Sdim AM.Base = Addr; 563251607Sdim 564251607Sdim // First try treating the address as a constant. 565251607Sdim if (Addr.getOpcode() == ISD::Constant && 566261991Sdim expandDisp(AM, true, SDValue(), 567261991Sdim cast<ConstantSDNode>(Addr)->getSExtValue())) 568251607Sdim ; 569309124Sdim // Also see if it's a bare ADJDYNALLOC. 570309124Sdim else if (Addr.getOpcode() == SystemZISD::ADJDYNALLOC && 571309124Sdim expandAdjDynAlloc(AM, true, SDValue())) 572309124Sdim ; 573251607Sdim else 574251607Sdim // Otherwise try expanding each component. 575251607Sdim while (expandAddress(AM, true) || 576251607Sdim (AM.Index.getNode() && expandAddress(AM, false))) 577251607Sdim continue; 578251607Sdim 579251607Sdim // Reject cases where it isn't profitable to use LA(Y). 580251607Sdim if (AM.Form == SystemZAddressingMode::FormBDXLA && 581251607Sdim !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode())) 582251607Sdim return false; 583251607Sdim 584251607Sdim // Reject cases where the other instruction in a pair should be used. 585251607Sdim if (!isValidDisp(AM.DR, AM.Disp)) 586251607Sdim return false; 587251607Sdim 588251607Sdim // Make sure that ADJDYNALLOC is included where necessary. 589251607Sdim if (AM.isDynAlloc() && !AM.IncludesDynAlloc) 590251607Sdim return false; 591251607Sdim 592341825Sdim LLVM_DEBUG(AM.dump()); 593251607Sdim return true; 594251607Sdim} 595251607Sdim 596251607Sdim// Insert a node into the DAG at least before Pos. This will reposition 597251607Sdim// the node as needed, and will assign it a node ID that is <= Pos's ID. 598251607Sdim// Note that this does *not* preserve the uniqueness of node IDs! 599251607Sdim// The selection DAG must no longer depend on their uniqueness when this 600251607Sdim// function is used. 601251607Sdimstatic void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) { 602341825Sdim if (N->getNodeId() == -1 || 603341825Sdim (SelectionDAGISel::getUninvalidatedNodeId(N.getNode()) > 604341825Sdim SelectionDAGISel::getUninvalidatedNodeId(Pos))) { 605296417Sdim DAG->RepositionNode(Pos->getIterator(), N.getNode()); 606341825Sdim // Mark Node as invalid for pruning as after this it may be a successor to a 607341825Sdim // selected node but otherwise be in the same position of Pos. 608341825Sdim // Conservatively mark it with the same -abs(Id) to assure node id 609341825Sdim // invariant is preserved. 610341825Sdim N->setNodeId(Pos->getNodeId()); 611341825Sdim SelectionDAGISel::InvalidateNodeId(N.getNode()); 612251607Sdim } 613251607Sdim} 614251607Sdim 615251607Sdimvoid SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 616251607Sdim EVT VT, SDValue &Base, 617261991Sdim SDValue &Disp) const { 618251607Sdim Base = AM.Base; 619251607Sdim if (!Base.getNode()) 620251607Sdim // Register 0 means "no base". This is mostly useful for shifts. 621251607Sdim Base = CurDAG->getRegister(0, VT); 622251607Sdim else if (Base.getOpcode() == ISD::FrameIndex) { 623251607Sdim // Lower a FrameIndex to a TargetFrameIndex. 624251607Sdim int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex(); 625251607Sdim Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); 626251607Sdim } else if (Base.getValueType() != VT) { 627251607Sdim // Truncate values from i64 to i32, for shifts. 628251607Sdim assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 && 629251607Sdim "Unexpected truncation"); 630261991Sdim SDLoc DL(Base); 631251607Sdim SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); 632251607Sdim insertDAGNode(CurDAG, Base.getNode(), Trunc); 633251607Sdim Base = Trunc; 634251607Sdim } 635251607Sdim 636251607Sdim // Lower the displacement to a TargetConstant. 637288943Sdim Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT); 638251607Sdim} 639251607Sdim 640251607Sdimvoid SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 641251607Sdim EVT VT, SDValue &Base, 642261991Sdim SDValue &Disp, 643261991Sdim SDValue &Index) const { 644251607Sdim getAddressOperands(AM, VT, Base, Disp); 645251607Sdim 646251607Sdim Index = AM.Index; 647251607Sdim if (!Index.getNode()) 648251607Sdim // Register 0 means "no index". 649251607Sdim Index = CurDAG->getRegister(0, VT); 650251607Sdim} 651251607Sdim 652251607Sdimbool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR, 653251607Sdim SDValue Addr, SDValue &Base, 654261991Sdim SDValue &Disp) const { 655251607Sdim SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR); 656251607Sdim if (!selectAddress(Addr, AM)) 657251607Sdim return false; 658251607Sdim 659251607Sdim getAddressOperands(AM, Addr.getValueType(), Base, Disp); 660251607Sdim return true; 661251607Sdim} 662251607Sdim 663261991Sdimbool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR, 664261991Sdim SDValue Addr, SDValue &Base, 665261991Sdim SDValue &Disp) const { 666261991Sdim SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR); 667261991Sdim if (!selectAddress(Addr, AM) || AM.Index.getNode()) 668261991Sdim return false; 669261991Sdim 670261991Sdim getAddressOperands(AM, Addr.getValueType(), Base, Disp); 671261991Sdim return true; 672261991Sdim} 673261991Sdim 674251607Sdimbool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form, 675251607Sdim SystemZAddressingMode::DispRange DR, 676251607Sdim SDValue Addr, SDValue &Base, 677261991Sdim SDValue &Disp, SDValue &Index) const { 678251607Sdim SystemZAddressingMode AM(Form, DR); 679251607Sdim if (!selectAddress(Addr, AM)) 680251607Sdim return false; 681251607Sdim 682251607Sdim getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index); 683251607Sdim return true; 684251607Sdim} 685251607Sdim 686288943Sdimbool SystemZDAGToDAGISel::selectBDVAddr12Only(SDValue Addr, SDValue Elem, 687288943Sdim SDValue &Base, 688288943Sdim SDValue &Disp, 689288943Sdim SDValue &Index) const { 690288943Sdim SDValue Regs[2]; 691288943Sdim if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) && 692288943Sdim Regs[0].getNode() && Regs[1].getNode()) { 693288943Sdim for (unsigned int I = 0; I < 2; ++I) { 694288943Sdim Base = Regs[I]; 695288943Sdim Index = Regs[1 - I]; 696288943Sdim // We can't tell here whether the index vector has the right type 697288943Sdim // for the access; the caller needs to do that instead. 698288943Sdim if (Index.getOpcode() == ISD::ZERO_EXTEND) 699288943Sdim Index = Index.getOperand(0); 700288943Sdim if (Index.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 701288943Sdim Index.getOperand(1) == Elem) { 702288943Sdim Index = Index.getOperand(0); 703288943Sdim return true; 704288943Sdim } 705288943Sdim } 706288943Sdim } 707288943Sdim return false; 708288943Sdim} 709288943Sdim 710261991Sdimbool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op, 711261991Sdim uint64_t InsertMask) const { 712261991Sdim // We're only interested in cases where the insertion is into some operand 713261991Sdim // of Op, rather than into Op itself. The only useful case is an AND. 714261991Sdim if (Op.getOpcode() != ISD::AND) 715261991Sdim return false; 716261991Sdim 717261991Sdim // We need a constant mask. 718276479Sdim auto *MaskNode = dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode()); 719261991Sdim if (!MaskNode) 720261991Sdim return false; 721261991Sdim 722261991Sdim // It's not an insertion of Op.getOperand(0) if the two masks overlap. 723261991Sdim uint64_t AndMask = MaskNode->getZExtValue(); 724261991Sdim if (InsertMask & AndMask) 725261991Sdim return false; 726261991Sdim 727261991Sdim // It's only an insertion if all bits are covered or are known to be zero. 728261991Sdim // The inner check covers all cases but is more expensive. 729314564Sdim uint64_t Used = allOnes(Op.getValueSizeInBits()); 730261991Sdim if (Used != (AndMask | InsertMask)) { 731321369Sdim KnownBits Known; 732321369Sdim CurDAG->computeKnownBits(Op.getOperand(0), Known); 733321369Sdim if (Used != (AndMask | InsertMask | Known.Zero.getZExtValue())) 734261991Sdim return false; 735261991Sdim } 736261991Sdim 737261991Sdim Op = Op.getOperand(0); 738261991Sdim return true; 739261991Sdim} 740261991Sdim 741261991Sdimbool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG, 742261991Sdim uint64_t Mask) const { 743261991Sdim const SystemZInstrInfo *TII = getInstrInfo(); 744261991Sdim if (RxSBG.Rotate != 0) 745261991Sdim Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)); 746261991Sdim Mask &= RxSBG.Mask; 747261991Sdim if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) { 748261991Sdim RxSBG.Mask = Mask; 749261991Sdim return true; 750261991Sdim } 751261991Sdim return false; 752261991Sdim} 753261991Sdim 754261991Sdim// Return true if any bits of (RxSBG.Input & Mask) are significant. 755261991Sdimstatic bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask) { 756261991Sdim // Rotate the mask in the same way as RxSBG.Input is rotated. 757261991Sdim if (RxSBG.Rotate != 0) 758261991Sdim Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate))); 759261991Sdim return (Mask & RxSBG.Mask) != 0; 760261991Sdim} 761261991Sdim 762261991Sdimbool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const { 763261991Sdim SDValue N = RxSBG.Input; 764261991Sdim unsigned Opcode = N.getOpcode(); 765261991Sdim switch (Opcode) { 766309124Sdim case ISD::TRUNCATE: { 767309124Sdim if (RxSBG.Opcode == SystemZ::RNSBG) 768309124Sdim return false; 769314564Sdim uint64_t BitSize = N.getValueSizeInBits(); 770309124Sdim uint64_t Mask = allOnes(BitSize); 771309124Sdim if (!refineRxSBGMask(RxSBG, Mask)) 772309124Sdim return false; 773309124Sdim RxSBG.Input = N.getOperand(0); 774309124Sdim return true; 775309124Sdim } 776261991Sdim case ISD::AND: { 777261991Sdim if (RxSBG.Opcode == SystemZ::RNSBG) 778261991Sdim return false; 779261991Sdim 780276479Sdim auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 781261991Sdim if (!MaskNode) 782261991Sdim return false; 783261991Sdim 784261991Sdim SDValue Input = N.getOperand(0); 785261991Sdim uint64_t Mask = MaskNode->getZExtValue(); 786261991Sdim if (!refineRxSBGMask(RxSBG, Mask)) { 787261991Sdim // If some bits of Input are already known zeros, those bits will have 788261991Sdim // been removed from the mask. See if adding them back in makes the 789261991Sdim // mask suitable. 790321369Sdim KnownBits Known; 791321369Sdim CurDAG->computeKnownBits(Input, Known); 792321369Sdim Mask |= Known.Zero.getZExtValue(); 793261991Sdim if (!refineRxSBGMask(RxSBG, Mask)) 794261991Sdim return false; 795261991Sdim } 796261991Sdim RxSBG.Input = Input; 797261991Sdim return true; 798261991Sdim } 799261991Sdim 800261991Sdim case ISD::OR: { 801261991Sdim if (RxSBG.Opcode != SystemZ::RNSBG) 802261991Sdim return false; 803261991Sdim 804276479Sdim auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 805261991Sdim if (!MaskNode) 806261991Sdim return false; 807261991Sdim 808261991Sdim SDValue Input = N.getOperand(0); 809261991Sdim uint64_t Mask = ~MaskNode->getZExtValue(); 810261991Sdim if (!refineRxSBGMask(RxSBG, Mask)) { 811261991Sdim // If some bits of Input are already known ones, those bits will have 812261991Sdim // been removed from the mask. See if adding them back in makes the 813261991Sdim // mask suitable. 814321369Sdim KnownBits Known; 815321369Sdim CurDAG->computeKnownBits(Input, Known); 816321369Sdim Mask &= ~Known.One.getZExtValue(); 817261991Sdim if (!refineRxSBGMask(RxSBG, Mask)) 818261991Sdim return false; 819261991Sdim } 820261991Sdim RxSBG.Input = Input; 821261991Sdim return true; 822261991Sdim } 823261991Sdim 824261991Sdim case ISD::ROTL: { 825261991Sdim // Any 64-bit rotate left can be merged into the RxSBG. 826261991Sdim if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64) 827261991Sdim return false; 828276479Sdim auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 829261991Sdim if (!CountNode) 830261991Sdim return false; 831261991Sdim 832261991Sdim RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63; 833261991Sdim RxSBG.Input = N.getOperand(0); 834261991Sdim return true; 835261991Sdim } 836296417Sdim 837276479Sdim case ISD::ANY_EXTEND: 838276479Sdim // Bits above the extended operand are don't-care. 839276479Sdim RxSBG.Input = N.getOperand(0); 840276479Sdim return true; 841276479Sdim 842261991Sdim case ISD::ZERO_EXTEND: 843276479Sdim if (RxSBG.Opcode != SystemZ::RNSBG) { 844276479Sdim // Restrict the mask to the extended operand. 845314564Sdim unsigned InnerBitSize = N.getOperand(0).getValueSizeInBits(); 846276479Sdim if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize))) 847276479Sdim return false; 848276479Sdim 849276479Sdim RxSBG.Input = N.getOperand(0); 850276479Sdim return true; 851276479Sdim } 852314564Sdim LLVM_FALLTHROUGH; 853296417Sdim 854276479Sdim case ISD::SIGN_EXTEND: { 855261991Sdim // Check that the extension bits are don't-care (i.e. are masked out 856261991Sdim // by the final mask). 857327952Sdim unsigned BitSize = N.getValueSizeInBits(); 858314564Sdim unsigned InnerBitSize = N.getOperand(0).getValueSizeInBits(); 859327952Sdim if (maskMatters(RxSBG, allOnes(BitSize) - allOnes(InnerBitSize))) { 860327952Sdim // In the case where only the sign bit is active, increase Rotate with 861327952Sdim // the extension width. 862327952Sdim if (RxSBG.Mask == 1 && RxSBG.Rotate == 1) 863327952Sdim RxSBG.Rotate += (BitSize - InnerBitSize); 864327952Sdim else 865327952Sdim return false; 866327952Sdim } 867261991Sdim 868261991Sdim RxSBG.Input = N.getOperand(0); 869261991Sdim return true; 870261991Sdim } 871261991Sdim 872261991Sdim case ISD::SHL: { 873276479Sdim auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 874261991Sdim if (!CountNode) 875261991Sdim return false; 876261991Sdim 877261991Sdim uint64_t Count = CountNode->getZExtValue(); 878314564Sdim unsigned BitSize = N.getValueSizeInBits(); 879261991Sdim if (Count < 1 || Count >= BitSize) 880261991Sdim return false; 881261991Sdim 882261991Sdim if (RxSBG.Opcode == SystemZ::RNSBG) { 883261991Sdim // Treat (shl X, count) as (rotl X, size-count) as long as the bottom 884261991Sdim // count bits from RxSBG.Input are ignored. 885261991Sdim if (maskMatters(RxSBG, allOnes(Count))) 886261991Sdim return false; 887261991Sdim } else { 888261991Sdim // Treat (shl X, count) as (and (rotl X, count), ~0<<count). 889261991Sdim if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count)) 890261991Sdim return false; 891261991Sdim } 892261991Sdim 893261991Sdim RxSBG.Rotate = (RxSBG.Rotate + Count) & 63; 894261991Sdim RxSBG.Input = N.getOperand(0); 895261991Sdim return true; 896261991Sdim } 897261991Sdim 898261991Sdim case ISD::SRL: 899261991Sdim case ISD::SRA: { 900276479Sdim auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 901261991Sdim if (!CountNode) 902261991Sdim return false; 903261991Sdim 904261991Sdim uint64_t Count = CountNode->getZExtValue(); 905314564Sdim unsigned BitSize = N.getValueSizeInBits(); 906261991Sdim if (Count < 1 || Count >= BitSize) 907261991Sdim return false; 908261991Sdim 909261991Sdim if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { 910261991Sdim // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top 911261991Sdim // count bits from RxSBG.Input are ignored. 912261991Sdim if (maskMatters(RxSBG, allOnes(Count) << (BitSize - Count))) 913261991Sdim return false; 914261991Sdim } else { 915261991Sdim // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count), 916261991Sdim // which is similar to SLL above. 917261991Sdim if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count))) 918261991Sdim return false; 919261991Sdim } 920261991Sdim 921261991Sdim RxSBG.Rotate = (RxSBG.Rotate - Count) & 63; 922261991Sdim RxSBG.Input = N.getOperand(0); 923261991Sdim return true; 924261991Sdim } 925261991Sdim default: 926261991Sdim return false; 927261991Sdim } 928261991Sdim} 929261991Sdim 930309124SdimSDValue SystemZDAGToDAGISel::getUNDEF(const SDLoc &DL, EVT VT) const { 931261991Sdim SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT); 932261991Sdim return SDValue(N, 0); 933261991Sdim} 934261991Sdim 935309124SdimSDValue SystemZDAGToDAGISel::convertTo(const SDLoc &DL, EVT VT, 936309124Sdim SDValue N) const { 937261991Sdim if (N.getValueType() == MVT::i32 && VT == MVT::i64) 938261991Sdim return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32, 939261991Sdim DL, VT, getUNDEF(DL, MVT::i64), N); 940261991Sdim if (N.getValueType() == MVT::i64 && VT == MVT::i32) 941261991Sdim return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); 942261991Sdim assert(N.getValueType() == VT && "Unexpected value types"); 943261991Sdim return N; 944261991Sdim} 945261991Sdim 946309124Sdimbool SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) { 947288943Sdim SDLoc DL(N); 948261991Sdim EVT VT = N->getValueType(0); 949288943Sdim if (!VT.isInteger() || VT.getSizeInBits() > 64) 950309124Sdim return false; 951261991Sdim RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0)); 952261991Sdim unsigned Count = 0; 953261991Sdim while (expandRxSBG(RISBG)) 954309124Sdim // The widening or narrowing is expected to be free. 955309124Sdim // Counting widening or narrowing as a saved operation will result in 956309124Sdim // preferring an R*SBG over a simple shift/logical instruction. 957309124Sdim if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND && 958309124Sdim RISBG.Input.getOpcode() != ISD::TRUNCATE) 959261991Sdim Count += 1; 960261991Sdim if (Count == 0) 961309124Sdim return false; 962261991Sdim 963314564Sdim // Prefer to use normal shift instructions over RISBG, since they can handle 964314564Sdim // all cases and are sometimes shorter. 965314564Sdim if (Count == 1 && N->getOpcode() != ISD::AND) 966314564Sdim return false; 967314564Sdim 968314564Sdim // Prefer register extensions like LLC over RISBG. Also prefer to start 969314564Sdim // out with normal ANDs if one instruction would be enough. We can convert 970314564Sdim // these ANDs into an RISBG later if a three-address instruction is useful. 971314564Sdim if (RISBG.Rotate == 0) { 972314564Sdim bool PreferAnd = false; 973314564Sdim // Prefer AND for any 32-bit and-immediate operation. 974314564Sdim if (VT == MVT::i32) 975314564Sdim PreferAnd = true; 976314564Sdim // As well as for any 64-bit operation that can be implemented via LLC(R), 977314564Sdim // LLH(R), LLGT(R), or one of the and-immediate instructions. 978314564Sdim else if (RISBG.Mask == 0xff || 979314564Sdim RISBG.Mask == 0xffff || 980314564Sdim RISBG.Mask == 0x7fffffff || 981314564Sdim SystemZ::isImmLF(~RISBG.Mask) || 982314564Sdim SystemZ::isImmHF(~RISBG.Mask)) 983314564Sdim PreferAnd = true; 984314564Sdim // And likewise for the LLZRGF instruction, which doesn't have a register 985314564Sdim // to register version. 986314564Sdim else if (auto *Load = dyn_cast<LoadSDNode>(RISBG.Input)) { 987314564Sdim if (Load->getMemoryVT() == MVT::i32 && 988314564Sdim (Load->getExtensionType() == ISD::EXTLOAD || 989314564Sdim Load->getExtensionType() == ISD::ZEXTLOAD) && 990314564Sdim RISBG.Mask == 0xffffff00 && 991314564Sdim Subtarget->hasLoadAndZeroRightmostByte()) 992314564Sdim PreferAnd = true; 993314564Sdim } 994314564Sdim if (PreferAnd) { 995314564Sdim // Replace the current node with an AND. Note that the current node 996314564Sdim // might already be that same AND, in which case it is already CSE'd 997314564Sdim // with it, and we must not call ReplaceNode. 998314564Sdim SDValue In = convertTo(DL, VT, RISBG.Input); 999314564Sdim SDValue Mask = CurDAG->getConstant(RISBG.Mask, DL, VT); 1000314564Sdim SDValue New = CurDAG->getNode(ISD::AND, DL, VT, In, Mask); 1001314564Sdim if (N != New.getNode()) { 1002314564Sdim insertDAGNode(CurDAG, N, Mask); 1003314564Sdim insertDAGNode(CurDAG, N, New); 1004314564Sdim ReplaceNode(N, New.getNode()); 1005314564Sdim N = New.getNode(); 1006261991Sdim } 1007314564Sdim // Now, select the machine opcode to implement this operation. 1008341825Sdim if (!N->isMachineOpcode()) 1009341825Sdim SelectCode(N); 1010314564Sdim return true; 1011261991Sdim } 1012296417Sdim } 1013261991Sdim 1014261991Sdim unsigned Opcode = SystemZ::RISBG; 1015288943Sdim // Prefer RISBGN if available, since it does not clobber CC. 1016288943Sdim if (Subtarget->hasMiscellaneousExtensions()) 1017288943Sdim Opcode = SystemZ::RISBGN; 1018261991Sdim EVT OpcodeVT = MVT::i64; 1019327952Sdim if (VT == MVT::i32 && Subtarget->hasHighWord() && 1020327952Sdim // We can only use the 32-bit instructions if all source bits are 1021327952Sdim // in the low 32 bits without wrapping, both after rotation (because 1022327952Sdim // of the smaller range for Start and End) and before rotation 1023327952Sdim // (because the input value is truncated). 1024327952Sdim RISBG.Start >= 32 && RISBG.End >= RISBG.Start && 1025327952Sdim ((RISBG.Start + RISBG.Rotate) & 63) >= 32 && 1026327952Sdim ((RISBG.End + RISBG.Rotate) & 63) >= 1027327952Sdim ((RISBG.Start + RISBG.Rotate) & 63)) { 1028261991Sdim Opcode = SystemZ::RISBMux; 1029261991Sdim OpcodeVT = MVT::i32; 1030261991Sdim RISBG.Start &= 31; 1031261991Sdim RISBG.End &= 31; 1032261991Sdim } 1033261991Sdim SDValue Ops[5] = { 1034288943Sdim getUNDEF(DL, OpcodeVT), 1035288943Sdim convertTo(DL, OpcodeVT, RISBG.Input), 1036288943Sdim CurDAG->getTargetConstant(RISBG.Start, DL, MVT::i32), 1037288943Sdim CurDAG->getTargetConstant(RISBG.End | 128, DL, MVT::i32), 1038288943Sdim CurDAG->getTargetConstant(RISBG.Rotate, DL, MVT::i32) 1039261991Sdim }; 1040309124Sdim SDValue New = convertTo( 1041309124Sdim DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops), 0)); 1042341825Sdim ReplaceNode(N, New.getNode()); 1043309124Sdim return true; 1044261991Sdim} 1045261991Sdim 1046309124Sdimbool SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) { 1047288943Sdim SDLoc DL(N); 1048288943Sdim EVT VT = N->getValueType(0); 1049288943Sdim if (!VT.isInteger() || VT.getSizeInBits() > 64) 1050309124Sdim return false; 1051261991Sdim // Try treating each operand of N as the second operand of the RxSBG 1052261991Sdim // and see which goes deepest. 1053261991Sdim RxSBGOperands RxSBG[] = { 1054261991Sdim RxSBGOperands(Opcode, N->getOperand(0)), 1055261991Sdim RxSBGOperands(Opcode, N->getOperand(1)) 1056261991Sdim }; 1057261991Sdim unsigned Count[] = { 0, 0 }; 1058261991Sdim for (unsigned I = 0; I < 2; ++I) 1059261991Sdim while (expandRxSBG(RxSBG[I])) 1060309124Sdim // The widening or narrowing is expected to be free. 1061309124Sdim // Counting widening or narrowing as a saved operation will result in 1062309124Sdim // preferring an R*SBG over a simple shift/logical instruction. 1063309124Sdim if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND && 1064309124Sdim RxSBG[I].Input.getOpcode() != ISD::TRUNCATE) 1065261991Sdim Count[I] += 1; 1066261991Sdim 1067261991Sdim // Do nothing if neither operand is suitable. 1068261991Sdim if (Count[0] == 0 && Count[1] == 0) 1069309124Sdim return false; 1070261991Sdim 1071261991Sdim // Pick the deepest second operand. 1072261991Sdim unsigned I = Count[0] > Count[1] ? 0 : 1; 1073261991Sdim SDValue Op0 = N->getOperand(I ^ 1); 1074261991Sdim 1075261991Sdim // Prefer IC for character insertions from memory. 1076261991Sdim if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0) 1077276479Sdim if (auto *Load = dyn_cast<LoadSDNode>(Op0.getNode())) 1078261991Sdim if (Load->getMemoryVT() == MVT::i8) 1079309124Sdim return false; 1080261991Sdim 1081261991Sdim // See whether we can avoid an AND in the first operand by converting 1082261991Sdim // ROSBG to RISBG. 1083288943Sdim if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) { 1084261991Sdim Opcode = SystemZ::RISBG; 1085288943Sdim // Prefer RISBGN if available, since it does not clobber CC. 1086288943Sdim if (Subtarget->hasMiscellaneousExtensions()) 1087288943Sdim Opcode = SystemZ::RISBGN; 1088288943Sdim } 1089288943Sdim 1090261991Sdim SDValue Ops[5] = { 1091288943Sdim convertTo(DL, MVT::i64, Op0), 1092288943Sdim convertTo(DL, MVT::i64, RxSBG[I].Input), 1093288943Sdim CurDAG->getTargetConstant(RxSBG[I].Start, DL, MVT::i32), 1094288943Sdim CurDAG->getTargetConstant(RxSBG[I].End, DL, MVT::i32), 1095288943Sdim CurDAG->getTargetConstant(RxSBG[I].Rotate, DL, MVT::i32) 1096261991Sdim }; 1097309124Sdim SDValue New = convertTo( 1098309124Sdim DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, MVT::i64, Ops), 0)); 1099309124Sdim ReplaceNode(N, New.getNode()); 1100309124Sdim return true; 1101261991Sdim} 1102261991Sdim 1103309124Sdimvoid SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node, 1104309124Sdim SDValue Op0, uint64_t UpperVal, 1105309124Sdim uint64_t LowerVal) { 1106251607Sdim EVT VT = Node->getValueType(0); 1107261991Sdim SDLoc DL(Node); 1108288943Sdim SDValue Upper = CurDAG->getConstant(UpperVal, DL, VT); 1109251607Sdim if (Op0.getNode()) 1110251607Sdim Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper); 1111251607Sdim 1112309124Sdim { 1113309124Sdim // When we haven't passed in Op0, Upper will be a constant. In order to 1114309124Sdim // prevent folding back to the large immediate in `Or = getNode(...)` we run 1115309124Sdim // SelectCode first and end up with an opaque machine node. This means that 1116309124Sdim // we need to use a handle to keep track of Upper in case it gets CSE'd by 1117309124Sdim // SelectCode. 1118309124Sdim // 1119309124Sdim // Note that in the case where Op0 is passed in we could just call 1120309124Sdim // SelectCode(Upper) later, along with the SelectCode(Or), and avoid needing 1121309124Sdim // the handle at all, but it's fine to do it here. 1122309124Sdim // 1123309124Sdim // TODO: This is a pretty hacky way to do this. Can we do something that 1124309124Sdim // doesn't require a two paragraph explanation? 1125309124Sdim HandleSDNode Handle(Upper); 1126309124Sdim SelectCode(Upper.getNode()); 1127309124Sdim Upper = Handle.getValue(); 1128309124Sdim } 1129309124Sdim 1130288943Sdim SDValue Lower = CurDAG->getConstant(LowerVal, DL, VT); 1131251607Sdim SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower); 1132309124Sdim 1133341825Sdim ReplaceNode(Node, Or.getNode()); 1134309124Sdim 1135309124Sdim SelectCode(Or.getNode()); 1136251607Sdim} 1137251607Sdim 1138309124Sdimbool SystemZDAGToDAGISel::tryGather(SDNode *N, unsigned Opcode) { 1139288943Sdim SDValue ElemV = N->getOperand(2); 1140288943Sdim auto *ElemN = dyn_cast<ConstantSDNode>(ElemV); 1141288943Sdim if (!ElemN) 1142309124Sdim return false; 1143288943Sdim 1144288943Sdim unsigned Elem = ElemN->getZExtValue(); 1145288943Sdim EVT VT = N->getValueType(0); 1146288943Sdim if (Elem >= VT.getVectorNumElements()) 1147309124Sdim return false; 1148288943Sdim 1149288943Sdim auto *Load = dyn_cast<LoadSDNode>(N->getOperand(1)); 1150288943Sdim if (!Load || !Load->hasOneUse()) 1151309124Sdim return false; 1152288943Sdim if (Load->getMemoryVT().getSizeInBits() != 1153288943Sdim Load->getValueType(0).getSizeInBits()) 1154309124Sdim return false; 1155288943Sdim 1156288943Sdim SDValue Base, Disp, Index; 1157288943Sdim if (!selectBDVAddr12Only(Load->getBasePtr(), ElemV, Base, Disp, Index) || 1158288943Sdim Index.getValueType() != VT.changeVectorElementTypeToInteger()) 1159309124Sdim return false; 1160288943Sdim 1161288943Sdim SDLoc DL(Load); 1162288943Sdim SDValue Ops[] = { 1163288943Sdim N->getOperand(0), Base, Disp, Index, 1164288943Sdim CurDAG->getTargetConstant(Elem, DL, MVT::i32), Load->getChain() 1165288943Sdim }; 1166288943Sdim SDNode *Res = CurDAG->getMachineNode(Opcode, DL, VT, MVT::Other, Ops); 1167288943Sdim ReplaceUses(SDValue(Load, 1), SDValue(Res, 1)); 1168309124Sdim ReplaceNode(N, Res); 1169309124Sdim return true; 1170288943Sdim} 1171288943Sdim 1172309124Sdimbool SystemZDAGToDAGISel::tryScatter(StoreSDNode *Store, unsigned Opcode) { 1173288943Sdim SDValue Value = Store->getValue(); 1174288943Sdim if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT) 1175309124Sdim return false; 1176314564Sdim if (Store->getMemoryVT().getSizeInBits() != Value.getValueSizeInBits()) 1177309124Sdim return false; 1178288943Sdim 1179288943Sdim SDValue ElemV = Value.getOperand(1); 1180288943Sdim auto *ElemN = dyn_cast<ConstantSDNode>(ElemV); 1181288943Sdim if (!ElemN) 1182309124Sdim return false; 1183288943Sdim 1184288943Sdim SDValue Vec = Value.getOperand(0); 1185288943Sdim EVT VT = Vec.getValueType(); 1186288943Sdim unsigned Elem = ElemN->getZExtValue(); 1187288943Sdim if (Elem >= VT.getVectorNumElements()) 1188309124Sdim return false; 1189288943Sdim 1190288943Sdim SDValue Base, Disp, Index; 1191288943Sdim if (!selectBDVAddr12Only(Store->getBasePtr(), ElemV, Base, Disp, Index) || 1192288943Sdim Index.getValueType() != VT.changeVectorElementTypeToInteger()) 1193309124Sdim return false; 1194288943Sdim 1195288943Sdim SDLoc DL(Store); 1196288943Sdim SDValue Ops[] = { 1197288943Sdim Vec, Base, Disp, Index, CurDAG->getTargetConstant(Elem, DL, MVT::i32), 1198288943Sdim Store->getChain() 1199288943Sdim }; 1200309124Sdim ReplaceNode(Store, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops)); 1201309124Sdim return true; 1202288943Sdim} 1203288943Sdim 1204341825Sdim// Check whether or not the chain ending in StoreNode is suitable for doing 1205341825Sdim// the {load; op; store} to modify transformation. 1206341825Sdimstatic bool isFusableLoadOpStorePattern(StoreSDNode *StoreNode, 1207341825Sdim SDValue StoredVal, SelectionDAG *CurDAG, 1208341825Sdim LoadSDNode *&LoadNode, 1209341825Sdim SDValue &InputChain) { 1210341825Sdim // Is the stored value result 0 of the operation? 1211341825Sdim if (StoredVal.getResNo() != 0) 1212341825Sdim return false; 1213341825Sdim 1214341825Sdim // Are there other uses of the loaded value than the operation? 1215341825Sdim if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) 1216341825Sdim return false; 1217341825Sdim 1218341825Sdim // Is the store non-extending and non-indexed? 1219341825Sdim if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal()) 1220341825Sdim return false; 1221341825Sdim 1222341825Sdim SDValue Load = StoredVal->getOperand(0); 1223341825Sdim // Is the stored value a non-extending and non-indexed load? 1224341825Sdim if (!ISD::isNormalLoad(Load.getNode())) 1225341825Sdim return false; 1226341825Sdim 1227341825Sdim // Return LoadNode by reference. 1228341825Sdim LoadNode = cast<LoadSDNode>(Load); 1229341825Sdim 1230341825Sdim // Is store the only read of the loaded value? 1231341825Sdim if (!Load.hasOneUse()) 1232341825Sdim return false; 1233341825Sdim 1234341825Sdim // Is the address of the store the same as the load? 1235341825Sdim if (LoadNode->getBasePtr() != StoreNode->getBasePtr() || 1236341825Sdim LoadNode->getOffset() != StoreNode->getOffset()) 1237341825Sdim return false; 1238341825Sdim 1239341825Sdim // Check if the chain is produced by the load or is a TokenFactor with 1240341825Sdim // the load output chain as an operand. Return InputChain by reference. 1241341825Sdim SDValue Chain = StoreNode->getChain(); 1242341825Sdim 1243341825Sdim bool ChainCheck = false; 1244341825Sdim if (Chain == Load.getValue(1)) { 1245341825Sdim ChainCheck = true; 1246341825Sdim InputChain = LoadNode->getChain(); 1247341825Sdim } else if (Chain.getOpcode() == ISD::TokenFactor) { 1248341825Sdim SmallVector<SDValue, 4> ChainOps; 1249341825Sdim for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) { 1250341825Sdim SDValue Op = Chain.getOperand(i); 1251341825Sdim if (Op == Load.getValue(1)) { 1252341825Sdim ChainCheck = true; 1253341825Sdim // Drop Load, but keep its chain. No cycle check necessary. 1254341825Sdim ChainOps.push_back(Load.getOperand(0)); 1255341825Sdim continue; 1256341825Sdim } 1257341825Sdim 1258341825Sdim // Make sure using Op as part of the chain would not cause a cycle here. 1259341825Sdim // In theory, we could check whether the chain node is a predecessor of 1260341825Sdim // the load. But that can be very expensive. Instead visit the uses and 1261341825Sdim // make sure they all have smaller node id than the load. 1262341825Sdim int LoadId = LoadNode->getNodeId(); 1263341825Sdim for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 1264341825Sdim UE = UI->use_end(); UI != UE; ++UI) { 1265341825Sdim if (UI.getUse().getResNo() != 0) 1266341825Sdim continue; 1267341825Sdim if (UI->getNodeId() > LoadId) 1268341825Sdim return false; 1269341825Sdim } 1270341825Sdim 1271341825Sdim ChainOps.push_back(Op); 1272341825Sdim } 1273341825Sdim 1274341825Sdim if (ChainCheck) 1275341825Sdim // Make a new TokenFactor with all the other input chains except 1276341825Sdim // for the load. 1277341825Sdim InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), 1278341825Sdim MVT::Other, ChainOps); 1279341825Sdim } 1280341825Sdim if (!ChainCheck) 1281341825Sdim return false; 1282341825Sdim 1283341825Sdim return true; 1284341825Sdim} 1285341825Sdim 1286341825Sdim// Change a chain of {load; op; store} of the same value into a simple op 1287341825Sdim// through memory of that value, if the uses of the modified value and its 1288341825Sdim// address are suitable. 1289341825Sdim// 1290341825Sdim// The tablegen pattern memory operand pattern is currently not able to match 1291341825Sdim// the case where the CC on the original operation are used. 1292341825Sdim// 1293341825Sdim// See the equivalent routine in X86ISelDAGToDAG for further comments. 1294341825Sdimbool SystemZDAGToDAGISel::tryFoldLoadStoreIntoMemOperand(SDNode *Node) { 1295341825Sdim StoreSDNode *StoreNode = cast<StoreSDNode>(Node); 1296341825Sdim SDValue StoredVal = StoreNode->getOperand(1); 1297341825Sdim unsigned Opc = StoredVal->getOpcode(); 1298341825Sdim SDLoc DL(StoreNode); 1299341825Sdim 1300341825Sdim // Before we try to select anything, make sure this is memory operand size 1301341825Sdim // and opcode we can handle. Note that this must match the code below that 1302341825Sdim // actually lowers the opcodes. 1303341825Sdim EVT MemVT = StoreNode->getMemoryVT(); 1304341825Sdim unsigned NewOpc = 0; 1305341825Sdim bool NegateOperand = false; 1306341825Sdim switch (Opc) { 1307341825Sdim default: 1308341825Sdim return false; 1309341825Sdim case SystemZISD::SSUBO: 1310341825Sdim NegateOperand = true; 1311341825Sdim /* fall through */ 1312341825Sdim case SystemZISD::SADDO: 1313341825Sdim if (MemVT == MVT::i32) 1314341825Sdim NewOpc = SystemZ::ASI; 1315341825Sdim else if (MemVT == MVT::i64) 1316341825Sdim NewOpc = SystemZ::AGSI; 1317341825Sdim else 1318341825Sdim return false; 1319341825Sdim break; 1320341825Sdim case SystemZISD::USUBO: 1321341825Sdim NegateOperand = true; 1322341825Sdim /* fall through */ 1323341825Sdim case SystemZISD::UADDO: 1324341825Sdim if (MemVT == MVT::i32) 1325341825Sdim NewOpc = SystemZ::ALSI; 1326341825Sdim else if (MemVT == MVT::i64) 1327341825Sdim NewOpc = SystemZ::ALGSI; 1328341825Sdim else 1329341825Sdim return false; 1330341825Sdim break; 1331341825Sdim } 1332341825Sdim 1333341825Sdim LoadSDNode *LoadNode = nullptr; 1334341825Sdim SDValue InputChain; 1335341825Sdim if (!isFusableLoadOpStorePattern(StoreNode, StoredVal, CurDAG, LoadNode, 1336341825Sdim InputChain)) 1337341825Sdim return false; 1338341825Sdim 1339341825Sdim SDValue Operand = StoredVal.getOperand(1); 1340341825Sdim auto *OperandC = dyn_cast<ConstantSDNode>(Operand); 1341341825Sdim if (!OperandC) 1342341825Sdim return false; 1343341825Sdim auto OperandV = OperandC->getAPIntValue(); 1344341825Sdim if (NegateOperand) 1345341825Sdim OperandV = -OperandV; 1346341825Sdim if (OperandV.getMinSignedBits() > 8) 1347341825Sdim return false; 1348341825Sdim Operand = CurDAG->getTargetConstant(OperandV, DL, MemVT); 1349341825Sdim 1350341825Sdim SDValue Base, Disp; 1351341825Sdim if (!selectBDAddr20Only(StoreNode->getBasePtr(), Base, Disp)) 1352341825Sdim return false; 1353341825Sdim 1354341825Sdim SDValue Ops[] = { Base, Disp, Operand, InputChain }; 1355341825Sdim MachineSDNode *Result = 1356341825Sdim CurDAG->getMachineNode(NewOpc, DL, MVT::i32, MVT::Other, Ops); 1357341825Sdim 1358341825Sdim MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2); 1359341825Sdim MemOp[0] = StoreNode->getMemOperand(); 1360341825Sdim MemOp[1] = LoadNode->getMemOperand(); 1361341825Sdim Result->setMemRefs(MemOp, MemOp + 2); 1362341825Sdim 1363341825Sdim ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1)); 1364341825Sdim ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0)); 1365341825Sdim CurDAG->RemoveDeadNode(Node); 1366341825Sdim return true; 1367341825Sdim} 1368341825Sdim 1369261991Sdimbool SystemZDAGToDAGISel::canUseBlockOperation(StoreSDNode *Store, 1370261991Sdim LoadSDNode *Load) const { 1371261991Sdim // Check that the two memory operands have the same size. 1372261991Sdim if (Load->getMemoryVT() != Store->getMemoryVT()) 1373261991Sdim return false; 1374261991Sdim 1375261991Sdim // Volatility stops an access from being decomposed. 1376261991Sdim if (Load->isVolatile() || Store->isVolatile()) 1377261991Sdim return false; 1378261991Sdim 1379261991Sdim // There's no chance of overlap if the load is invariant. 1380314564Sdim if (Load->isInvariant() && Load->isDereferenceable()) 1381261991Sdim return true; 1382261991Sdim 1383261991Sdim // Otherwise we need to check whether there's an alias. 1384276479Sdim const Value *V1 = Load->getMemOperand()->getValue(); 1385276479Sdim const Value *V2 = Store->getMemOperand()->getValue(); 1386261991Sdim if (!V1 || !V2) 1387261991Sdim return false; 1388261991Sdim 1389261991Sdim // Reject equality. 1390261991Sdim uint64_t Size = Load->getMemoryVT().getStoreSize(); 1391261991Sdim int64_t End1 = Load->getSrcValueOffset() + Size; 1392261991Sdim int64_t End2 = Store->getSrcValueOffset() + Size; 1393261991Sdim if (V1 == V2 && End1 == End2) 1394261991Sdim return false; 1395261991Sdim 1396288943Sdim return !AA->alias(MemoryLocation(V1, End1, Load->getAAInfo()), 1397288943Sdim MemoryLocation(V2, End2, Store->getAAInfo())); 1398261991Sdim} 1399261991Sdim 1400261991Sdimbool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const { 1401276479Sdim auto *Store = cast<StoreSDNode>(N); 1402276479Sdim auto *Load = cast<LoadSDNode>(Store->getValue()); 1403261991Sdim 1404261991Sdim // Prefer not to use MVC if either address can use ... RELATIVE LONG 1405261991Sdim // instructions. 1406261991Sdim uint64_t Size = Load->getMemoryVT().getStoreSize(); 1407261991Sdim if (Size > 1 && Size <= 8) { 1408261991Sdim // Prefer LHRL, LRL and LGRL. 1409261991Sdim if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode())) 1410261991Sdim return false; 1411261991Sdim // Prefer STHRL, STRL and STGRL. 1412261991Sdim if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode())) 1413261991Sdim return false; 1414261991Sdim } 1415261991Sdim 1416261991Sdim return canUseBlockOperation(Store, Load); 1417261991Sdim} 1418261991Sdim 1419261991Sdimbool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N, 1420261991Sdim unsigned I) const { 1421276479Sdim auto *StoreA = cast<StoreSDNode>(N); 1422276479Sdim auto *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I)); 1423276479Sdim auto *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I)); 1424261991Sdim return !LoadA->isVolatile() && canUseBlockOperation(StoreA, LoadB); 1425261991Sdim} 1426261991Sdim 1427309124Sdimvoid SystemZDAGToDAGISel::Select(SDNode *Node) { 1428251607Sdim // If we have a custom node, we already have selected! 1429251607Sdim if (Node->isMachineOpcode()) { 1430341825Sdim LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 1431255804Sdim Node->setNodeId(-1); 1432309124Sdim return; 1433251607Sdim } 1434251607Sdim 1435251607Sdim unsigned Opcode = Node->getOpcode(); 1436251607Sdim switch (Opcode) { 1437251607Sdim case ISD::OR: 1438261991Sdim if (Node->getOperand(1).getOpcode() != ISD::Constant) 1439309124Sdim if (tryRxSBG(Node, SystemZ::ROSBG)) 1440309124Sdim return; 1441261991Sdim goto or_xor; 1442261991Sdim 1443251607Sdim case ISD::XOR: 1444261991Sdim if (Node->getOperand(1).getOpcode() != ISD::Constant) 1445309124Sdim if (tryRxSBG(Node, SystemZ::RXSBG)) 1446309124Sdim return; 1447261991Sdim // Fall through. 1448261991Sdim or_xor: 1449251607Sdim // If this is a 64-bit operation in which both 32-bit halves are nonzero, 1450327952Sdim // split the operation into two. If both operands here happen to be 1451327952Sdim // constant, leave this to common code to optimize. 1452327952Sdim if (Node->getValueType(0) == MVT::i64 && 1453327952Sdim Node->getOperand(0).getOpcode() != ISD::Constant) 1454276479Sdim if (auto *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) { 1455251607Sdim uint64_t Val = Op1->getZExtValue(); 1456309124Sdim if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val)) { 1457309124Sdim splitLargeImmediate(Opcode, Node, Node->getOperand(0), 1458309124Sdim Val - uint32_t(Val), uint32_t(Val)); 1459309124Sdim return; 1460309124Sdim } 1461251607Sdim } 1462251607Sdim break; 1463251607Sdim 1464261991Sdim case ISD::AND: 1465261991Sdim if (Node->getOperand(1).getOpcode() != ISD::Constant) 1466309124Sdim if (tryRxSBG(Node, SystemZ::RNSBG)) 1467309124Sdim return; 1468314564Sdim LLVM_FALLTHROUGH; 1469261991Sdim case ISD::ROTL: 1470261991Sdim case ISD::SHL: 1471261991Sdim case ISD::SRL: 1472276479Sdim case ISD::ZERO_EXTEND: 1473309124Sdim if (tryRISBGZero(Node)) 1474309124Sdim return; 1475261991Sdim break; 1476261991Sdim 1477251607Sdim case ISD::Constant: 1478251607Sdim // If this is a 64-bit constant that is out of the range of LLILF, 1479251607Sdim // LLIHF and LGFI, split it into two 32-bit pieces. 1480251607Sdim if (Node->getValueType(0) == MVT::i64) { 1481251607Sdim uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue(); 1482309124Sdim if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val)) { 1483309124Sdim splitLargeImmediate(ISD::OR, Node, SDValue(), Val - uint32_t(Val), 1484309124Sdim uint32_t(Val)); 1485309124Sdim return; 1486309124Sdim } 1487251607Sdim } 1488251607Sdim break; 1489251607Sdim 1490261991Sdim case SystemZISD::SELECT_CCMASK: { 1491261991Sdim SDValue Op0 = Node->getOperand(0); 1492261991Sdim SDValue Op1 = Node->getOperand(1); 1493261991Sdim // Prefer to put any load first, so that it can be matched as a 1494314564Sdim // conditional load. Likewise for constants in range for LOCHI. 1495314564Sdim if ((Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) || 1496314564Sdim (Subtarget->hasLoadStoreOnCond2() && 1497314564Sdim Node->getValueType(0).isInteger() && 1498314564Sdim Op1.getOpcode() == ISD::Constant && 1499314564Sdim isInt<16>(cast<ConstantSDNode>(Op1)->getSExtValue()) && 1500314564Sdim !(Op0.getOpcode() == ISD::Constant && 1501314564Sdim isInt<16>(cast<ConstantSDNode>(Op0)->getSExtValue())))) { 1502261991Sdim SDValue CCValid = Node->getOperand(2); 1503261991Sdim SDValue CCMask = Node->getOperand(3); 1504261991Sdim uint64_t ConstCCValid = 1505261991Sdim cast<ConstantSDNode>(CCValid.getNode())->getZExtValue(); 1506261991Sdim uint64_t ConstCCMask = 1507261991Sdim cast<ConstantSDNode>(CCMask.getNode())->getZExtValue(); 1508261991Sdim // Invert the condition. 1509288943Sdim CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask, SDLoc(Node), 1510261991Sdim CCMask.getValueType()); 1511261991Sdim SDValue Op4 = Node->getOperand(4); 1512341825Sdim SDNode *UpdatedNode = 1513341825Sdim CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); 1514341825Sdim if (UpdatedNode != Node) { 1515341825Sdim // In case this node already exists then replace Node with it. 1516341825Sdim ReplaceNode(Node, UpdatedNode); 1517341825Sdim Node = UpdatedNode; 1518341825Sdim } 1519261991Sdim } 1520261991Sdim break; 1521251607Sdim } 1522288943Sdim 1523288943Sdim case ISD::INSERT_VECTOR_ELT: { 1524288943Sdim EVT VT = Node->getValueType(0); 1525314564Sdim unsigned ElemBitSize = VT.getScalarSizeInBits(); 1526309124Sdim if (ElemBitSize == 32) { 1527309124Sdim if (tryGather(Node, SystemZ::VGEF)) 1528309124Sdim return; 1529309124Sdim } else if (ElemBitSize == 64) { 1530309124Sdim if (tryGather(Node, SystemZ::VGEG)) 1531309124Sdim return; 1532309124Sdim } 1533288943Sdim break; 1534261991Sdim } 1535251607Sdim 1536288943Sdim case ISD::STORE: { 1537341825Sdim if (tryFoldLoadStoreIntoMemOperand(Node)) 1538341825Sdim return; 1539288943Sdim auto *Store = cast<StoreSDNode>(Node); 1540314564Sdim unsigned ElemBitSize = Store->getValue().getValueSizeInBits(); 1541309124Sdim if (ElemBitSize == 32) { 1542309124Sdim if (tryScatter(Store, SystemZ::VSCEF)) 1543309124Sdim return; 1544309124Sdim } else if (ElemBitSize == 64) { 1545309124Sdim if (tryScatter(Store, SystemZ::VSCEG)) 1546309124Sdim return; 1547309124Sdim } 1548288943Sdim break; 1549288943Sdim } 1550288943Sdim } 1551288943Sdim 1552309124Sdim SelectCode(Node); 1553251607Sdim} 1554251607Sdim 1555251607Sdimbool SystemZDAGToDAGISel:: 1556251607SdimSelectInlineAsmMemoryOperand(const SDValue &Op, 1557288943Sdim unsigned ConstraintID, 1558251607Sdim std::vector<SDValue> &OutOps) { 1559309124Sdim SystemZAddressingMode::AddrForm Form; 1560309124Sdim SystemZAddressingMode::DispRange DispRange; 1561309124Sdim SDValue Base, Disp, Index; 1562309124Sdim 1563288943Sdim switch(ConstraintID) { 1564288943Sdim default: 1565288943Sdim llvm_unreachable("Unexpected asm memory constraint"); 1566288943Sdim case InlineAsm::Constraint_i: 1567288943Sdim case InlineAsm::Constraint_Q: 1568309124Sdim // Accept an address with a short displacement, but no index. 1569309124Sdim Form = SystemZAddressingMode::FormBD; 1570309124Sdim DispRange = SystemZAddressingMode::Disp12Only; 1571309124Sdim break; 1572288943Sdim case InlineAsm::Constraint_R: 1573309124Sdim // Accept an address with a short displacement and an index. 1574309124Sdim Form = SystemZAddressingMode::FormBDXNormal; 1575309124Sdim DispRange = SystemZAddressingMode::Disp12Only; 1576309124Sdim break; 1577288943Sdim case InlineAsm::Constraint_S: 1578309124Sdim // Accept an address with a long displacement, but no index. 1579309124Sdim Form = SystemZAddressingMode::FormBD; 1580309124Sdim DispRange = SystemZAddressingMode::Disp20Only; 1581309124Sdim break; 1582288943Sdim case InlineAsm::Constraint_T: 1583309124Sdim case InlineAsm::Constraint_m: 1584327952Sdim case InlineAsm::Constraint_o: 1585309124Sdim // Accept an address with a long displacement and an index. 1586309124Sdim // m works the same as T, as this is the most general case. 1587327952Sdim // We don't really have any special handling of "offsettable" 1588327952Sdim // memory addresses, so just treat o the same as m. 1589309124Sdim Form = SystemZAddressingMode::FormBDXNormal; 1590309124Sdim DispRange = SystemZAddressingMode::Disp20Only; 1591288943Sdim break; 1592288943Sdim } 1593309124Sdim 1594309124Sdim if (selectBDXAddr(Form, DispRange, Op, Base, Disp, Index)) { 1595314564Sdim const TargetRegisterClass *TRC = 1596314564Sdim Subtarget->getRegisterInfo()->getPointerRegClass(*MF); 1597314564Sdim SDLoc DL(Base); 1598314564Sdim SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); 1599314564Sdim 1600314564Sdim // Make sure that the base address doesn't go into %r0. 1601314564Sdim // If it's a TargetFrameIndex or a fixed register, we shouldn't do anything. 1602314564Sdim if (Base.getOpcode() != ISD::TargetFrameIndex && 1603314564Sdim Base.getOpcode() != ISD::Register) { 1604314564Sdim Base = 1605314564Sdim SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, 1606314564Sdim DL, Base.getValueType(), 1607314564Sdim Base, RC), 0); 1608314564Sdim } 1609314564Sdim 1610314564Sdim // Make sure that the index register isn't assigned to %r0 either. 1611314564Sdim if (Index.getOpcode() != ISD::Register) { 1612314564Sdim Index = 1613314564Sdim SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, 1614314564Sdim DL, Index.getValueType(), 1615314564Sdim Index, RC), 0); 1616314564Sdim } 1617314564Sdim 1618309124Sdim OutOps.push_back(Base); 1619309124Sdim OutOps.push_back(Disp); 1620309124Sdim OutOps.push_back(Index); 1621309124Sdim return false; 1622309124Sdim } 1623309124Sdim 1624288943Sdim return true; 1625251607Sdim} 1626341825Sdim 1627341825Sdim// IsProfitableToFold - Returns true if is profitable to fold the specific 1628341825Sdim// operand node N of U during instruction selection that starts at Root. 1629341825Sdimbool 1630341825SdimSystemZDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1631341825Sdim SDNode *Root) const { 1632341825Sdim // We want to avoid folding a LOAD into an ICMP node if as a result 1633341825Sdim // we would be forced to spill the condition code into a GPR. 1634341825Sdim if (N.getOpcode() == ISD::LOAD && U->getOpcode() == SystemZISD::ICMP) { 1635341825Sdim if (!N.hasOneUse() || !U->hasOneUse()) 1636341825Sdim return false; 1637341825Sdim 1638341825Sdim // The user of the CC value will usually be a CopyToReg into the 1639341825Sdim // physical CC register, which in turn is glued and chained to the 1640341825Sdim // actual instruction that uses the CC value. Bail out if we have 1641341825Sdim // anything else than that. 1642341825Sdim SDNode *CCUser = *U->use_begin(); 1643341825Sdim SDNode *CCRegUser = nullptr; 1644341825Sdim if (CCUser->getOpcode() == ISD::CopyToReg || 1645341825Sdim cast<RegisterSDNode>(CCUser->getOperand(1))->getReg() == SystemZ::CC) { 1646341825Sdim for (auto *U : CCUser->uses()) { 1647341825Sdim if (CCRegUser == nullptr) 1648341825Sdim CCRegUser = U; 1649341825Sdim else if (CCRegUser != U) 1650341825Sdim return false; 1651341825Sdim } 1652341825Sdim } 1653341825Sdim if (CCRegUser == nullptr) 1654341825Sdim return false; 1655341825Sdim 1656341825Sdim // If the actual instruction is a branch, the only thing that remains to be 1657341825Sdim // checked is whether the CCUser chain is a predecessor of the load. 1658341825Sdim if (CCRegUser->isMachineOpcode() && 1659341825Sdim CCRegUser->getMachineOpcode() == SystemZ::BRC) 1660341825Sdim return !N->isPredecessorOf(CCUser->getOperand(0).getNode()); 1661341825Sdim 1662341825Sdim // Otherwise, the instruction may have multiple operands, and we need to 1663341825Sdim // verify that none of them are a predecessor of the load. This is exactly 1664341825Sdim // the same check that would be done by common code if the CC setter were 1665341825Sdim // glued to the CC user, so simply invoke that check here. 1666341825Sdim if (!IsLegalToFold(N, U, CCRegUser, OptLevel, false)) 1667341825Sdim return false; 1668341825Sdim } 1669341825Sdim 1670341825Sdim return true; 1671341825Sdim} 1672341825Sdim 1673341825Sdimnamespace { 1674341825Sdim// Represents a sequence for extracting a 0/1 value from an IPM result: 1675341825Sdim// (((X ^ XORValue) + AddValue) >> Bit) 1676341825Sdimstruct IPMConversion { 1677341825Sdim IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit) 1678341825Sdim : XORValue(xorValue), AddValue(addValue), Bit(bit) {} 1679341825Sdim 1680341825Sdim int64_t XORValue; 1681341825Sdim int64_t AddValue; 1682341825Sdim unsigned Bit; 1683341825Sdim}; 1684341825Sdim} // end anonymous namespace 1685341825Sdim 1686341825Sdim// Return a sequence for getting a 1 from an IPM result when CC has a 1687341825Sdim// value in CCMask and a 0 when CC has a value in CCValid & ~CCMask. 1688341825Sdim// The handling of CC values outside CCValid doesn't matter. 1689341825Sdimstatic IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) { 1690341825Sdim // Deal with cases where the result can be taken directly from a bit 1691341825Sdim // of the IPM result. 1692341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3))) 1693341825Sdim return IPMConversion(0, 0, SystemZ::IPM_CC); 1694341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3))) 1695341825Sdim return IPMConversion(0, 0, SystemZ::IPM_CC + 1); 1696341825Sdim 1697341825Sdim // Deal with cases where we can add a value to force the sign bit 1698341825Sdim // to contain the right value. Putting the bit in 31 means we can 1699341825Sdim // use SRL rather than RISBG(L), and also makes it easier to get a 1700341825Sdim // 0/-1 value, so it has priority over the other tests below. 1701341825Sdim // 1702341825Sdim // These sequences rely on the fact that the upper two bits of the 1703341825Sdim // IPM result are zero. 1704341825Sdim uint64_t TopBit = uint64_t(1) << 31; 1705341825Sdim if (CCMask == (CCValid & SystemZ::CCMASK_0)) 1706341825Sdim return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31); 1707341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1))) 1708341825Sdim return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31); 1709341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 1710341825Sdim | SystemZ::CCMASK_1 1711341825Sdim | SystemZ::CCMASK_2))) 1712341825Sdim return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31); 1713341825Sdim if (CCMask == (CCValid & SystemZ::CCMASK_3)) 1714341825Sdim return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31); 1715341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_1 1716341825Sdim | SystemZ::CCMASK_2 1717341825Sdim | SystemZ::CCMASK_3))) 1718341825Sdim return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31); 1719341825Sdim 1720341825Sdim // Next try inverting the value and testing a bit. 0/1 could be 1721341825Sdim // handled this way too, but we dealt with that case above. 1722341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2))) 1723341825Sdim return IPMConversion(-1, 0, SystemZ::IPM_CC); 1724341825Sdim 1725341825Sdim // Handle cases where adding a value forces a non-sign bit to contain 1726341825Sdim // the right value. 1727341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2))) 1728341825Sdim return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1); 1729341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3))) 1730341825Sdim return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1); 1731341825Sdim 1732341825Sdim // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are 1733341825Sdim // can be done by inverting the low CC bit and applying one of the 1734341825Sdim // sign-based extractions above. 1735341825Sdim if (CCMask == (CCValid & SystemZ::CCMASK_1)) 1736341825Sdim return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31); 1737341825Sdim if (CCMask == (CCValid & SystemZ::CCMASK_2)) 1738341825Sdim return IPMConversion(1 << SystemZ::IPM_CC, 1739341825Sdim TopBit - (3 << SystemZ::IPM_CC), 31); 1740341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 1741341825Sdim | SystemZ::CCMASK_1 1742341825Sdim | SystemZ::CCMASK_3))) 1743341825Sdim return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31); 1744341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 1745341825Sdim | SystemZ::CCMASK_2 1746341825Sdim | SystemZ::CCMASK_3))) 1747341825Sdim return IPMConversion(1 << SystemZ::IPM_CC, 1748341825Sdim TopBit - (1 << SystemZ::IPM_CC), 31); 1749341825Sdim 1750341825Sdim llvm_unreachable("Unexpected CC combination"); 1751341825Sdim} 1752341825Sdim 1753341825SdimSDValue SystemZDAGToDAGISel::expandSelectBoolean(SDNode *Node) { 1754341825Sdim auto *TrueOp = dyn_cast<ConstantSDNode>(Node->getOperand(0)); 1755341825Sdim auto *FalseOp = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1756341825Sdim if (!TrueOp || !FalseOp) 1757341825Sdim return SDValue(); 1758341825Sdim if (FalseOp->getZExtValue() != 0) 1759341825Sdim return SDValue(); 1760341825Sdim if (TrueOp->getSExtValue() != 1 && TrueOp->getSExtValue() != -1) 1761341825Sdim return SDValue(); 1762341825Sdim 1763341825Sdim auto *CCValidOp = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1764341825Sdim auto *CCMaskOp = dyn_cast<ConstantSDNode>(Node->getOperand(3)); 1765341825Sdim if (!CCValidOp || !CCMaskOp) 1766341825Sdim return SDValue(); 1767341825Sdim int CCValid = CCValidOp->getZExtValue(); 1768341825Sdim int CCMask = CCMaskOp->getZExtValue(); 1769341825Sdim 1770341825Sdim SDLoc DL(Node); 1771341825Sdim SDValue CCReg = Node->getOperand(4); 1772341825Sdim IPMConversion IPM = getIPMConversion(CCValid, CCMask); 1773341825Sdim SDValue Result = CurDAG->getNode(SystemZISD::IPM, DL, MVT::i32, CCReg); 1774341825Sdim 1775341825Sdim if (IPM.XORValue) 1776341825Sdim Result = CurDAG->getNode(ISD::XOR, DL, MVT::i32, Result, 1777341825Sdim CurDAG->getConstant(IPM.XORValue, DL, MVT::i32)); 1778341825Sdim 1779341825Sdim if (IPM.AddValue) 1780341825Sdim Result = CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result, 1781341825Sdim CurDAG->getConstant(IPM.AddValue, DL, MVT::i32)); 1782341825Sdim 1783341825Sdim EVT VT = Node->getValueType(0); 1784341825Sdim if (VT == MVT::i32 && IPM.Bit == 31) { 1785341825Sdim unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; 1786341825Sdim Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, 1787341825Sdim CurDAG->getConstant(IPM.Bit, DL, MVT::i32)); 1788341825Sdim } else { 1789341825Sdim if (VT != MVT::i32) 1790341825Sdim Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result); 1791341825Sdim 1792341825Sdim if (TrueOp->getSExtValue() == 1) { 1793341825Sdim // The SHR/AND sequence should get optimized to an RISBG. 1794341825Sdim Result = CurDAG->getNode(ISD::SRL, DL, VT, Result, 1795341825Sdim CurDAG->getConstant(IPM.Bit, DL, MVT::i32)); 1796341825Sdim Result = CurDAG->getNode(ISD::AND, DL, VT, Result, 1797341825Sdim CurDAG->getConstant(1, DL, VT)); 1798341825Sdim } else { 1799341825Sdim // Sign-extend from IPM.Bit using a pair of shifts. 1800341825Sdim int ShlAmt = VT.getSizeInBits() - 1 - IPM.Bit; 1801341825Sdim int SraAmt = VT.getSizeInBits() - 1; 1802341825Sdim Result = CurDAG->getNode(ISD::SHL, DL, VT, Result, 1803341825Sdim CurDAG->getConstant(ShlAmt, DL, MVT::i32)); 1804341825Sdim Result = CurDAG->getNode(ISD::SRA, DL, VT, Result, 1805341825Sdim CurDAG->getConstant(SraAmt, DL, MVT::i32)); 1806341825Sdim } 1807341825Sdim } 1808341825Sdim 1809341825Sdim return Result; 1810341825Sdim} 1811341825Sdim 1812341825Sdimvoid SystemZDAGToDAGISel::PreprocessISelDAG() { 1813341825Sdim // If we have conditional immediate loads, we always prefer 1814341825Sdim // using those over an IPM sequence. 1815341825Sdim if (Subtarget->hasLoadStoreOnCond2()) 1816341825Sdim return; 1817341825Sdim 1818341825Sdim bool MadeChange = false; 1819341825Sdim 1820341825Sdim for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 1821341825Sdim E = CurDAG->allnodes_end(); 1822341825Sdim I != E;) { 1823341825Sdim SDNode *N = &*I++; 1824341825Sdim if (N->use_empty()) 1825341825Sdim continue; 1826341825Sdim 1827341825Sdim SDValue Res; 1828341825Sdim switch (N->getOpcode()) { 1829341825Sdim default: break; 1830341825Sdim case SystemZISD::SELECT_CCMASK: 1831341825Sdim Res = expandSelectBoolean(N); 1832341825Sdim break; 1833341825Sdim } 1834341825Sdim 1835341825Sdim if (Res) { 1836341825Sdim LLVM_DEBUG(dbgs() << "SystemZ DAG preprocessing replacing:\nOld: "); 1837341825Sdim LLVM_DEBUG(N->dump(CurDAG)); 1838341825Sdim LLVM_DEBUG(dbgs() << "\nNew: "); 1839341825Sdim LLVM_DEBUG(Res.getNode()->dump(CurDAG)); 1840341825Sdim LLVM_DEBUG(dbgs() << "\n"); 1841341825Sdim 1842341825Sdim CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res); 1843341825Sdim MadeChange = true; 1844341825Sdim } 1845341825Sdim } 1846341825Sdim 1847341825Sdim if (MadeChange) 1848341825Sdim CurDAG->RemoveDeadNodes(); 1849341825Sdim} 1850