1//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
10#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
11
12#include "llvm/Support/DataTypes.h"
13
14#include <memory>
15
16namespace llvm {
17
18class MCAsmBackend;
19class MCCodeEmitter;
20class MCContext;
21class MCInstrInfo;
22class MCObjectTargetWriter;
23class MCRegisterInfo;
24class MCSubtargetInfo;
25class MCTargetOptions;
26class StringRef;
27class Target;
28class Triple;
29class raw_pwrite_stream;
30class raw_ostream;
31
32namespace SystemZMC {
33// How many bytes are in the ABI-defined, caller-allocated part of
34// a stack frame.
35const int64_t CallFrameSize = 160;
36
37// The offset of the DWARF CFA from the incoming stack pointer.
38const int64_t CFAOffsetFromInitialSP = CallFrameSize;
39
40// Maps of asm register numbers to LLVM register numbers, with 0 indicating
41// an invalid register.  In principle we could use 32-bit and 64-bit register
42// classes directly, provided that we relegated the GPR allocation order
43// in SystemZRegisterInfo.td to an AltOrder and left the default order
44// as %r0-%r15.  It seems better to provide the same interface for
45// all classes though.
46extern const unsigned GR32Regs[16];
47extern const unsigned GRH32Regs[16];
48extern const unsigned GR64Regs[16];
49extern const unsigned GR128Regs[16];
50extern const unsigned FP32Regs[16];
51extern const unsigned FP64Regs[16];
52extern const unsigned FP128Regs[16];
53extern const unsigned VR32Regs[32];
54extern const unsigned VR64Regs[32];
55extern const unsigned VR128Regs[32];
56extern const unsigned AR32Regs[16];
57extern const unsigned CR64Regs[16];
58
59// Return the 0-based number of the first architectural register that
60// contains the given LLVM register.   E.g. R1D -> 1.
61unsigned getFirstReg(unsigned Reg);
62
63// Return the given register as a GR64.
64inline unsigned getRegAsGR64(unsigned Reg) {
65  return GR64Regs[getFirstReg(Reg)];
66}
67
68// Return the given register as a low GR32.
69inline unsigned getRegAsGR32(unsigned Reg) {
70  return GR32Regs[getFirstReg(Reg)];
71}
72
73// Return the given register as a high GR32.
74inline unsigned getRegAsGRH32(unsigned Reg) {
75  return GRH32Regs[getFirstReg(Reg)];
76}
77
78// Return the given register as a VR128.
79inline unsigned getRegAsVR128(unsigned Reg) {
80  return VR128Regs[getFirstReg(Reg)];
81}
82} // end namespace SystemZMC
83
84MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
85                                          const MCRegisterInfo &MRI,
86                                          MCContext &Ctx);
87
88MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
89                                        const MCSubtargetInfo &STI,
90                                        const MCRegisterInfo &MRI,
91                                        const MCTargetOptions &Options);
92
93std::unique_ptr<MCObjectTargetWriter> createSystemZObjectWriter(uint8_t OSABI);
94} // end namespace llvm
95
96// Defines symbolic names for SystemZ registers.
97// This defines a mapping from register name to register number.
98#define GET_REGINFO_ENUM
99#include "SystemZGenRegisterInfo.inc"
100
101// Defines symbolic names for the SystemZ instructions.
102#define GET_INSTRINFO_ENUM
103#include "SystemZGenInstrInfo.inc"
104
105#define GET_SUBTARGETINFO_ENUM
106#include "SystemZGenSubtargetInfo.inc"
107
108#endif
109