RISCV.td revision 360784
1331722Seadler//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2149871Sscottl// 3136849Sscottl// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4136849Sscottl// See https://llvm.org/LICENSE.txt for license information. 5136849Sscottl// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6136849Sscottl// 7136849Sscottl//===----------------------------------------------------------------------===// 8136849Sscottl 9136849Sscottlinclude "llvm/Target/Target.td" 10136849Sscottl 11136849Sscottl//===----------------------------------------------------------------------===// 12136849Sscottl// RISC-V subtarget features and instruction predicates. 13136849Sscottl//===----------------------------------------------------------------------===// 14136849Sscottl 15136849Sscottldef FeatureStdExtM 16136849Sscottl : SubtargetFeature<"m", "HasStdExtM", "true", 17136849Sscottl "'M' (Integer Multiplication and Division)">; 18136849Sscottldef HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 19136849Sscottl AssemblerPredicate<"FeatureStdExtM", 20136849Sscottl "'M' (Integer Multiplication and Division)">; 21136849Sscottl 22136849Sscottldef FeatureStdExtA 23136849Sscottl : SubtargetFeature<"a", "HasStdExtA", "true", 24136849Sscottl "'A' (Atomic Instructions)">; 25142988Sscottldef HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 26142988Sscottl AssemblerPredicate<"FeatureStdExtA", 27136849Sscottl "'A' (Atomic Instructions)">; 28136849Sscottl 29136849Sscottldef FeatureStdExtF 30136849Sscottl : SubtargetFeature<"f", "HasStdExtF", "true", 31136849Sscottl "'F' (Single-Precision Floating-Point)">; 32136849Sscottldef HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 33136849Sscottl AssemblerPredicate<"FeatureStdExtF", 34136849Sscottl "'F' (Single-Precision Floating-Point)">; 35136849Sscottl 36136849Sscottldef FeatureStdExtD 37136849Sscottl : SubtargetFeature<"d", "HasStdExtD", "true", 38136849Sscottl "'D' (Double-Precision Floating-Point)", 39136849Sscottl [FeatureStdExtF]>; 40136849Sscottldef HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 41136849Sscottl AssemblerPredicate<"FeatureStdExtD", 42136849Sscottl "'D' (Double-Precision Floating-Point)">; 43136849Sscottl 44136849Sscottldef FeatureStdExtC 45136849Sscottl : SubtargetFeature<"c", "HasStdExtC", "true", 46136849Sscottl "'C' (Compressed Instructions)">; 47136849Sscottldef HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 48136849Sscottl AssemblerPredicate<"FeatureStdExtC", 49136849Sscottl "'C' (Compressed Instructions)">; 50136849Sscottl 51136849Sscottldef FeatureRVCHints 52136849Sscottl : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true", 53136849Sscottl "Enable RVC Hint Instructions.">; 54136849Sscottldef HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, 55136849Sscottl AssemblerPredicate<"FeatureRVCHints", 56136849Sscottl "RVC Hint Instructions">; 57136849Sscottl 58136849Sscottldef Feature64Bit 59136849Sscottl : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; 60136849Sscottldef IsRV64 : Predicate<"Subtarget->is64Bit()">, 61136849Sscottl AssemblerPredicate<"Feature64Bit", 62136849Sscottl "RV64I Base Instruction Set">; 63136849Sscottldef IsRV32 : Predicate<"!Subtarget->is64Bit()">, 64190809Sdelphij AssemblerPredicate<"!Feature64Bit", 65190809Sdelphij "RV32I Base Instruction Set">; 66136849Sscottl 67190809Sdelphijdef RV64 : HwMode<"+64bit">; 68136849Sscottldef RV32 : HwMode<"-64bit">; 69136849Sscottl 70136849Sscottldef FeatureRV32E 71136849Sscottl : SubtargetFeature<"e", "IsRV32E", "true", 72136849Sscottl "Implements RV32E (provides 16 rather than 32 GPRs)">; 73136849Sscottldef IsRV32E : Predicate<"Subtarget->isRV32E()">, 74136849Sscottl AssemblerPredicate<"FeatureRV32E">; 75136849Sscottl 76136849Sscottldef FeatureRelax 77136849Sscottl : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 78136849Sscottl "Enable Linker relaxation.">; 79136849Sscottl 80136849Sscottlforeach i = {1-31} in 81136849Sscottl def FeatureReserveX#i : 82136849Sscottl SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", 83136849Sscottl "true", "Reserve X"#i>; 84136849Sscottl 85136849Sscottl//===----------------------------------------------------------------------===// 86136849Sscottl// Named operands for CSR instructions. 87136849Sscottl//===----------------------------------------------------------------------===// 88136849Sscottl 89136849Sscottlinclude "RISCVSystemOperands.td" 90136849Sscottl 91136849Sscottl//===----------------------------------------------------------------------===// 92136849Sscottl// Registers, calling conventions, instruction descriptions. 93136849Sscottl//===----------------------------------------------------------------------===// 94136849Sscottl 95136849Sscottlinclude "RISCVSchedule.td" 96136849Sscottlinclude "RISCVRegisterInfo.td" 97136849Sscottlinclude "RISCVCallingConv.td" 98136849Sscottlinclude "RISCVInstrInfo.td" 99136849Sscottlinclude "RISCVRegisterBanks.td" 100136849Sscottlinclude "RISCVSchedRocket32.td" 101136849Sscottlinclude "RISCVSchedRocket64.td" 102136849Sscottl 103136849Sscottl//===----------------------------------------------------------------------===// 104136849Sscottl// RISC-V processors supported. 105136849Sscottl//===----------------------------------------------------------------------===// 106136849Sscottl 107136849Sscottldef : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>; 108136849Sscottl 109136849Sscottldef : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit, 110136849Sscottl FeatureRVCHints]>; 111136849Sscottl 112136849Sscottldef : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>; 113149871Sscottl 114136849Sscottldef : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit, 115136849Sscottl FeatureRVCHints]>; 116136849Sscottl 117136849Sscottl 118136849Sscottl//===----------------------------------------------------------------------===// 119149871Sscottl// Define the RISC-V target. 120149871Sscottl//===----------------------------------------------------------------------===// 121149871Sscottl 122136849Sscottldef RISCVInstrInfo : InstrInfo { 123136849Sscottl let guessInstructionProperties = 0; 124136849Sscottl} 125136849Sscottl 126def RISCVAsmParser : AsmParser { 127 let ShouldEmitMatchRegisterAltName = 1; 128 let AllowDuplicateRegisterNames = 1; 129} 130 131def RISCVAsmWriter : AsmWriter { 132 int PassSubtarget = 1; 133} 134 135def RISCV : Target { 136 let InstructionSet = RISCVInstrInfo; 137 let AssemblyParsers = [RISCVAsmParser]; 138 let AssemblyWriters = [RISCVAsmWriter]; 139 let AllowRegisterRenaming = 1; 140} 141