1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9include "llvm/Target/Target.td"
10
11//===----------------------------------------------------------------------===//
12// RISC-V subtarget features and instruction predicates.
13//===----------------------------------------------------------------------===//
14
15def FeatureStdExtM
16    : SubtargetFeature<"m", "HasStdExtM", "true",
17                       "'M' (Integer Multiplication and Division)">;
18def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
19                           AssemblerPredicate<"FeatureStdExtM",
20                           "'M' (Integer Multiplication and Division)">;
21
22def FeatureStdExtA
23    : SubtargetFeature<"a", "HasStdExtA", "true",
24                       "'A' (Atomic Instructions)">;
25def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
26                           AssemblerPredicate<"FeatureStdExtA",
27                           "'A' (Atomic Instructions)">;
28
29def FeatureStdExtF
30    : SubtargetFeature<"f", "HasStdExtF", "true",
31                       "'F' (Single-Precision Floating-Point)">;
32def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
33                           AssemblerPredicate<"FeatureStdExtF",
34                           "'F' (Single-Precision Floating-Point)">;
35
36def FeatureStdExtD
37    : SubtargetFeature<"d", "HasStdExtD", "true",
38                       "'D' (Double-Precision Floating-Point)",
39                       [FeatureStdExtF]>;
40def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
41                           AssemblerPredicate<"FeatureStdExtD",
42                           "'D' (Double-Precision Floating-Point)">;
43
44def FeatureStdExtC
45    : SubtargetFeature<"c", "HasStdExtC", "true",
46                       "'C' (Compressed Instructions)">;
47def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
48                           AssemblerPredicate<"FeatureStdExtC",
49                           "'C' (Compressed Instructions)">;
50
51def FeatureRVCHints
52    : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
53                       "Enable RVC Hint Instructions.">;
54def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
55                            AssemblerPredicate<"FeatureRVCHints",
56                            "RVC Hint Instructions">;
57
58def Feature64Bit
59    : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
60def IsRV64 : Predicate<"Subtarget->is64Bit()">,
61                       AssemblerPredicate<"Feature64Bit",
62                       "RV64I Base Instruction Set">;
63def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
64                       AssemblerPredicate<"!Feature64Bit",
65                       "RV32I Base Instruction Set">;
66
67def RV64           : HwMode<"+64bit">;
68def RV32           : HwMode<"-64bit">;
69
70def FeatureRV32E
71    : SubtargetFeature<"e", "IsRV32E", "true",
72                       "Implements RV32E (provides 16 rather than 32 GPRs)">;
73def IsRV32E : Predicate<"Subtarget->isRV32E()">,
74                        AssemblerPredicate<"FeatureRV32E">;
75
76def FeatureRelax
77    : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
78                       "Enable Linker relaxation.">;
79
80foreach i = {1-31} in
81    def FeatureReserveX#i :
82        SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
83                         "true", "Reserve X"#i>;
84
85//===----------------------------------------------------------------------===//
86// Named operands for CSR instructions.
87//===----------------------------------------------------------------------===//
88
89include "RISCVSystemOperands.td"
90
91//===----------------------------------------------------------------------===//
92// Registers, calling conventions, instruction descriptions.
93//===----------------------------------------------------------------------===//
94
95include "RISCVSchedule.td"
96include "RISCVRegisterInfo.td"
97include "RISCVCallingConv.td"
98include "RISCVInstrInfo.td"
99include "RISCVRegisterBanks.td"
100include "RISCVSchedRocket32.td"
101include "RISCVSchedRocket64.td"
102
103//===----------------------------------------------------------------------===//
104// RISC-V processors supported.
105//===----------------------------------------------------------------------===//
106
107def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
108
109def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
110                     FeatureRVCHints]>;
111
112def : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>;
113
114def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit,
115                     FeatureRVCHints]>;
116
117
118//===----------------------------------------------------------------------===//
119// Define the RISC-V target.
120//===----------------------------------------------------------------------===//
121
122def RISCVInstrInfo : InstrInfo {
123  let guessInstructionProperties = 0;
124}
125
126def RISCVAsmParser : AsmParser {
127  let ShouldEmitMatchRegisterAltName = 1;
128  let AllowDuplicateRegisterNames = 1;
129}
130
131def RISCVAsmWriter : AsmWriter {
132  int PassSubtarget = 1;
133}
134
135def RISCV : Target {
136  let InstructionSet = RISCVInstrInfo;
137  let AssemblyParsers = [RISCVAsmParser];
138  let AssemblyWriters = [RISCVAsmWriter];
139  let AllowRegisterRenaming = 1;
140}
141