1//===-- PPCMachineFunctionInfo.h - Private data used for PowerPC --*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the PowerPC specific subclass of MachineFunctionInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
15
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/TargetCallingConv.h"
19
20namespace llvm {
21
22/// PPCFunctionInfo - This class is derived from MachineFunction private
23/// PowerPC target-specific information for each MachineFunction.
24class PPCFunctionInfo : public MachineFunctionInfo {
25  virtual void anchor();
26
27  /// FramePointerSaveIndex - Frame index of where the old frame pointer is
28  /// stored.  Also used as an anchor for instructions that need to be altered
29  /// when using frame pointers (dyna_add, dyna_sub.)
30  int FramePointerSaveIndex = 0;
31
32  /// ReturnAddrSaveIndex - Frame index of where the return address is stored.
33  ///
34  int ReturnAddrSaveIndex = 0;
35
36  /// Frame index where the old base pointer is stored.
37  int BasePointerSaveIndex = 0;
38
39  /// Frame index where the old PIC base pointer is stored.
40  int PICBasePointerSaveIndex = 0;
41
42  /// MustSaveLR - Indicates whether LR is defined (or clobbered) in the current
43  /// function.  This is only valid after the initial scan of the function by
44  /// PEI.
45  bool MustSaveLR = false;
46
47  /// MustSaveTOC - Indicates that the TOC save needs to be performed in the
48  /// prologue of the function. This is typically the case when there are
49  /// indirect calls in the function and it is more profitable to save the
50  /// TOC pointer in the prologue than in the block(s) containing the call(s).
51  bool MustSaveTOC = false;
52
53  /// Do we have to disable shrink-wrapping? This has to be set if we emit any
54  /// instructions that clobber LR in the entry block because discovering this
55  /// in PEI is too late (happens after shrink-wrapping);
56  bool ShrinkWrapDisabled = false;
57
58  /// Does this function have any stack spills.
59  bool HasSpills = false;
60
61  /// Does this function spill using instructions with only r+r (not r+i)
62  /// forms.
63  bool HasNonRISpills = false;
64
65  /// SpillsCR - Indicates whether CR is spilled in the current function.
66  bool SpillsCR = false;
67
68  /// Indicates whether VRSAVE is spilled in the current function.
69  bool SpillsVRSAVE = false;
70
71  /// LRStoreRequired - The bool indicates whether there is some explicit use of
72  /// the LR/LR8 stack slot that is not obvious from scanning the code.  This
73  /// requires that the code generator produce a store of LR to the stack on
74  /// entry, even though LR may otherwise apparently not be used.
75  bool LRStoreRequired = false;
76
77  /// This function makes use of the PPC64 ELF TOC base pointer (register r2).
78  bool UsesTOCBasePtr = false;
79
80  /// MinReservedArea - This is the frame size that is at least reserved in a
81  /// potential caller (parameter+linkage area).
82  unsigned MinReservedArea = 0;
83
84  /// TailCallSPDelta - Stack pointer delta used when tail calling. Maximum
85  /// amount the stack pointer is adjusted to make the frame bigger for tail
86  /// calls. Used for creating an area before the register spill area.
87  int TailCallSPDelta = 0;
88
89  /// HasFastCall - Does this function contain a fast call. Used to determine
90  /// how the caller's stack pointer should be calculated (epilog/dynamicalloc).
91  bool HasFastCall = false;
92
93  /// VarArgsFrameIndex - FrameIndex for start of varargs area.
94  int VarArgsFrameIndex = 0;
95
96  /// VarArgsStackOffset - StackOffset for start of stack
97  /// arguments.
98
99  int VarArgsStackOffset = 0;
100
101  /// VarArgsNumGPR - Index of the first unused integer
102  /// register for parameter passing.
103  unsigned VarArgsNumGPR = 0;
104
105  /// VarArgsNumFPR - Index of the first unused double
106  /// register for parameter passing.
107  unsigned VarArgsNumFPR = 0;
108
109  /// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4.
110  int CRSpillFrameIndex = 0;
111
112  /// If any of CR[2-4] need to be saved in the prologue and restored in the
113  /// epilogue then they are added to this array. This is used for the
114  /// 64-bit SVR4 ABI.
115  SmallVector<unsigned, 3> MustSaveCRs;
116
117  /// Hold onto our MachineFunction context.
118  MachineFunction &MF;
119
120  /// Whether this uses the PIC Base register or not.
121  bool UsesPICBase = false;
122
123  /// True if this function has a subset of CSRs that is handled explicitly via
124  /// copies
125  bool IsSplitCSR = false;
126
127  /// We keep track attributes for each live-in virtual registers
128  /// to use SExt/ZExt flags in later optimization.
129  std::vector<std::pair<unsigned, ISD::ArgFlagsTy>> LiveInAttrs;
130
131public:
132  explicit PPCFunctionInfo(MachineFunction &MF) : MF(MF) {}
133
134  int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
135  void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
136
137  int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; }
138  void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; }
139
140  int getBasePointerSaveIndex() const { return BasePointerSaveIndex; }
141  void setBasePointerSaveIndex(int Idx) { BasePointerSaveIndex = Idx; }
142
143  int getPICBasePointerSaveIndex() const { return PICBasePointerSaveIndex; }
144  void setPICBasePointerSaveIndex(int Idx) { PICBasePointerSaveIndex = Idx; }
145
146  unsigned getMinReservedArea() const { return MinReservedArea; }
147  void setMinReservedArea(unsigned size) { MinReservedArea = size; }
148
149  int getTailCallSPDelta() const { return TailCallSPDelta; }
150  void setTailCallSPDelta(int size) { TailCallSPDelta = size; }
151
152  /// MustSaveLR - This is set when the prolog/epilog inserter does its initial
153  /// scan of the function. It is true if the LR/LR8 register is ever explicitly
154  /// defined/clobbered in the machine function (e.g. by calls and movpctolr,
155  /// which is used in PIC generation), or if the LR stack slot is explicitly
156  /// referenced by builtin_return_address.
157  void setMustSaveLR(bool U) { MustSaveLR = U; }
158  bool mustSaveLR() const    { return MustSaveLR; }
159
160  void setMustSaveTOC(bool U) { MustSaveTOC = U; }
161  bool mustSaveTOC() const    { return MustSaveTOC; }
162
163  /// We certainly don't want to shrink wrap functions if we've emitted a
164  /// MovePCtoLR8 as that has to go into the entry, so the prologue definitely
165  /// has to go into the entry block.
166  void setShrinkWrapDisabled(bool U) { ShrinkWrapDisabled = U; }
167  bool shrinkWrapDisabled() const { return ShrinkWrapDisabled; }
168
169  void setHasSpills()      { HasSpills = true; }
170  bool hasSpills() const   { return HasSpills; }
171
172  void setHasNonRISpills()    { HasNonRISpills = true; }
173  bool hasNonRISpills() const { return HasNonRISpills; }
174
175  void setSpillsCR()       { SpillsCR = true; }
176  bool isCRSpilled() const { return SpillsCR; }
177
178  void setSpillsVRSAVE()       { SpillsVRSAVE = true; }
179  bool isVRSAVESpilled() const { return SpillsVRSAVE; }
180
181  void setLRStoreRequired() { LRStoreRequired = true; }
182  bool isLRStoreRequired() const { return LRStoreRequired; }
183
184  void setUsesTOCBasePtr()    { UsesTOCBasePtr = true; }
185  bool usesTOCBasePtr() const { return UsesTOCBasePtr; }
186
187  void setHasFastCall() { HasFastCall = true; }
188  bool hasFastCall() const { return HasFastCall;}
189
190  int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
191  void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
192
193  int getVarArgsStackOffset() const { return VarArgsStackOffset; }
194  void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; }
195
196  unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; }
197  void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; }
198
199  unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; }
200  void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; }
201
202  /// This function associates attributes for each live-in virtual register.
203  void addLiveInAttr(unsigned VReg, ISD::ArgFlagsTy Flags) {
204    LiveInAttrs.push_back(std::make_pair(VReg, Flags));
205  }
206
207  /// This function returns true if the specified vreg is
208  /// a live-in register and sign-extended.
209  bool isLiveInSExt(unsigned VReg) const;
210
211  /// This function returns true if the specified vreg is
212  /// a live-in register and zero-extended.
213  bool isLiveInZExt(unsigned VReg) const;
214
215  int getCRSpillFrameIndex() const { return CRSpillFrameIndex; }
216  void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; }
217
218  const SmallVectorImpl<unsigned> &
219    getMustSaveCRs() const { return MustSaveCRs; }
220  void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); }
221
222  void setUsesPICBase(bool uses) { UsesPICBase = uses; }
223  bool usesPICBase() const { return UsesPICBase; }
224
225  bool isSplitCSR() const { return IsSplitCSR; }
226  void setIsSplitCSR(bool s) { IsSplitCSR = s; }
227
228  MCSymbol *getPICOffsetSymbol() const;
229
230  MCSymbol *getGlobalEPSymbol() const;
231  MCSymbol *getLocalEPSymbol() const;
232  MCSymbol *getTOCOffsetSymbol() const;
233};
234
235} // end namespace llvm
236
237#endif // LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
238