ARMMCTargetDesc.h revision 239462
1227652Sgrehan//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 2227652Sgrehan// 3227652Sgrehan// The LLVM Compiler Infrastructure 4227652Sgrehan// 5227652Sgrehan// This file is distributed under the University of Illinois Open Source 6227652Sgrehan// License. See LICENSE.TXT for details. 7227652Sgrehan// 8227652Sgrehan//===----------------------------------------------------------------------===// 9227652Sgrehan// 10227652Sgrehan// This file provides ARM specific target descriptions. 11227652Sgrehan// 12227652Sgrehan//===----------------------------------------------------------------------===// 13227652Sgrehan 14227652Sgrehan#ifndef ARMMCTARGETDESC_H 15227652Sgrehan#define ARMMCTARGETDESC_H 16227652Sgrehan 17227652Sgrehan#include "llvm/Support/DataTypes.h" 18227652Sgrehan#include <string> 19227652Sgrehan 20227652Sgrehannamespace llvm { 21227652Sgrehanclass MCAsmBackend; 22227652Sgrehanclass MCCodeEmitter; 23227652Sgrehanclass MCContext; 24227652Sgrehanclass MCInstrInfo; 25227652Sgrehanclass MCObjectWriter; 26227652Sgrehanclass MCRegisterInfo; 27227652Sgrehanclass MCSubtargetInfo; 28227652Sgrehanclass StringRef; 29227652Sgrehanclass Target; 30227652Sgrehanclass raw_ostream; 31227652Sgrehan 32227652Sgrehanextern Target TheARMTarget, TheThumbTarget; 33227652Sgrehan 34227652Sgrehannamespace ARM_MC { 35227652Sgrehan std::string ParseARMTriple(StringRef TT, StringRef CPU); 36227652Sgrehan 37227652Sgrehan /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. 38227652Sgrehan /// This is exposed so Asm parser, etc. do not need to go through 39227652Sgrehan /// TargetRegistry. 40227652Sgrehan MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, 41227652Sgrehan StringRef FS); 42227652Sgrehan} 43227652Sgrehan 44227652SgrehanMCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII, 45227652Sgrehan const MCRegisterInfo &MRI, 46227652Sgrehan const MCSubtargetInfo &STI, 47227652Sgrehan MCContext &Ctx); 48227652Sgrehan 49227652SgrehanMCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT); 50227652Sgrehan 51227652Sgrehan/// createARMELFObjectWriter - Construct an ELF Mach-O object writer. 52227652SgrehanMCObjectWriter *createARMELFObjectWriter(raw_ostream &OS, 53227652Sgrehan uint8_t OSABI); 54227652Sgrehan 55227652Sgrehan/// createARMMachObjectWriter - Construct an ARM Mach-O object writer. 56227652SgrehanMCObjectWriter *createARMMachObjectWriter(raw_ostream &OS, 57227652Sgrehan bool Is64Bit, 58227652Sgrehan uint32_t CPUType, 59227652Sgrehan uint32_t CPUSubtype); 60227652Sgrehan 61227652Sgrehan} // End llvm namespace 62227652Sgrehan 63227652Sgrehan// Defines symbolic names for ARM registers. This defines a mapping from 64227652Sgrehan// register name to register number. 65227652Sgrehan// 66227652Sgrehan#define GET_REGINFO_ENUM 67227652Sgrehan#include "ARMGenRegisterInfo.inc" 68227652Sgrehan 69227652Sgrehan// Defines symbolic names for the ARM instructions. 70227652Sgrehan// 71227652Sgrehan#define GET_INSTRINFO_ENUM 72227652Sgrehan#include "ARMGenInstrInfo.inc" 73227652Sgrehan 74227652Sgrehan#define GET_SUBTARGETINFO_ENUM 75227652Sgrehan#include "ARMGenSubtargetInfo.inc" 76227652Sgrehan 77227652Sgrehan#endif 78227652Sgrehan