1//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone helper functions and enum definitions for
10// the ARM target useful for the compiler back-end and the MC libraries.
11// As such, it deliberately does not include references to LLVM core
12// code gen types, passes, etc..
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
17#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
18
19#include "ARMMCTargetDesc.h"
20#include "llvm/Support/ErrorHandling.h"
21#include "Utils/ARMBaseInfo.h"
22
23namespace llvm {
24
25namespace ARM_PROC {
26  enum IMod {
27    IE = 2,
28    ID = 3
29  };
30
31  enum IFlags {
32    F = 1,
33    I = 2,
34    A = 4
35  };
36
37  inline static const char *IFlagsToString(unsigned val) {
38    switch (val) {
39    default: llvm_unreachable("Unknown iflags operand");
40    case F: return "f";
41    case I: return "i";
42    case A: return "a";
43    }
44  }
45
46  inline static const char *IModToString(unsigned val) {
47    switch (val) {
48    default: llvm_unreachable("Unknown imod operand");
49    case IE: return "ie";
50    case ID: return "id";
51    }
52  }
53}
54
55namespace ARM_MB {
56  // The Memory Barrier Option constants map directly to the 4-bit encoding of
57  // the option field for memory barrier operations.
58  enum MemBOpt {
59    RESERVED_0 = 0,
60    OSHLD = 1,
61    OSHST = 2,
62    OSH   = 3,
63    RESERVED_4 = 4,
64    NSHLD = 5,
65    NSHST = 6,
66    NSH   = 7,
67    RESERVED_8 = 8,
68    ISHLD = 9,
69    ISHST = 10,
70    ISH   = 11,
71    RESERVED_12 = 12,
72    LD = 13,
73    ST    = 14,
74    SY    = 15
75  };
76
77  inline static const char *MemBOptToString(unsigned val, bool HasV8) {
78    switch (val) {
79    default: llvm_unreachable("Unknown memory operation");
80    case SY:    return "sy";
81    case ST:    return "st";
82    case LD: return HasV8 ? "ld" : "#0xd";
83    case RESERVED_12: return "#0xc";
84    case ISH:   return "ish";
85    case ISHST: return "ishst";
86    case ISHLD: return HasV8 ?  "ishld" : "#0x9";
87    case RESERVED_8: return "#0x8";
88    case NSH:   return "nsh";
89    case NSHST: return "nshst";
90    case NSHLD: return HasV8 ? "nshld" : "#0x5";
91    case RESERVED_4: return "#0x4";
92    case OSH:   return "osh";
93    case OSHST: return "oshst";
94    case OSHLD: return HasV8 ? "oshld" : "#0x1";
95    case RESERVED_0: return "#0x0";
96    }
97  }
98} // namespace ARM_MB
99
100namespace ARM_TSB {
101  enum TraceSyncBOpt {
102    CSYNC = 0
103  };
104
105  inline static const char *TraceSyncBOptToString(unsigned val) {
106    switch (val) {
107    default:
108      llvm_unreachable("Unknown trace synchronization barrier operation");
109      case CSYNC: return "csync";
110    }
111  }
112} // namespace ARM_TSB
113
114namespace ARM_ISB {
115  enum InstSyncBOpt {
116    RESERVED_0 = 0,
117    RESERVED_1 = 1,
118    RESERVED_2 = 2,
119    RESERVED_3 = 3,
120    RESERVED_4 = 4,
121    RESERVED_5 = 5,
122    RESERVED_6 = 6,
123    RESERVED_7 = 7,
124    RESERVED_8 = 8,
125    RESERVED_9 = 9,
126    RESERVED_10 = 10,
127    RESERVED_11 = 11,
128    RESERVED_12 = 12,
129    RESERVED_13 = 13,
130    RESERVED_14 = 14,
131    SY = 15
132  };
133
134  inline static const char *InstSyncBOptToString(unsigned val) {
135    switch (val) {
136    default:
137      llvm_unreachable("Unknown memory operation");
138      case RESERVED_0:  return "#0x0";
139      case RESERVED_1:  return "#0x1";
140      case RESERVED_2:  return "#0x2";
141      case RESERVED_3:  return "#0x3";
142      case RESERVED_4:  return "#0x4";
143      case RESERVED_5:  return "#0x5";
144      case RESERVED_6:  return "#0x6";
145      case RESERVED_7:  return "#0x7";
146      case RESERVED_8:  return "#0x8";
147      case RESERVED_9:  return "#0x9";
148      case RESERVED_10: return "#0xa";
149      case RESERVED_11: return "#0xb";
150      case RESERVED_12: return "#0xc";
151      case RESERVED_13: return "#0xd";
152      case RESERVED_14: return "#0xe";
153      case SY:          return "sy";
154    }
155  }
156} // namespace ARM_ISB
157
158/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
159///
160static inline bool isARMLowRegister(unsigned Reg) {
161  using namespace ARM;
162  switch (Reg) {
163  case R0:  case R1:  case R2:  case R3:
164  case R4:  case R5:  case R6:  case R7:
165    return true;
166  default:
167    return false;
168  }
169}
170
171/// ARMII - This namespace holds all of the target specific flags that
172/// instruction info tracks.
173///
174namespace ARMII {
175
176  /// ARM Index Modes
177  enum IndexMode {
178    IndexModeNone  = 0,
179    IndexModePre   = 1,
180    IndexModePost  = 2,
181    IndexModeUpd   = 3
182  };
183
184  /// ARM Addressing Modes
185  enum AddrMode {
186    AddrModeNone    = 0,
187    AddrMode1       = 1,
188    AddrMode2       = 2,
189    AddrMode3       = 3,
190    AddrMode4       = 4,
191    AddrMode5       = 5,
192    AddrMode6       = 6,
193    AddrModeT1_1    = 7,
194    AddrModeT1_2    = 8,
195    AddrModeT1_4    = 9,
196    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
197    AddrModeT2_i12  = 11,
198    AddrModeT2_i8   = 12,
199    AddrModeT2_so   = 13,
200    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
201    AddrModeT2_i8s4 = 15, // i8 * 4
202    AddrMode_i12    = 16,
203    AddrMode5FP16   = 17,  // i8 * 2
204    AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst
205    AddrModeT2_i7s4 = 19, // i7 * 4
206    AddrModeT2_i7s2 = 20, // i7 * 2
207    AddrModeT2_i7   = 21, // i7 * 1
208  };
209
210  inline static const char *AddrModeToString(AddrMode addrmode) {
211    switch (addrmode) {
212    case AddrModeNone:    return "AddrModeNone";
213    case AddrMode1:       return "AddrMode1";
214    case AddrMode2:       return "AddrMode2";
215    case AddrMode3:       return "AddrMode3";
216    case AddrMode4:       return "AddrMode4";
217    case AddrMode5:       return "AddrMode5";
218    case AddrMode5FP16:   return "AddrMode5FP16";
219    case AddrMode6:       return "AddrMode6";
220    case AddrModeT1_1:    return "AddrModeT1_1";
221    case AddrModeT1_2:    return "AddrModeT1_2";
222    case AddrModeT1_4:    return "AddrModeT1_4";
223    case AddrModeT1_s:    return "AddrModeT1_s";
224    case AddrModeT2_i12:  return "AddrModeT2_i12";
225    case AddrModeT2_i8:   return "AddrModeT2_i8";
226    case AddrModeT2_so:   return "AddrModeT2_so";
227    case AddrModeT2_pc:   return "AddrModeT2_pc";
228    case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
229    case AddrMode_i12:    return "AddrMode_i12";
230    case AddrModeT2_ldrex:return "AddrModeT2_ldrex";
231    case AddrModeT2_i7s4: return "AddrModeT2_i7s4";
232    case AddrModeT2_i7s2: return "AddrModeT2_i7s2";
233    case AddrModeT2_i7:   return "AddrModeT2_i7";
234    }
235  }
236
237  /// Target Operand Flag enum.
238  enum TOF {
239    //===------------------------------------------------------------------===//
240    // ARM Specific MachineOperand flags.
241
242    MO_NO_FLAG = 0,
243
244    /// MO_LO16 - On a symbol operand, this represents a relocation containing
245    /// lower 16 bit of the address. Used only via movw instruction.
246    MO_LO16 = 0x1,
247
248    /// MO_HI16 - On a symbol operand, this represents a relocation containing
249    /// higher 16 bit of the address. Used only via movt instruction.
250    MO_HI16 = 0x2,
251
252    /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
253    /// just that part of the flag set.
254    MO_OPTION_MASK = 0x3,
255
256    /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
257    /// reference is actually to the ".refptrp.FOO" symbol.  This is used for
258    /// stub symbols on windows.
259    MO_COFFSTUB = 0x4,
260
261    /// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
262    MO_GOT = 0x8,
263
264    /// MO_SBREL - On a symbol operand, this represents a static base relative
265    /// relocation. Used in movw and movt instructions.
266    MO_SBREL = 0x10,
267
268    /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
269    /// to the symbol is for an import stub.  This is used for DLL import
270    /// storage class indication on Windows.
271    MO_DLLIMPORT = 0x20,
272
273    /// MO_SECREL - On a symbol operand this indicates that the immediate is
274    /// the offset from beginning of section.
275    ///
276    /// This is the TLS offset for the COFF/Windows TLS mechanism.
277    MO_SECREL = 0x40,
278
279    /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
280    /// represents a symbol which, if indirect, will get special Darwin mangling
281    /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
282    /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
283    /// example).
284    MO_NONLAZY = 0x80,
285
286    // It's undefined behaviour if an enum overflows the range between its
287    // smallest and largest values, but since these are |ed together, it can
288    // happen. Put a sentinel in (values of this enum are stored as "unsigned
289    // char").
290    MO_UNUSED_MAXIMUM = 0xff
291  };
292
293  enum {
294    //===------------------------------------------------------------------===//
295    // Instruction Flags.
296
297    //===------------------------------------------------------------------===//
298    // This four-bit field describes the addressing mode used.
299    AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
300
301    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
302    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
303    // The index mode enums are declared in ARMBaseInfo.h
304    IndexModeShift = 5,
305    IndexModeMask  = 3 << IndexModeShift,
306
307    //===------------------------------------------------------------------===//
308    // Instruction encoding formats.
309    //
310    FormShift     = 7,
311    FormMask      = 0x3f << FormShift,
312
313    // Pseudo instructions
314    Pseudo        = 0  << FormShift,
315
316    // Multiply instructions
317    MulFrm        = 1  << FormShift,
318
319    // Branch instructions
320    BrFrm         = 2  << FormShift,
321    BrMiscFrm     = 3  << FormShift,
322
323    // Data Processing instructions
324    DPFrm         = 4  << FormShift,
325    DPSoRegFrm    = 5  << FormShift,
326
327    // Load and Store
328    LdFrm         = 6  << FormShift,
329    StFrm         = 7  << FormShift,
330    LdMiscFrm     = 8  << FormShift,
331    StMiscFrm     = 9  << FormShift,
332    LdStMulFrm    = 10 << FormShift,
333
334    LdStExFrm     = 11 << FormShift,
335
336    // Miscellaneous arithmetic instructions
337    ArithMiscFrm  = 12 << FormShift,
338    SatFrm        = 13 << FormShift,
339
340    // Extend instructions
341    ExtFrm        = 14 << FormShift,
342
343    // VFP formats
344    VFPUnaryFrm   = 15 << FormShift,
345    VFPBinaryFrm  = 16 << FormShift,
346    VFPConv1Frm   = 17 << FormShift,
347    VFPConv2Frm   = 18 << FormShift,
348    VFPConv3Frm   = 19 << FormShift,
349    VFPConv4Frm   = 20 << FormShift,
350    VFPConv5Frm   = 21 << FormShift,
351    VFPLdStFrm    = 22 << FormShift,
352    VFPLdStMulFrm = 23 << FormShift,
353    VFPMiscFrm    = 24 << FormShift,
354
355    // Thumb format
356    ThumbFrm      = 25 << FormShift,
357
358    // Miscelleaneous format
359    MiscFrm       = 26 << FormShift,
360
361    // NEON formats
362    NGetLnFrm     = 27 << FormShift,
363    NSetLnFrm     = 28 << FormShift,
364    NDupFrm       = 29 << FormShift,
365    NLdStFrm      = 30 << FormShift,
366    N1RegModImmFrm= 31 << FormShift,
367    N2RegFrm      = 32 << FormShift,
368    NVCVTFrm      = 33 << FormShift,
369    NVDupLnFrm    = 34 << FormShift,
370    N2RegVShLFrm  = 35 << FormShift,
371    N2RegVShRFrm  = 36 << FormShift,
372    N3RegFrm      = 37 << FormShift,
373    N3RegVShFrm   = 38 << FormShift,
374    NVExtFrm      = 39 << FormShift,
375    NVMulSLFrm    = 40 << FormShift,
376    NVTBLFrm      = 41 << FormShift,
377    N3RegCplxFrm  = 43 << FormShift,
378
379    //===------------------------------------------------------------------===//
380    // Misc flags.
381
382    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
383    // it doesn't have a Rn operand.
384    UnaryDP       = 1 << 13,
385
386    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
387    // a 16-bit Thumb instruction if certain conditions are met.
388    Xform16Bit    = 1 << 14,
389
390    // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
391    // instruction. Used by the parser to determine whether to require the 'S'
392    // suffix on the mnemonic (when not in an IT block) or preclude it (when
393    // in an IT block).
394    ThumbArithFlagSetting = 1 << 19,
395
396    // Whether an instruction can be included in an MVE tail-predicated loop.
397    ValidForTailPredication = 1 << 20,
398
399    //===------------------------------------------------------------------===//
400    // Code domain.
401    DomainShift   = 15,
402    DomainMask    = 15 << DomainShift,
403    DomainGeneral = 0 << DomainShift,
404    DomainVFP     = 1 << DomainShift,
405    DomainNEON    = 2 << DomainShift,
406    DomainNEONA8  = 4 << DomainShift,
407    DomainMVE     = 8 << DomainShift,
408
409    //===------------------------------------------------------------------===//
410    // Field shifts - such shifts are used to set field while generating
411    // machine instructions.
412    //
413    // FIXME: This list will need adjusting/fixing as the MC code emitter
414    // takes shape and the ARMCodeEmitter.cpp bits go away.
415    ShiftTypeShift = 4,
416
417    M_BitShift     = 5,
418    ShiftImmShift  = 5,
419    ShiftShift     = 7,
420    N_BitShift     = 7,
421    ImmHiShift     = 8,
422    SoRotImmShift  = 8,
423    RegRsShift     = 8,
424    ExtRotImmShift = 10,
425    RegRdLoShift   = 12,
426    RegRdShift     = 12,
427    RegRdHiShift   = 16,
428    RegRnShift     = 16,
429    S_BitShift     = 20,
430    W_BitShift     = 21,
431    AM3_I_BitShift = 22,
432    D_BitShift     = 22,
433    U_BitShift     = 23,
434    P_BitShift     = 24,
435    I_BitShift     = 25,
436    CondShift      = 28
437  };
438
439} // end namespace ARMII
440
441} // end namespace llvm;
442
443#endif
444