ARMDisassembler.cpp revision 314564
11541Srgrimes//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 21541Srgrimes// 31541Srgrimes// The LLVM Compiler Infrastructure 41541Srgrimes// 551138Salfred// This file is distributed under the University of Illinois Open Source 6211999Skib// License. See LICENSE.TXT for details. 71541Srgrimes// 81541Srgrimes//===----------------------------------------------------------------------===// 9106149Sdwmalone 101541Srgrimes#include "llvm/MC/MCDisassembler/MCDisassembler.h" 1164002Speter#include "MCTargetDesc/ARMAddressingModes.h" 121541Srgrimes#include "MCTargetDesc/ARMBaseInfo.h" 131541Srgrimes#include "MCTargetDesc/ARMMCExpr.h" 141541Srgrimes#include "llvm/MC/MCContext.h" 151541Srgrimes#include "llvm/MC/MCExpr.h" 161541Srgrimes#include "llvm/MC/MCFixedLenDisassembler.h" 171541Srgrimes#include "llvm/MC/MCInst.h" 18171210Speter#include "llvm/MC/MCInstrDesc.h" 191541Srgrimes#include "llvm/MC/MCSubtargetInfo.h" 201541Srgrimes#include "llvm/Support/Debug.h" 211541Srgrimes#include "llvm/Support/ErrorHandling.h" 221541Srgrimes#include "llvm/Support/LEB128.h" 231541Srgrimes#include "llvm/Support/TargetRegistry.h" 241541Srgrimes#include "llvm/Support/raw_ostream.h" 251541Srgrimes#include <vector> 261541Srgrimes 271541Srgrimesusing namespace llvm; 28194392Sjhb 29171210Speter#define DEBUG_TYPE "arm-disassembler" 301541Srgrimes 311541Srgrimestypedef MCDisassembler::DecodeStatus DecodeStatus; 321541Srgrimes 331541Srgrimesnamespace { 341541Srgrimes // Handles the condition code status of instructions in IT blocks 351541Srgrimes class ITStatus 361541Srgrimes { 371541Srgrimes public: 381541Srgrimes // Returns the condition code for instruction in IT block 391541Srgrimes unsigned getITCC() { 401541Srgrimes unsigned CC = ARMCC::AL; 411541Srgrimes if (instrInITBlock()) 421541Srgrimes CC = ITStates.back(); 431541Srgrimes return CC; 441541Srgrimes } 451541Srgrimes 461541Srgrimes // Advances the IT block state to the next T or E 471541Srgrimes void advanceITState() { 48171210Speter ITStates.pop_back(); 491541Srgrimes } 50171210Speter 511541Srgrimes // Returns true if the current instruction is in an IT block 521541Srgrimes bool instrInITBlock() { 531541Srgrimes return !ITStates.empty(); 541541Srgrimes } 551541Srgrimes 56171210Speter // Returns true if current instruction is the last instruction in an IT block 571541Srgrimes bool instrLastInITBlock() { 58171210Speter return ITStates.size() == 1; 591541Srgrimes } 601541Srgrimes 611541Srgrimes // Called when decoding an IT instruction. Sets the IT state for the following 62171210Speter // instructions that for the IT block. Firstcond and Mask correspond to the 631541Srgrimes // fields in the IT instruction encoding. 641541Srgrimes void setITState(char Firstcond, char Mask) { 651541Srgrimes // (3 - the number of trailing zeros) is the number of then / else. 661541Srgrimes unsigned CondBit0 = Firstcond & 1; 671541Srgrimes unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 681541Srgrimes unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 691541Srgrimes assert(NumTZ <= 3 && "Invalid IT mask!"); 701541Srgrimes // push condition codes onto the stack the correct order for the pops 711541Srgrimes for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 72171210Speter bool T = ((Mask >> Pos) & 1) == CondBit0; 73171210Speter if (T) 74171210Speter ITStates.push_back(CCBits); 751541Srgrimes else 761541Srgrimes ITStates.push_back(CCBits ^ 1); 771541Srgrimes } 781541Srgrimes ITStates.push_back(CCBits); 791541Srgrimes } 801541Srgrimes 81171210Speter private: 821541Srgrimes std::vector<unsigned char> ITStates; 831541Srgrimes }; 841541Srgrimes} 851541Srgrimes 861541Srgrimesnamespace { 871541Srgrimes/// ARM disassembler for all ARM platforms. 881541Srgrimesclass ARMDisassembler : public MCDisassembler { 891541Srgrimespublic: 901541Srgrimes ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 911541Srgrimes MCDisassembler(STI, Ctx) { 921541Srgrimes } 931541Srgrimes 94171210Speter ~ARMDisassembler() override {} 951541Srgrimes 961541Srgrimes DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 97171210Speter ArrayRef<uint8_t> Bytes, uint64_t Address, 98171210Speter raw_ostream &VStream, 991541Srgrimes raw_ostream &CStream) const override; 1001541Srgrimes}; 1011541Srgrimes 1021541Srgrimes/// Thumb disassembler for all Thumb platforms. 1031541Srgrimesclass ThumbDisassembler : public MCDisassembler { 1041541Srgrimespublic: 1051541Srgrimes ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 1061541Srgrimes MCDisassembler(STI, Ctx) { 1071541Srgrimes } 1081541Srgrimes 109171210Speter ~ThumbDisassembler() override {} 1101541Srgrimes 111171210Speter DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 112171210Speter ArrayRef<uint8_t> Bytes, uint64_t Address, 113171210Speter raw_ostream &VStream, 1141541Srgrimes raw_ostream &CStream) const override; 1151541Srgrimes 1161541Srgrimesprivate: 1171541Srgrimes mutable ITStatus ITBlock; 118171210Speter DecodeStatus AddThumbPredicate(MCInst&) const; 119171210Speter void UpdateThumbVFPPredicate(MCInst&) const; 120171210Speter}; 121171210Speter} 122171210Speter 123171210Speterstatic bool Check(DecodeStatus &Out, DecodeStatus In) { 124171210Speter switch (In) { 1251541Srgrimes case MCDisassembler::Success: 1261541Srgrimes // Out stays the same. 1271541Srgrimes return true; 1281541Srgrimes case MCDisassembler::SoftFail: 12914220Speter Out = In; 1301541Srgrimes return true; 1311541Srgrimes case MCDisassembler::Fail: 1321541Srgrimes Out = In; 1331541Srgrimes return false; 1341541Srgrimes } 135171210Speter llvm_unreachable("Invalid DecodeStatus!"); 1368019Sache} 1378019Sache 1381541Srgrimes 139171210Speter// Forward declare these because the autogenerated code will reference them. 140171210Speter// Definitions are further down. 1411541Srgrimesstatic DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1421541Srgrimes uint64_t Address, const void *Decoder); 1431541Srgrimesstatic DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 1441541Srgrimes unsigned RegNo, uint64_t Address, 1451541Srgrimes const void *Decoder); 1461541Srgrimesstatic DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 1471541Srgrimes unsigned RegNo, uint64_t Address, 1481541Srgrimes const void *Decoder); 1491541Srgrimesstatic DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1501541Srgrimes uint64_t Address, const void *Decoder); 151171210Speterstatic DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 152171210Speter uint64_t Address, const void *Decoder); 153171210Speterstatic DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 154171210Speter uint64_t Address, const void *Decoder); 155171210Speterstatic DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 156171210Speter uint64_t Address, const void *Decoder); 1571541Srgrimesstatic DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1581541Srgrimes uint64_t Address, const void *Decoder); 159171210Speterstatic DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 160171210Speter uint64_t Address, const void *Decoder); 16114220Speterstatic DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 16214220Speter uint64_t Address, const void *Decoder); 16314220Speterstatic DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 164177634Sdfr unsigned RegNo, 1651541Srgrimes uint64_t Address, 166171210Speter const void *Decoder); 167194392Sjhbstatic DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 168194392Sjhb uint64_t Address, const void *Decoder); 1691541Srgrimesstatic DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 170127891Sdfr uint64_t Address, const void *Decoder); 1711541Srgrimesstatic DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 172194392Sjhb unsigned RegNo, uint64_t Address, 173194392Sjhb const void *Decoder); 174194392Sjhb 1751549Srgrimesstatic DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1762442Sdg uint64_t Address, const void *Decoder); 1771541Srgrimesstatic DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1781541Srgrimes uint64_t Address, const void *Decoder); 1792729Sdfrstatic DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1802729Sdfr uint64_t Address, const void *Decoder); 1811541Srgrimesstatic DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1821541Srgrimes uint64_t Address, const void *Decoder); 183171210Speterstatic DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 184171210Speter uint64_t Address, const void *Decoder); 185178888Sjulian 1862297Swollmanstatic DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 18714220Speter uint64_t Address, const void *Decoder); 18814220Speterstatic DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 18914220Speter uint64_t Address, const void *Decoder); 1901541Srgrimesstatic DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 1911541Srgrimes unsigned Insn, 1921541Srgrimes uint64_t Address, 1931541Srgrimes const void *Decoder); 19432889Sphkstatic DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 19532889Sphk uint64_t Address, const void *Decoder); 19632889Sphkstatic DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 19732889Sphk uint64_t Address, const void *Decoder); 1981541Srgrimesstatic DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 1991541Srgrimes uint64_t Address, const void *Decoder); 2001541Srgrimesstatic DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 2011541Srgrimes uint64_t Address, const void *Decoder); 2021541Srgrimes 2031541Srgrimesstatic DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 2041541Srgrimes unsigned Insn, 2051541Srgrimes uint64_t Adddress, 2061541Srgrimes const void *Decoder); 207171210Speterstatic DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2081541Srgrimes uint64_t Address, const void *Decoder); 209171210Speterstatic DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 210171210Speter uint64_t Address, const void *Decoder); 211171210Speterstatic DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2121541Srgrimes uint64_t Address, const void *Decoder); 2131541Srgrimesstatic DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2141541Srgrimes uint64_t Address, const void *Decoder); 21535938Sdysonstatic DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 21635938Sdyson uint64_t Address, const void *Decoder); 21728400Speterstatic DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 21825582Speter uint64_t Address, const void *Decoder); 21929349Speterstatic DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2202124Sdg uint64_t Address, const void *Decoder); 2212124Sdgstatic DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2222124Sdg uint64_t Address, const void *Decoder); 2232124Sdgstatic DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2242124Sdg uint64_t Address, const void *Decoder); 2252124Sdgstatic DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2262124Sdg uint64_t Address, const void *Decoder); 2272124Sdgstatic DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2282124Sdg uint64_t Address, const void *Decoder); 2292124Sdgstatic DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 230194919Sjhb uint64_t Address, const void *Decoder); 23112865Speterstatic DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 23212865Speter uint64_t Address, const void *Decoder); 23359829Speterstatic DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 234194919Sjhb uint64_t Address, const void *Decoder); 23512865Speterstatic DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 23612865Speter uint64_t Address, const void *Decoder); 23712865Speterstatic DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 23812865Speter uint64_t Address, const void *Decoder); 239194919Sjhbstatic DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 24012865Speter uint64_t Address, const void *Decoder); 24112865Speterstatic DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 24225582Speter uint64_t Address, const void *Decoder); 24325582Speterstatic DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 24425582Speter uint64_t Address, const void *Decoder); 245156138Sdavidxustatic DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 246156138Sdavidxu uint64_t Address, const void *Decoder); 247156138Sdavidxustatic DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 248156138Sdavidxu uint64_t Address, const void *Decoder); 249156138Sdavidxustatic DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 25025582Speter uint64_t Address, const void *Decoder); 25114220Speterstatic DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 25214220Speter uint64_t Address, const void *Decoder); 25314220Speterstatic DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 25414220Speter uint64_t Address, const void *Decoder); 25514220Speterstatic DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 25614220Speter uint64_t Address, const void *Decoder); 25714220Speterstatic DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 258137875Smarks uint64_t Address, const void *Decoder); 25914220Speterstatic DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 26014220Speter uint64_t Address, const void *Decoder); 26114220Speterstatic DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 26229349Speter uint64_t Address, const void *Decoder); 26324452Speterstatic DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 26424440Speter uint64_t Address, const void *Decoder); 265151868Sdavidxustatic DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 266151868Sdavidxu uint64_t Address, const void *Decoder); 267151868Sdavidxustatic DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 268152846Sdavidxu uint64_t Address, const void *Decoder); 269152846Sdavidxustatic DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 270152846Sdavidxu uint64_t Address, const void *Decoder); 271152846Sdavidxustatic DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 272152846Sdavidxu uint64_t Address, const void *Decoder); 273152846Sdavidxustatic DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 27425537Sdfr uint64_t Address, const void *Decoder); 27525537Sdfrstatic DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 27625537Sdfr uint64_t Address, const void *Decoder); 27725537Sdfrstatic DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 27825537Sdfr uint64_t Address, const void *Decoder); 27925537Sdfrstatic DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 28025537Sdfr uint64_t Address, const void *Decoder); 28125537Sdfrstatic DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 28235938Sdyson uint64_t Address, const void *Decoder); 28325537Sdfrstatic DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 28435938Sdyson uint64_t Address, const void *Decoder); 28535938Sdysonstatic DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 28635938Sdyson uint64_t Address, const void *Decoder); 28735938Sdysonstatic DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 28835938Sdyson uint64_t Address, const void *Decoder); 28935938Sdysonstatic DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 29035938Sdyson uint64_t Address, const void *Decoder); 29125537Sdfrstatic DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 29225537Sdfr uint64_t Address, const void *Decoder); 29325537Sdfrstatic DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 29425537Sdfr uint64_t Address, const void *Decoder); 29525537Sdfrstatic DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 29625537Sdfr uint64_t Address, const void *Decoder); 29725537Sdfrstatic DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 29825537Sdfr uint64_t Address, const void *Decoder); 299147814Sjhbstatic DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 300147814Sjhb uint64_t Address, const void *Decoder); 30125537Sdfrstatic DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 30225537Sdfr uint64_t Address, const void *Decoder); 30325537Sdfrstatic DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 30425537Sdfr uint64_t Address, const void *Decoder); 30525537Sdfrstatic DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 30625537Sdfr uint64_t Address, const void *Decoder); 307194392Sjhbstatic DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 30851138Salfred uint64_t Address, const void *Decoder); 30951138Salfredstatic DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 31025537Sdfr uint64_t Address, const void *Decoder); 31125537Sdfrstatic DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 31225537Sdfr uint64_t Address, const void *Decoder); 31325537Sdfrstatic DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 31425537Sdfr uint64_t Address, const void *Decoder); 31525537Sdfrstatic DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 31625537Sdfr uint64_t Address, const void *Decoder); 31725537Sdfrstatic DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 31825537Sdfr uint64_t Address, const void *Decoder); 31925537Sdfrstatic DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 32028400Speter uint64_t Address, const void *Decoder); 32156115Speter 32256115Speter 32336034Speterstatic DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 32426671Sdyson uint64_t Address, const void *Decoder); 32526671Sdysonstatic DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 32626671Sdyson uint64_t Address, const void *Decoder); 32726671Sdysonstatic DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 328151868Sdavidxu uint64_t Address, const void *Decoder); 329151868Sdavidxustatic DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 330151868Sdavidxu uint64_t Address, const void *Decoder); 33126671Sdysonstatic DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 33269514Sjake uint64_t Address, const void *Decoder); 33369514Sjakestatic DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 33426671Sdyson uint64_t Address, const void *Decoder); 33526671Sdysonstatic DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 33629391Sphk uint64_t Address, const void *Decoder); 33734925Sdufaultstatic DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 33834925Sdufault uint64_t Address, const void *Decoder); 33934925Sdufaultstatic DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 34034925Sdufault uint64_t Address, const void *Decoder); 34134925Sdufaultstatic DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 34234925Sdufault uint64_t Address, const void *Decoder); 34334925Sdufaultstatic DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 34434925Sdufault uint64_t Address, const void* Decoder); 34535938Sdysonstatic DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 346194392Sjhb uint64_t Address, const void* Decoder); 34741089Speterstatic DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 34846155Sphk uint64_t Address, const void* Decoder); 349211999Skibstatic DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 35051791Smarcel uint64_t Address, const void* Decoder); 35151791Smarcelstatic DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 352194392Sjhb uint64_t Address, const void *Decoder); 35351791Smarcelstatic DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 354194392Sjhb uint64_t Address, const void *Decoder); 355112895Sjeffstatic DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 356112895Sjeff uint64_t Address, const void *Decoder); 35756271Srwatsonstatic DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 35856271Srwatson uint64_t Address, const void *Decoder); 35956271Srwatsonstatic DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 36056271Srwatson uint64_t Address, const void *Decoder); 36156271Srwatsonstatic DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 36256271Srwatson uint64_t Address, const void *Decoder); 36356271Srwatsonstatic DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 36456271Srwatson uint64_t Address, const void *Decoder); 36554803Srwatsonstatic DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 36654803Srwatson uint64_t Address, const void *Decoder); 36754803Srwatsonstatic DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 36854803Srwatson uint64_t Address, const void *Decoder); 36955943Sjasonestatic DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 37056115Speter uint64_t Address, const void *Decoder); 37156115Speterstatic DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 37259288Sjlemon uint64_t Address, const void *Decoder); 37359288Sjlemonstatic DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 37498198Srwatson uint64_t Address, const void *Decoder); 37598198Srwatsonstatic DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 37698198Srwatson uint64_t Address, const void *Decoder); 37798198Srwatsonstatic DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 37898198Srwatson uint64_t Address, const void *Decoder); 37998198Srwatsonstatic DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 380183362Sjhb uint64_t Address, const void *Decoder); 38175039Srwatsonstatic DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 38275039Srwatson uint64_t Address, const void *Decoder); 38375039Srwatsonstatic DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 38475427Srwatson uint64_t Address, const void *Decoder); 385194392Sjhbstatic DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 38683796Srwatson uint64_t Address, const void *Decoder); 387211999Skibstatic DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 38885891Sphk uint64_t Address, const void *Decoder); 389177091Sjeffstatic DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 390177091Sjeff uint64_t Address, const void *Decoder); 391177091Sjeffstatic DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 392177091Sjeff uint64_t Address, const void *Decoder); 393177091Sjeffstatic DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 394100897Srwatson uint64_t Address, const void *Decoder); 395100897Srwatson 396100897Srwatsonstatic DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 397100897Srwatson uint64_t Address, const void *Decoder); 398100897Srwatsonstatic DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val, 399100897Srwatson uint64_t Address, const void *Decoder); 40094936Smux#include "ARMGenDisassemblerTables.inc" 40196084Smux 40297372Smarcelstatic MCDisassembler *createARMDisassembler(const Target &T, 40399856Salfred const MCSubtargetInfo &STI, 404101426Srwatson MCContext &Ctx) { 405122540Smckusick return new ARMDisassembler(STI, Ctx); 406122540Smckusick} 407122540Smckusick 408122540Smckusickstatic MCDisassembler *createThumbDisassembler(const Target &T, 409103575Salfred const MCSubtargetInfo &STI, 410103575Salfred MCContext &Ctx) { 411103575Salfred return new ThumbDisassembler(STI, Ctx); 412103575Salfred} 413103575Salfred 414103575Salfred// Post-decoding checks 415103575Salfredstatic DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 416103575Salfred uint64_t Address, raw_ostream &OS, 417103575Salfred raw_ostream &CS, 418103575Salfred uint32_t Insn, 419105692Srwatson DecodeStatus Result) 420105692Srwatson{ 421105692Srwatson switch (MI.getOpcode()) { 422104731Srwatson case ARM::HVC: { 423104731Srwatson // HVC is undefined if condition = 0xf otherwise upredictable 424104731Srwatson // if condition != 0xe 425106467Srwatson uint32_t Cond = (Insn >> 28) & 0xF; 426105950Speter if (Cond == 0xF) 427105950Speter return MCDisassembler::Fail; 428105692Srwatson if (Cond != 0xE) 429105692Srwatson return MCDisassembler::SoftFail; 430105692Srwatson return Result; 431106978Sdeischen } 432106978Sdeischen default: return Result; 433106978Sdeischen } 434107914Sdillon} 435108406Srwatson 436108406SrwatsonDecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 437108406Srwatson ArrayRef<uint8_t> Bytes, 438108406Srwatson uint64_t Address, raw_ostream &OS, 439112895Sjeff raw_ostream &CS) const { 440112902Sjeff CommentStream = &CS; 441112902Sjeff 442112902Sjeff assert(!STI.getFeatureBits()[ARM::ModeThumb] && 443112902Sjeff "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 444112909Sjeff "mode!"); 445112909Sjeff 446113276Smike // We want to read exactly 4 bytes of data. 447115800Srwatson if (Bytes.size() < 4) { 448115800Srwatson Size = 0; 449115800Srwatson return MCDisassembler::Fail; 450177091Sjeff } 451125369Sdeischen 452127484Smtm // Encoded as a small-endian 32-bit word in the stream. 453127484Smtm uint32_t Insn = 454132117Sphk (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 455136831Srwatson 456136831Srwatson // Calling the auto-generated decoder function. 457136831Srwatson DecodeStatus Result = 458136831Srwatson decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 459136831Srwatson if (Result != MCDisassembler::Fail) { 460136831Srwatson Size = 4; 461136831Srwatson return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 462136831Srwatson } 463136831Srwatson 464139013Sdavidxu // VFP and NEON instructions, similarly, are shared between ARM 465145435Sdavidxu // and Thumb modes. 466151317Sdavidxu Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI); 467156138Sdavidxu if (Result != MCDisassembler::Fail) { 468156138Sdavidxu Size = 4; 469156138Sdavidxu return Result; 470156138Sdavidxu } 471156138Sdavidxu 472156138Sdavidxu Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI); 473153681Sphk if (Result != MCDisassembler::Fail) { 474155328Sdavidxu Size = 4; 475157039Sdavidxu return Result; 476162498Sdavidxu } 477162498Sdavidxu 478162498Sdavidxu Result = 479161679Sdavidxu decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI); 480161679Sdavidxu if (Result != MCDisassembler::Fail) { 481163953Srrs Size = 4; 482163953Srrs // Add a fake predicate operand, because we share these instruction 483163953Srrs // definitions with Thumb2 where these instructions are predicable. 484163953Srrs if (!DecodePredicateOperand(MI, 0xE, Address, this)) 485171210Speter return MCDisassembler::Fail; 486171210Speter return Result; 487171210Speter } 488171210Speter 489171210Speter Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address, 490171210Speter this, STI); 491171861Sdavidxu if (Result != MCDisassembler::Fail) { 492175165Sjhb Size = 4; 493175165Sjhb // Add a fake predicate operand, because we share these instruction 494176731Sjeff // definitions with Thumb2 where these instructions are predicable. 495176731Sjeff if (!DecodePredicateOperand(MI, 0xE, Address, this)) 496176731Sjeff return MCDisassembler::Fail; 497176731Sjeff return Result; 498176731Sjeff } 499177790Skib 500177790Skib Result = 501177790Skib decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI); 502177790Skib if (Result != MCDisassembler::Fail) { 503177790Skib Size = 4; 504177790Skib // Add a fake predicate operand, because we share these instruction 505177790Skib // definitions with Thumb2 where these instructions are predicable. 506177790Skib if (!DecodePredicateOperand(MI, 0xE, Address, this)) 507177790Skib return MCDisassembler::Fail; 508177790Skib return Result; 509177790Skib } 510177790Skib 511177790Skib Result = 512177790Skib decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI); 513177790Skib if (Result != MCDisassembler::Fail) { 514181905Sed Size = 4; 515184589Sdfr return Result; 516191675Sjamie } 517191675Sjamie 518191675Sjamie Result = 519194263Sjhb decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI); 520194919Sjhb if (Result != MCDisassembler::Fail) { 521194919Sjhb Size = 4; 522194919Sjhb return Result; 523195459Strasz } 524197637Srwatson 525197637Srwatson Size = 0; 526197637Srwatson return MCDisassembler::Fail; 527197637Srwatson} 528197637Srwatson 529197637Srwatsonnamespace llvm { 530197637Srwatsonextern const MCInstrDesc ARMInsts[]; 531197637Srwatson} 532198510Skib 5331541Srgrimes/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 534/// immediate Value in the MCInst. The immediate Value has had any PC 535/// adjustment made by the caller. If the instruction is a branch instruction 536/// then isBranch is true, else false. If the getOpInfo() function was set as 537/// part of the setupForSymbolicDisassembly() call then that function is called 538/// to get any symbolic information at the Address for this instruction. If 539/// that returns non-zero then the symbolic information it returns is used to 540/// create an MCExpr and that is added as an operand to the MCInst. If 541/// getOpInfo() returns zero and isBranch is true then a symbol look up for 542/// Value is done and if a symbol is found an MCExpr is created with that, else 543/// an MCExpr with Value is created. This function returns true if it adds an 544/// operand to the MCInst and false otherwise. 545static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 546 bool isBranch, uint64_t InstSize, 547 MCInst &MI, const void *Decoder) { 548 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 549 // FIXME: Does it make sense for value to be negative? 550 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 551 /* Offset */ 0, InstSize); 552} 553 554/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 555/// referenced by a load instruction with the base register that is the Pc. 556/// These can often be values in a literal pool near the Address of the 557/// instruction. The Address of the instruction and its immediate Value are 558/// used as a possible literal pool entry. The SymbolLookUp call back will 559/// return the name of a symbol referenced by the literal pool's entry if 560/// the referenced address is that of a symbol. Or it will return a pointer to 561/// a literal 'C' string if the referenced address of the literal pool's entry 562/// is an address into a section with 'C' string literals. 563static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 564 const void *Decoder) { 565 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 566 Dis->tryAddingPcLoadReferenceComment(Value, Address); 567} 568 569// Thumb1 instructions don't have explicit S bits. Rather, they 570// implicitly set CPSR. Since it's not represented in the encoding, the 571// auto-generated decoder won't inject the CPSR operand. We need to fix 572// that as a post-pass. 573static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 576 MCInst::iterator I = MI.begin(); 577 for (unsigned i = 0; i < NumOps; ++i, ++I) { 578 if (I == MI.end()) break; 579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 580 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 581 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 582 return; 583 } 584 } 585 586 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 587} 588 589// Most Thumb instructions don't have explicit predicates in the 590// encoding, but rather get their predicates from IT context. We need 591// to fix up the predicate operands using this context information as a 592// post-pass. 593MCDisassembler::DecodeStatus 594ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 595 MCDisassembler::DecodeStatus S = Success; 596 597 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 598 599 // A few instructions actually have predicates encoded in them. Don't 600 // try to overwrite it if we're seeing one of those. 601 switch (MI.getOpcode()) { 602 case ARM::tBcc: 603 case ARM::t2Bcc: 604 case ARM::tCBZ: 605 case ARM::tCBNZ: 606 case ARM::tCPS: 607 case ARM::t2CPS3p: 608 case ARM::t2CPS2p: 609 case ARM::t2CPS1p: 610 case ARM::tMOVSr: 611 case ARM::tSETEND: 612 // Some instructions (mostly conditional branches) are not 613 // allowed in IT blocks. 614 if (ITBlock.instrInITBlock()) 615 S = SoftFail; 616 else 617 return Success; 618 break; 619 case ARM::t2HINT: 620 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 621 S = SoftFail; 622 break; 623 case ARM::tB: 624 case ARM::t2B: 625 case ARM::t2TBB: 626 case ARM::t2TBH: 627 // Some instructions (mostly unconditional branches) can 628 // only appears at the end of, or outside of, an IT. 629 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 630 S = SoftFail; 631 break; 632 default: 633 break; 634 } 635 636 // If we're in an IT block, base the predicate on that. Otherwise, 637 // assume a predicate of AL. 638 unsigned CC; 639 CC = ITBlock.getITCC(); 640 if (CC == 0xF) 641 CC = ARMCC::AL; 642 if (ITBlock.instrInITBlock()) 643 ITBlock.advanceITState(); 644 645 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 646 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 647 MCInst::iterator I = MI.begin(); 648 for (unsigned i = 0; i < NumOps; ++i, ++I) { 649 if (I == MI.end()) break; 650 if (OpInfo[i].isPredicate()) { 651 I = MI.insert(I, MCOperand::createImm(CC)); 652 ++I; 653 if (CC == ARMCC::AL) 654 MI.insert(I, MCOperand::createReg(0)); 655 else 656 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 657 return S; 658 } 659 } 660 661 I = MI.insert(I, MCOperand::createImm(CC)); 662 ++I; 663 if (CC == ARMCC::AL) 664 MI.insert(I, MCOperand::createReg(0)); 665 else 666 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 667 668 return S; 669} 670 671// Thumb VFP instructions are a special case. Because we share their 672// encodings between ARM and Thumb modes, and they are predicable in ARM 673// mode, the auto-generated decoder will give them an (incorrect) 674// predicate operand. We need to rewrite these operands based on the IT 675// context as a post-pass. 676void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 677 unsigned CC; 678 CC = ITBlock.getITCC(); 679 if (ITBlock.instrInITBlock()) 680 ITBlock.advanceITState(); 681 682 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 683 MCInst::iterator I = MI.begin(); 684 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 685 for (unsigned i = 0; i < NumOps; ++i, ++I) { 686 if (OpInfo[i].isPredicate() ) { 687 I->setImm(CC); 688 ++I; 689 if (CC == ARMCC::AL) 690 I->setReg(0); 691 else 692 I->setReg(ARM::CPSR); 693 return; 694 } 695 } 696} 697 698DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 699 ArrayRef<uint8_t> Bytes, 700 uint64_t Address, 701 raw_ostream &OS, 702 raw_ostream &CS) const { 703 CommentStream = &CS; 704 705 assert(STI.getFeatureBits()[ARM::ModeThumb] && 706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 707 708 // We want to read exactly 2 bytes of data. 709 if (Bytes.size() < 2) { 710 Size = 0; 711 return MCDisassembler::Fail; 712 } 713 714 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 715 DecodeStatus Result = 716 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 717 if (Result != MCDisassembler::Fail) { 718 Size = 2; 719 Check(Result, AddThumbPredicate(MI)); 720 return Result; 721 } 722 723 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 724 STI); 725 if (Result) { 726 Size = 2; 727 bool InITBlock = ITBlock.instrInITBlock(); 728 Check(Result, AddThumbPredicate(MI)); 729 AddThumb1SBit(MI, InITBlock); 730 return Result; 731 } 732 733 Result = 734 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 735 if (Result != MCDisassembler::Fail) { 736 Size = 2; 737 738 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 739 // the Thumb predicate. 740 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 741 Result = MCDisassembler::SoftFail; 742 743 Check(Result, AddThumbPredicate(MI)); 744 745 // If we find an IT instruction, we need to parse its condition 746 // code and mask operands so that we can apply them correctly 747 // to the subsequent instructions. 748 if (MI.getOpcode() == ARM::t2IT) { 749 750 unsigned Firstcond = MI.getOperand(0).getImm(); 751 unsigned Mask = MI.getOperand(1).getImm(); 752 ITBlock.setITState(Firstcond, Mask); 753 } 754 755 return Result; 756 } 757 758 // We want to read exactly 4 bytes of data. 759 if (Bytes.size() < 4) { 760 Size = 0; 761 return MCDisassembler::Fail; 762 } 763 764 uint32_t Insn32 = 765 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 766 Result = 767 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 768 if (Result != MCDisassembler::Fail) { 769 Size = 4; 770 bool InITBlock = ITBlock.instrInITBlock(); 771 Check(Result, AddThumbPredicate(MI)); 772 AddThumb1SBit(MI, InITBlock); 773 return Result; 774 } 775 776 Result = 777 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 778 if (Result != MCDisassembler::Fail) { 779 Size = 4; 780 Check(Result, AddThumbPredicate(MI)); 781 return Result; 782 } 783 784 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 785 Result = 786 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 787 if (Result != MCDisassembler::Fail) { 788 Size = 4; 789 UpdateThumbVFPPredicate(MI); 790 return Result; 791 } 792 } 793 794 Result = 795 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 796 if (Result != MCDisassembler::Fail) { 797 Size = 4; 798 return Result; 799 } 800 801 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 802 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 803 STI); 804 if (Result != MCDisassembler::Fail) { 805 Size = 4; 806 Check(Result, AddThumbPredicate(MI)); 807 return Result; 808 } 809 } 810 811 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 812 uint32_t NEONLdStInsn = Insn32; 813 NEONLdStInsn &= 0xF0FFFFFF; 814 NEONLdStInsn |= 0x04000000; 815 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 816 Address, this, STI); 817 if (Result != MCDisassembler::Fail) { 818 Size = 4; 819 Check(Result, AddThumbPredicate(MI)); 820 return Result; 821 } 822 } 823 824 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 825 uint32_t NEONDataInsn = Insn32; 826 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 827 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 828 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 829 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 830 Address, this, STI); 831 if (Result != MCDisassembler::Fail) { 832 Size = 4; 833 Check(Result, AddThumbPredicate(MI)); 834 return Result; 835 } 836 837 uint32_t NEONCryptoInsn = Insn32; 838 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 839 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 840 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 841 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 842 Address, this, STI); 843 if (Result != MCDisassembler::Fail) { 844 Size = 4; 845 return Result; 846 } 847 848 uint32_t NEONv8Insn = Insn32; 849 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 850 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 851 this, STI); 852 if (Result != MCDisassembler::Fail) { 853 Size = 4; 854 return Result; 855 } 856 } 857 858 Size = 0; 859 return MCDisassembler::Fail; 860} 861 862 863extern "C" void LLVMInitializeARMDisassembler() { 864 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 865 createARMDisassembler); 866 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 867 createARMDisassembler); 868 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 869 createThumbDisassembler); 870 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 871 createThumbDisassembler); 872} 873 874static const uint16_t GPRDecoderTable[] = { 875 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 876 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 877 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 878 ARM::R12, ARM::SP, ARM::LR, ARM::PC 879}; 880 881static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 882 uint64_t Address, const void *Decoder) { 883 if (RegNo > 15) 884 return MCDisassembler::Fail; 885 886 unsigned Register = GPRDecoderTable[RegNo]; 887 Inst.addOperand(MCOperand::createReg(Register)); 888 return MCDisassembler::Success; 889} 890 891static DecodeStatus 892DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 893 uint64_t Address, const void *Decoder) { 894 DecodeStatus S = MCDisassembler::Success; 895 896 if (RegNo == 15) 897 S = MCDisassembler::SoftFail; 898 899 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 900 901 return S; 902} 903 904static DecodeStatus 905DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 906 uint64_t Address, const void *Decoder) { 907 DecodeStatus S = MCDisassembler::Success; 908 909 if (RegNo == 15) 910 { 911 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 912 return MCDisassembler::Success; 913 } 914 915 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 916 return S; 917} 918 919static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 920 uint64_t Address, const void *Decoder) { 921 if (RegNo > 7) 922 return MCDisassembler::Fail; 923 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 924} 925 926static const uint16_t GPRPairDecoderTable[] = { 927 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 928 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 929}; 930 931static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 932 uint64_t Address, const void *Decoder) { 933 DecodeStatus S = MCDisassembler::Success; 934 935 if (RegNo > 13) 936 return MCDisassembler::Fail; 937 938 if ((RegNo & 1) || RegNo == 0xe) 939 S = MCDisassembler::SoftFail; 940 941 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 942 Inst.addOperand(MCOperand::createReg(RegisterPair)); 943 return S; 944} 945 946static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 947 uint64_t Address, const void *Decoder) { 948 unsigned Register = 0; 949 switch (RegNo) { 950 case 0: 951 Register = ARM::R0; 952 break; 953 case 1: 954 Register = ARM::R1; 955 break; 956 case 2: 957 Register = ARM::R2; 958 break; 959 case 3: 960 Register = ARM::R3; 961 break; 962 case 9: 963 Register = ARM::R9; 964 break; 965 case 12: 966 Register = ARM::R12; 967 break; 968 default: 969 return MCDisassembler::Fail; 970 } 971 972 Inst.addOperand(MCOperand::createReg(Register)); 973 return MCDisassembler::Success; 974} 975 976static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 977 uint64_t Address, const void *Decoder) { 978 DecodeStatus S = MCDisassembler::Success; 979 980 const FeatureBitset &featureBits = 981 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 982 983 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 984 S = MCDisassembler::SoftFail; 985 986 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 987 return S; 988} 989 990static const uint16_t SPRDecoderTable[] = { 991 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 992 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 993 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 994 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 995 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 996 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 997 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 998 ARM::S28, ARM::S29, ARM::S30, ARM::S31 999}; 1000 1001static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1002 uint64_t Address, const void *Decoder) { 1003 if (RegNo > 31) 1004 return MCDisassembler::Fail; 1005 1006 unsigned Register = SPRDecoderTable[RegNo]; 1007 Inst.addOperand(MCOperand::createReg(Register)); 1008 return MCDisassembler::Success; 1009} 1010 1011static const uint16_t DPRDecoderTable[] = { 1012 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1013 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1014 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1015 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1016 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1017 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1018 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1019 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1020}; 1021 1022static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1023 uint64_t Address, const void *Decoder) { 1024 const FeatureBitset &featureBits = 1025 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1026 1027 bool hasD16 = featureBits[ARM::FeatureD16]; 1028 1029 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1030 return MCDisassembler::Fail; 1031 1032 unsigned Register = DPRDecoderTable[RegNo]; 1033 Inst.addOperand(MCOperand::createReg(Register)); 1034 return MCDisassembler::Success; 1035} 1036 1037static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1038 uint64_t Address, const void *Decoder) { 1039 if (RegNo > 7) 1040 return MCDisassembler::Fail; 1041 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1042} 1043 1044static DecodeStatus 1045DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1046 uint64_t Address, const void *Decoder) { 1047 if (RegNo > 15) 1048 return MCDisassembler::Fail; 1049 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1050} 1051 1052static const uint16_t QPRDecoderTable[] = { 1053 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1054 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1055 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1056 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1057}; 1058 1059 1060static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1061 uint64_t Address, const void *Decoder) { 1062 if (RegNo > 31 || (RegNo & 1) != 0) 1063 return MCDisassembler::Fail; 1064 RegNo >>= 1; 1065 1066 unsigned Register = QPRDecoderTable[RegNo]; 1067 Inst.addOperand(MCOperand::createReg(Register)); 1068 return MCDisassembler::Success; 1069} 1070 1071static const uint16_t DPairDecoderTable[] = { 1072 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1073 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1074 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1075 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1076 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1077 ARM::Q15 1078}; 1079 1080static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1081 uint64_t Address, const void *Decoder) { 1082 if (RegNo > 30) 1083 return MCDisassembler::Fail; 1084 1085 unsigned Register = DPairDecoderTable[RegNo]; 1086 Inst.addOperand(MCOperand::createReg(Register)); 1087 return MCDisassembler::Success; 1088} 1089 1090static const uint16_t DPairSpacedDecoderTable[] = { 1091 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1092 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1093 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1094 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1095 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1096 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1097 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1098 ARM::D28_D30, ARM::D29_D31 1099}; 1100 1101static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1102 unsigned RegNo, 1103 uint64_t Address, 1104 const void *Decoder) { 1105 if (RegNo > 29) 1106 return MCDisassembler::Fail; 1107 1108 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1109 Inst.addOperand(MCOperand::createReg(Register)); 1110 return MCDisassembler::Success; 1111} 1112 1113static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1114 uint64_t Address, const void *Decoder) { 1115 if (Val == 0xF) return MCDisassembler::Fail; 1116 // AL predicate is not allowed on Thumb1 branches. 1117 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1118 return MCDisassembler::Fail; 1119 Inst.addOperand(MCOperand::createImm(Val)); 1120 if (Val == ARMCC::AL) { 1121 Inst.addOperand(MCOperand::createReg(0)); 1122 } else 1123 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1124 return MCDisassembler::Success; 1125} 1126 1127static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1128 uint64_t Address, const void *Decoder) { 1129 if (Val) 1130 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1131 else 1132 Inst.addOperand(MCOperand::createReg(0)); 1133 return MCDisassembler::Success; 1134} 1135 1136static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1137 uint64_t Address, const void *Decoder) { 1138 DecodeStatus S = MCDisassembler::Success; 1139 1140 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1141 unsigned type = fieldFromInstruction(Val, 5, 2); 1142 unsigned imm = fieldFromInstruction(Val, 7, 5); 1143 1144 // Register-immediate 1145 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1146 return MCDisassembler::Fail; 1147 1148 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1149 switch (type) { 1150 case 0: 1151 Shift = ARM_AM::lsl; 1152 break; 1153 case 1: 1154 Shift = ARM_AM::lsr; 1155 break; 1156 case 2: 1157 Shift = ARM_AM::asr; 1158 break; 1159 case 3: 1160 Shift = ARM_AM::ror; 1161 break; 1162 } 1163 1164 if (Shift == ARM_AM::ror && imm == 0) 1165 Shift = ARM_AM::rrx; 1166 1167 unsigned Op = Shift | (imm << 3); 1168 Inst.addOperand(MCOperand::createImm(Op)); 1169 1170 return S; 1171} 1172 1173static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1174 uint64_t Address, const void *Decoder) { 1175 DecodeStatus S = MCDisassembler::Success; 1176 1177 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1178 unsigned type = fieldFromInstruction(Val, 5, 2); 1179 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1180 1181 // Register-register 1182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1183 return MCDisassembler::Fail; 1184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1185 return MCDisassembler::Fail; 1186 1187 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1188 switch (type) { 1189 case 0: 1190 Shift = ARM_AM::lsl; 1191 break; 1192 case 1: 1193 Shift = ARM_AM::lsr; 1194 break; 1195 case 2: 1196 Shift = ARM_AM::asr; 1197 break; 1198 case 3: 1199 Shift = ARM_AM::ror; 1200 break; 1201 } 1202 1203 Inst.addOperand(MCOperand::createImm(Shift)); 1204 1205 return S; 1206} 1207 1208static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1209 uint64_t Address, const void *Decoder) { 1210 DecodeStatus S = MCDisassembler::Success; 1211 1212 bool NeedDisjointWriteback = false; 1213 unsigned WritebackReg = 0; 1214 switch (Inst.getOpcode()) { 1215 default: 1216 break; 1217 case ARM::LDMIA_UPD: 1218 case ARM::LDMDB_UPD: 1219 case ARM::LDMIB_UPD: 1220 case ARM::LDMDA_UPD: 1221 case ARM::t2LDMIA_UPD: 1222 case ARM::t2LDMDB_UPD: 1223 case ARM::t2STMIA_UPD: 1224 case ARM::t2STMDB_UPD: 1225 NeedDisjointWriteback = true; 1226 WritebackReg = Inst.getOperand(0).getReg(); 1227 break; 1228 } 1229 1230 // Empty register lists are not allowed. 1231 if (Val == 0) return MCDisassembler::Fail; 1232 for (unsigned i = 0; i < 16; ++i) { 1233 if (Val & (1 << i)) { 1234 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1235 return MCDisassembler::Fail; 1236 // Writeback not allowed if Rn is in the target list. 1237 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1238 Check(S, MCDisassembler::SoftFail); 1239 } 1240 } 1241 1242 return S; 1243} 1244 1245static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1246 uint64_t Address, const void *Decoder) { 1247 DecodeStatus S = MCDisassembler::Success; 1248 1249 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1250 unsigned regs = fieldFromInstruction(Val, 0, 8); 1251 1252 // In case of unpredictable encoding, tweak the operands. 1253 if (regs == 0 || (Vd + regs) > 32) { 1254 regs = Vd + regs > 32 ? 32 - Vd : regs; 1255 regs = std::max( 1u, regs); 1256 S = MCDisassembler::SoftFail; 1257 } 1258 1259 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1260 return MCDisassembler::Fail; 1261 for (unsigned i = 0; i < (regs - 1); ++i) { 1262 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1263 return MCDisassembler::Fail; 1264 } 1265 1266 return S; 1267} 1268 1269static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1270 uint64_t Address, const void *Decoder) { 1271 DecodeStatus S = MCDisassembler::Success; 1272 1273 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1274 unsigned regs = fieldFromInstruction(Val, 1, 7); 1275 1276 // In case of unpredictable encoding, tweak the operands. 1277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1278 regs = Vd + regs > 32 ? 32 - Vd : regs; 1279 regs = std::max( 1u, regs); 1280 regs = std::min(16u, regs); 1281 S = MCDisassembler::SoftFail; 1282 } 1283 1284 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1285 return MCDisassembler::Fail; 1286 for (unsigned i = 0; i < (regs - 1); ++i) { 1287 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1288 return MCDisassembler::Fail; 1289 } 1290 1291 return S; 1292} 1293 1294static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1295 uint64_t Address, const void *Decoder) { 1296 // This operand encodes a mask of contiguous zeros between a specified MSB 1297 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1298 // the mask of all bits LSB-and-lower, and then xor them to create 1299 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1300 // create the final mask. 1301 unsigned msb = fieldFromInstruction(Val, 5, 5); 1302 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1303 1304 DecodeStatus S = MCDisassembler::Success; 1305 if (lsb > msb) { 1306 Check(S, MCDisassembler::SoftFail); 1307 // The check above will cause the warning for the "potentially undefined 1308 // instruction encoding" but we can't build a bad MCOperand value here 1309 // with a lsb > msb or else printing the MCInst will cause a crash. 1310 lsb = msb; 1311 } 1312 1313 uint32_t msb_mask = 0xFFFFFFFF; 1314 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1315 uint32_t lsb_mask = (1U << lsb) - 1; 1316 1317 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1318 return S; 1319} 1320 1321static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1322 uint64_t Address, const void *Decoder) { 1323 DecodeStatus S = MCDisassembler::Success; 1324 1325 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1326 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1327 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1328 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1329 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1330 unsigned U = fieldFromInstruction(Insn, 23, 1); 1331 1332 switch (Inst.getOpcode()) { 1333 case ARM::LDC_OFFSET: 1334 case ARM::LDC_PRE: 1335 case ARM::LDC_POST: 1336 case ARM::LDC_OPTION: 1337 case ARM::LDCL_OFFSET: 1338 case ARM::LDCL_PRE: 1339 case ARM::LDCL_POST: 1340 case ARM::LDCL_OPTION: 1341 case ARM::STC_OFFSET: 1342 case ARM::STC_PRE: 1343 case ARM::STC_POST: 1344 case ARM::STC_OPTION: 1345 case ARM::STCL_OFFSET: 1346 case ARM::STCL_PRE: 1347 case ARM::STCL_POST: 1348 case ARM::STCL_OPTION: 1349 case ARM::t2LDC_OFFSET: 1350 case ARM::t2LDC_PRE: 1351 case ARM::t2LDC_POST: 1352 case ARM::t2LDC_OPTION: 1353 case ARM::t2LDCL_OFFSET: 1354 case ARM::t2LDCL_PRE: 1355 case ARM::t2LDCL_POST: 1356 case ARM::t2LDCL_OPTION: 1357 case ARM::t2STC_OFFSET: 1358 case ARM::t2STC_PRE: 1359 case ARM::t2STC_POST: 1360 case ARM::t2STC_OPTION: 1361 case ARM::t2STCL_OFFSET: 1362 case ARM::t2STCL_PRE: 1363 case ARM::t2STCL_POST: 1364 case ARM::t2STCL_OPTION: 1365 if (coproc == 0xA || coproc == 0xB) 1366 return MCDisassembler::Fail; 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 const FeatureBitset &featureBits = 1373 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1374 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1375 return MCDisassembler::Fail; 1376 1377 Inst.addOperand(MCOperand::createImm(coproc)); 1378 Inst.addOperand(MCOperand::createImm(CRd)); 1379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1380 return MCDisassembler::Fail; 1381 1382 switch (Inst.getOpcode()) { 1383 case ARM::t2LDC2_OFFSET: 1384 case ARM::t2LDC2L_OFFSET: 1385 case ARM::t2LDC2_PRE: 1386 case ARM::t2LDC2L_PRE: 1387 case ARM::t2STC2_OFFSET: 1388 case ARM::t2STC2L_OFFSET: 1389 case ARM::t2STC2_PRE: 1390 case ARM::t2STC2L_PRE: 1391 case ARM::LDC2_OFFSET: 1392 case ARM::LDC2L_OFFSET: 1393 case ARM::LDC2_PRE: 1394 case ARM::LDC2L_PRE: 1395 case ARM::STC2_OFFSET: 1396 case ARM::STC2L_OFFSET: 1397 case ARM::STC2_PRE: 1398 case ARM::STC2L_PRE: 1399 case ARM::t2LDC_OFFSET: 1400 case ARM::t2LDCL_OFFSET: 1401 case ARM::t2LDC_PRE: 1402 case ARM::t2LDCL_PRE: 1403 case ARM::t2STC_OFFSET: 1404 case ARM::t2STCL_OFFSET: 1405 case ARM::t2STC_PRE: 1406 case ARM::t2STCL_PRE: 1407 case ARM::LDC_OFFSET: 1408 case ARM::LDCL_OFFSET: 1409 case ARM::LDC_PRE: 1410 case ARM::LDCL_PRE: 1411 case ARM::STC_OFFSET: 1412 case ARM::STCL_OFFSET: 1413 case ARM::STC_PRE: 1414 case ARM::STCL_PRE: 1415 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1416 Inst.addOperand(MCOperand::createImm(imm)); 1417 break; 1418 case ARM::t2LDC2_POST: 1419 case ARM::t2LDC2L_POST: 1420 case ARM::t2STC2_POST: 1421 case ARM::t2STC2L_POST: 1422 case ARM::LDC2_POST: 1423 case ARM::LDC2L_POST: 1424 case ARM::STC2_POST: 1425 case ARM::STC2L_POST: 1426 case ARM::t2LDC_POST: 1427 case ARM::t2LDCL_POST: 1428 case ARM::t2STC_POST: 1429 case ARM::t2STCL_POST: 1430 case ARM::LDC_POST: 1431 case ARM::LDCL_POST: 1432 case ARM::STC_POST: 1433 case ARM::STCL_POST: 1434 imm |= U << 8; 1435 LLVM_FALLTHROUGH; 1436 default: 1437 // The 'option' variant doesn't encode 'U' in the immediate since 1438 // the immediate is unsigned [0,255]. 1439 Inst.addOperand(MCOperand::createImm(imm)); 1440 break; 1441 } 1442 1443 switch (Inst.getOpcode()) { 1444 case ARM::LDC_OFFSET: 1445 case ARM::LDC_PRE: 1446 case ARM::LDC_POST: 1447 case ARM::LDC_OPTION: 1448 case ARM::LDCL_OFFSET: 1449 case ARM::LDCL_PRE: 1450 case ARM::LDCL_POST: 1451 case ARM::LDCL_OPTION: 1452 case ARM::STC_OFFSET: 1453 case ARM::STC_PRE: 1454 case ARM::STC_POST: 1455 case ARM::STC_OPTION: 1456 case ARM::STCL_OFFSET: 1457 case ARM::STCL_PRE: 1458 case ARM::STCL_POST: 1459 case ARM::STCL_OPTION: 1460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1461 return MCDisassembler::Fail; 1462 break; 1463 default: 1464 break; 1465 } 1466 1467 return S; 1468} 1469 1470static DecodeStatus 1471DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1472 uint64_t Address, const void *Decoder) { 1473 DecodeStatus S = MCDisassembler::Success; 1474 1475 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1476 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1477 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1478 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1479 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1480 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1481 unsigned P = fieldFromInstruction(Insn, 24, 1); 1482 unsigned W = fieldFromInstruction(Insn, 21, 1); 1483 1484 // On stores, the writeback operand precedes Rt. 1485 switch (Inst.getOpcode()) { 1486 case ARM::STR_POST_IMM: 1487 case ARM::STR_POST_REG: 1488 case ARM::STRB_POST_IMM: 1489 case ARM::STRB_POST_REG: 1490 case ARM::STRT_POST_REG: 1491 case ARM::STRT_POST_IMM: 1492 case ARM::STRBT_POST_REG: 1493 case ARM::STRBT_POST_IMM: 1494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1495 return MCDisassembler::Fail; 1496 break; 1497 default: 1498 break; 1499 } 1500 1501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1502 return MCDisassembler::Fail; 1503 1504 // On loads, the writeback operand comes after Rt. 1505 switch (Inst.getOpcode()) { 1506 case ARM::LDR_POST_IMM: 1507 case ARM::LDR_POST_REG: 1508 case ARM::LDRB_POST_IMM: 1509 case ARM::LDRB_POST_REG: 1510 case ARM::LDRBT_POST_REG: 1511 case ARM::LDRBT_POST_IMM: 1512 case ARM::LDRT_POST_REG: 1513 case ARM::LDRT_POST_IMM: 1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1515 return MCDisassembler::Fail; 1516 break; 1517 default: 1518 break; 1519 } 1520 1521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1522 return MCDisassembler::Fail; 1523 1524 ARM_AM::AddrOpc Op = ARM_AM::add; 1525 if (!fieldFromInstruction(Insn, 23, 1)) 1526 Op = ARM_AM::sub; 1527 1528 bool writeback = (P == 0) || (W == 1); 1529 unsigned idx_mode = 0; 1530 if (P && writeback) 1531 idx_mode = ARMII::IndexModePre; 1532 else if (!P && writeback) 1533 idx_mode = ARMII::IndexModePost; 1534 1535 if (writeback && (Rn == 15 || Rn == Rt)) 1536 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1537 1538 if (reg) { 1539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1540 return MCDisassembler::Fail; 1541 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1542 switch( fieldFromInstruction(Insn, 5, 2)) { 1543 case 0: 1544 Opc = ARM_AM::lsl; 1545 break; 1546 case 1: 1547 Opc = ARM_AM::lsr; 1548 break; 1549 case 2: 1550 Opc = ARM_AM::asr; 1551 break; 1552 case 3: 1553 Opc = ARM_AM::ror; 1554 break; 1555 default: 1556 return MCDisassembler::Fail; 1557 } 1558 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1559 if (Opc == ARM_AM::ror && amt == 0) 1560 Opc = ARM_AM::rrx; 1561 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1562 1563 Inst.addOperand(MCOperand::createImm(imm)); 1564 } else { 1565 Inst.addOperand(MCOperand::createReg(0)); 1566 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1567 Inst.addOperand(MCOperand::createImm(tmp)); 1568 } 1569 1570 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1571 return MCDisassembler::Fail; 1572 1573 return S; 1574} 1575 1576static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1577 uint64_t Address, const void *Decoder) { 1578 DecodeStatus S = MCDisassembler::Success; 1579 1580 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1581 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1582 unsigned type = fieldFromInstruction(Val, 5, 2); 1583 unsigned imm = fieldFromInstruction(Val, 7, 5); 1584 unsigned U = fieldFromInstruction(Val, 12, 1); 1585 1586 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1587 switch (type) { 1588 case 0: 1589 ShOp = ARM_AM::lsl; 1590 break; 1591 case 1: 1592 ShOp = ARM_AM::lsr; 1593 break; 1594 case 2: 1595 ShOp = ARM_AM::asr; 1596 break; 1597 case 3: 1598 ShOp = ARM_AM::ror; 1599 break; 1600 } 1601 1602 if (ShOp == ARM_AM::ror && imm == 0) 1603 ShOp = ARM_AM::rrx; 1604 1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1606 return MCDisassembler::Fail; 1607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1608 return MCDisassembler::Fail; 1609 unsigned shift; 1610 if (U) 1611 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1612 else 1613 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1614 Inst.addOperand(MCOperand::createImm(shift)); 1615 1616 return S; 1617} 1618 1619static DecodeStatus 1620DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1621 uint64_t Address, const void *Decoder) { 1622 DecodeStatus S = MCDisassembler::Success; 1623 1624 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1625 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1626 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1627 unsigned type = fieldFromInstruction(Insn, 22, 1); 1628 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1629 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1630 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1631 unsigned W = fieldFromInstruction(Insn, 21, 1); 1632 unsigned P = fieldFromInstruction(Insn, 24, 1); 1633 unsigned Rt2 = Rt + 1; 1634 1635 bool writeback = (W == 1) | (P == 0); 1636 1637 // For {LD,ST}RD, Rt must be even, else undefined. 1638 switch (Inst.getOpcode()) { 1639 case ARM::STRD: 1640 case ARM::STRD_PRE: 1641 case ARM::STRD_POST: 1642 case ARM::LDRD: 1643 case ARM::LDRD_PRE: 1644 case ARM::LDRD_POST: 1645 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1646 break; 1647 default: 1648 break; 1649 } 1650 switch (Inst.getOpcode()) { 1651 case ARM::STRD: 1652 case ARM::STRD_PRE: 1653 case ARM::STRD_POST: 1654 if (P == 0 && W == 1) 1655 S = MCDisassembler::SoftFail; 1656 1657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1658 S = MCDisassembler::SoftFail; 1659 if (type && Rm == 15) 1660 S = MCDisassembler::SoftFail; 1661 if (Rt2 == 15) 1662 S = MCDisassembler::SoftFail; 1663 if (!type && fieldFromInstruction(Insn, 8, 4)) 1664 S = MCDisassembler::SoftFail; 1665 break; 1666 case ARM::STRH: 1667 case ARM::STRH_PRE: 1668 case ARM::STRH_POST: 1669 if (Rt == 15) 1670 S = MCDisassembler::SoftFail; 1671 if (writeback && (Rn == 15 || Rn == Rt)) 1672 S = MCDisassembler::SoftFail; 1673 if (!type && Rm == 15) 1674 S = MCDisassembler::SoftFail; 1675 break; 1676 case ARM::LDRD: 1677 case ARM::LDRD_PRE: 1678 case ARM::LDRD_POST: 1679 if (type && Rn == 15){ 1680 if (Rt2 == 15) 1681 S = MCDisassembler::SoftFail; 1682 break; 1683 } 1684 if (P == 0 && W == 1) 1685 S = MCDisassembler::SoftFail; 1686 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1687 S = MCDisassembler::SoftFail; 1688 if (!type && writeback && Rn == 15) 1689 S = MCDisassembler::SoftFail; 1690 if (writeback && (Rn == Rt || Rn == Rt2)) 1691 S = MCDisassembler::SoftFail; 1692 break; 1693 case ARM::LDRH: 1694 case ARM::LDRH_PRE: 1695 case ARM::LDRH_POST: 1696 if (type && Rn == 15){ 1697 if (Rt == 15) 1698 S = MCDisassembler::SoftFail; 1699 break; 1700 } 1701 if (Rt == 15) 1702 S = MCDisassembler::SoftFail; 1703 if (!type && Rm == 15) 1704 S = MCDisassembler::SoftFail; 1705 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1706 S = MCDisassembler::SoftFail; 1707 break; 1708 case ARM::LDRSH: 1709 case ARM::LDRSH_PRE: 1710 case ARM::LDRSH_POST: 1711 case ARM::LDRSB: 1712 case ARM::LDRSB_PRE: 1713 case ARM::LDRSB_POST: 1714 if (type && Rn == 15){ 1715 if (Rt == 15) 1716 S = MCDisassembler::SoftFail; 1717 break; 1718 } 1719 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1720 S = MCDisassembler::SoftFail; 1721 if (!type && (Rt == 15 || Rm == 15)) 1722 S = MCDisassembler::SoftFail; 1723 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1724 S = MCDisassembler::SoftFail; 1725 break; 1726 default: 1727 break; 1728 } 1729 1730 if (writeback) { // Writeback 1731 if (P) 1732 U |= ARMII::IndexModePre << 9; 1733 else 1734 U |= ARMII::IndexModePost << 9; 1735 1736 // On stores, the writeback operand precedes Rt. 1737 switch (Inst.getOpcode()) { 1738 case ARM::STRD: 1739 case ARM::STRD_PRE: 1740 case ARM::STRD_POST: 1741 case ARM::STRH: 1742 case ARM::STRH_PRE: 1743 case ARM::STRH_POST: 1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1745 return MCDisassembler::Fail; 1746 break; 1747 default: 1748 break; 1749 } 1750 } 1751 1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1753 return MCDisassembler::Fail; 1754 switch (Inst.getOpcode()) { 1755 case ARM::STRD: 1756 case ARM::STRD_PRE: 1757 case ARM::STRD_POST: 1758 case ARM::LDRD: 1759 case ARM::LDRD_PRE: 1760 case ARM::LDRD_POST: 1761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1762 return MCDisassembler::Fail; 1763 break; 1764 default: 1765 break; 1766 } 1767 1768 if (writeback) { 1769 // On loads, the writeback operand comes after Rt. 1770 switch (Inst.getOpcode()) { 1771 case ARM::LDRD: 1772 case ARM::LDRD_PRE: 1773 case ARM::LDRD_POST: 1774 case ARM::LDRH: 1775 case ARM::LDRH_PRE: 1776 case ARM::LDRH_POST: 1777 case ARM::LDRSH: 1778 case ARM::LDRSH_PRE: 1779 case ARM::LDRSH_POST: 1780 case ARM::LDRSB: 1781 case ARM::LDRSB_PRE: 1782 case ARM::LDRSB_POST: 1783 case ARM::LDRHTr: 1784 case ARM::LDRSBTr: 1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1786 return MCDisassembler::Fail; 1787 break; 1788 default: 1789 break; 1790 } 1791 } 1792 1793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 1796 if (type) { 1797 Inst.addOperand(MCOperand::createReg(0)); 1798 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1799 } else { 1800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1801 return MCDisassembler::Fail; 1802 Inst.addOperand(MCOperand::createImm(U)); 1803 } 1804 1805 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1806 return MCDisassembler::Fail; 1807 1808 return S; 1809} 1810 1811static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1812 uint64_t Address, const void *Decoder) { 1813 DecodeStatus S = MCDisassembler::Success; 1814 1815 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1816 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1817 1818 switch (mode) { 1819 case 0: 1820 mode = ARM_AM::da; 1821 break; 1822 case 1: 1823 mode = ARM_AM::ia; 1824 break; 1825 case 2: 1826 mode = ARM_AM::db; 1827 break; 1828 case 3: 1829 mode = ARM_AM::ib; 1830 break; 1831 } 1832 1833 Inst.addOperand(MCOperand::createImm(mode)); 1834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1835 return MCDisassembler::Fail; 1836 1837 return S; 1838} 1839 1840static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1841 uint64_t Address, const void *Decoder) { 1842 DecodeStatus S = MCDisassembler::Success; 1843 1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1845 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1846 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1847 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1848 1849 if (pred == 0xF) 1850 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1851 1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1853 return MCDisassembler::Fail; 1854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1855 return MCDisassembler::Fail; 1856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1857 return MCDisassembler::Fail; 1858 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1859 return MCDisassembler::Fail; 1860 return S; 1861} 1862 1863static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1864 unsigned Insn, 1865 uint64_t Address, const void *Decoder) { 1866 DecodeStatus S = MCDisassembler::Success; 1867 1868 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1869 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1870 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1871 1872 if (pred == 0xF) { 1873 // Ambiguous with RFE and SRS 1874 switch (Inst.getOpcode()) { 1875 case ARM::LDMDA: 1876 Inst.setOpcode(ARM::RFEDA); 1877 break; 1878 case ARM::LDMDA_UPD: 1879 Inst.setOpcode(ARM::RFEDA_UPD); 1880 break; 1881 case ARM::LDMDB: 1882 Inst.setOpcode(ARM::RFEDB); 1883 break; 1884 case ARM::LDMDB_UPD: 1885 Inst.setOpcode(ARM::RFEDB_UPD); 1886 break; 1887 case ARM::LDMIA: 1888 Inst.setOpcode(ARM::RFEIA); 1889 break; 1890 case ARM::LDMIA_UPD: 1891 Inst.setOpcode(ARM::RFEIA_UPD); 1892 break; 1893 case ARM::LDMIB: 1894 Inst.setOpcode(ARM::RFEIB); 1895 break; 1896 case ARM::LDMIB_UPD: 1897 Inst.setOpcode(ARM::RFEIB_UPD); 1898 break; 1899 case ARM::STMDA: 1900 Inst.setOpcode(ARM::SRSDA); 1901 break; 1902 case ARM::STMDA_UPD: 1903 Inst.setOpcode(ARM::SRSDA_UPD); 1904 break; 1905 case ARM::STMDB: 1906 Inst.setOpcode(ARM::SRSDB); 1907 break; 1908 case ARM::STMDB_UPD: 1909 Inst.setOpcode(ARM::SRSDB_UPD); 1910 break; 1911 case ARM::STMIA: 1912 Inst.setOpcode(ARM::SRSIA); 1913 break; 1914 case ARM::STMIA_UPD: 1915 Inst.setOpcode(ARM::SRSIA_UPD); 1916 break; 1917 case ARM::STMIB: 1918 Inst.setOpcode(ARM::SRSIB); 1919 break; 1920 case ARM::STMIB_UPD: 1921 Inst.setOpcode(ARM::SRSIB_UPD); 1922 break; 1923 default: 1924 return MCDisassembler::Fail; 1925 } 1926 1927 // For stores (which become SRS's, the only operand is the mode. 1928 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1929 // Check SRS encoding constraints 1930 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1931 fieldFromInstruction(Insn, 20, 1) == 0)) 1932 return MCDisassembler::Fail; 1933 1934 Inst.addOperand( 1935 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1936 return S; 1937 } 1938 1939 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1940 } 1941 1942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1943 return MCDisassembler::Fail; 1944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1945 return MCDisassembler::Fail; // Tied 1946 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1947 return MCDisassembler::Fail; 1948 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 1951 return S; 1952} 1953 1954// Check for UNPREDICTABLE predicated ESB instruction 1955static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 1956 uint64_t Address, const void *Decoder) { 1957 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1958 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 1959 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 1960 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 1961 1962 DecodeStatus S = MCDisassembler::Success; 1963 1964 Inst.addOperand(MCOperand::createImm(imm8)); 1965 1966 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1967 return MCDisassembler::Fail; 1968 1969 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 1970 // so all predicates should be allowed. 1971 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 1972 S = MCDisassembler::SoftFail; 1973 1974 return S; 1975} 1976 1977static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1978 uint64_t Address, const void *Decoder) { 1979 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1980 unsigned M = fieldFromInstruction(Insn, 17, 1); 1981 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1982 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1983 1984 DecodeStatus S = MCDisassembler::Success; 1985 1986 // This decoder is called from multiple location that do not check 1987 // the full encoding is valid before they do. 1988 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1989 fieldFromInstruction(Insn, 16, 1) != 0 || 1990 fieldFromInstruction(Insn, 20, 8) != 0x10) 1991 return MCDisassembler::Fail; 1992 1993 // imod == '01' --> UNPREDICTABLE 1994 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1995 // return failure here. The '01' imod value is unprintable, so there's 1996 // nothing useful we could do even if we returned UNPREDICTABLE. 1997 1998 if (imod == 1) return MCDisassembler::Fail; 1999 2000 if (imod && M) { 2001 Inst.setOpcode(ARM::CPS3p); 2002 Inst.addOperand(MCOperand::createImm(imod)); 2003 Inst.addOperand(MCOperand::createImm(iflags)); 2004 Inst.addOperand(MCOperand::createImm(mode)); 2005 } else if (imod && !M) { 2006 Inst.setOpcode(ARM::CPS2p); 2007 Inst.addOperand(MCOperand::createImm(imod)); 2008 Inst.addOperand(MCOperand::createImm(iflags)); 2009 if (mode) S = MCDisassembler::SoftFail; 2010 } else if (!imod && M) { 2011 Inst.setOpcode(ARM::CPS1p); 2012 Inst.addOperand(MCOperand::createImm(mode)); 2013 if (iflags) S = MCDisassembler::SoftFail; 2014 } else { 2015 // imod == '00' && M == '0' --> UNPREDICTABLE 2016 Inst.setOpcode(ARM::CPS1p); 2017 Inst.addOperand(MCOperand::createImm(mode)); 2018 S = MCDisassembler::SoftFail; 2019 } 2020 2021 return S; 2022} 2023 2024static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2025 uint64_t Address, const void *Decoder) { 2026 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2027 unsigned M = fieldFromInstruction(Insn, 8, 1); 2028 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2029 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2030 2031 DecodeStatus S = MCDisassembler::Success; 2032 2033 // imod == '01' --> UNPREDICTABLE 2034 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2035 // return failure here. The '01' imod value is unprintable, so there's 2036 // nothing useful we could do even if we returned UNPREDICTABLE. 2037 2038 if (imod == 1) return MCDisassembler::Fail; 2039 2040 if (imod && M) { 2041 Inst.setOpcode(ARM::t2CPS3p); 2042 Inst.addOperand(MCOperand::createImm(imod)); 2043 Inst.addOperand(MCOperand::createImm(iflags)); 2044 Inst.addOperand(MCOperand::createImm(mode)); 2045 } else if (imod && !M) { 2046 Inst.setOpcode(ARM::t2CPS2p); 2047 Inst.addOperand(MCOperand::createImm(imod)); 2048 Inst.addOperand(MCOperand::createImm(iflags)); 2049 if (mode) S = MCDisassembler::SoftFail; 2050 } else if (!imod && M) { 2051 Inst.setOpcode(ARM::t2CPS1p); 2052 Inst.addOperand(MCOperand::createImm(mode)); 2053 if (iflags) S = MCDisassembler::SoftFail; 2054 } else { 2055 // imod == '00' && M == '0' --> this is a HINT instruction 2056 int imm = fieldFromInstruction(Insn, 0, 8); 2057 // HINT are defined only for immediate in [0..4] 2058 if(imm > 4) return MCDisassembler::Fail; 2059 Inst.setOpcode(ARM::t2HINT); 2060 Inst.addOperand(MCOperand::createImm(imm)); 2061 } 2062 2063 return S; 2064} 2065 2066static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2067 uint64_t Address, const void *Decoder) { 2068 DecodeStatus S = MCDisassembler::Success; 2069 2070 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2071 unsigned imm = 0; 2072 2073 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2074 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2075 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2076 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2077 2078 if (Inst.getOpcode() == ARM::t2MOVTi16) 2079 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2080 return MCDisassembler::Fail; 2081 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2082 return MCDisassembler::Fail; 2083 2084 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2085 Inst.addOperand(MCOperand::createImm(imm)); 2086 2087 return S; 2088} 2089 2090static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2091 uint64_t Address, const void *Decoder) { 2092 DecodeStatus S = MCDisassembler::Success; 2093 2094 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2095 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2096 unsigned imm = 0; 2097 2098 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2099 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2100 2101 if (Inst.getOpcode() == ARM::MOVTi16) 2102 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2103 return MCDisassembler::Fail; 2104 2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2106 return MCDisassembler::Fail; 2107 2108 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2109 Inst.addOperand(MCOperand::createImm(imm)); 2110 2111 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 2114 return S; 2115} 2116 2117static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2118 uint64_t Address, const void *Decoder) { 2119 DecodeStatus S = MCDisassembler::Success; 2120 2121 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2122 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2123 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2124 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2125 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2126 2127 if (pred == 0xF) 2128 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2129 2130 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2131 return MCDisassembler::Fail; 2132 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2133 return MCDisassembler::Fail; 2134 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2135 return MCDisassembler::Fail; 2136 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2137 return MCDisassembler::Fail; 2138 2139 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2140 return MCDisassembler::Fail; 2141 2142 return S; 2143} 2144 2145static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2146 uint64_t Address, const void *Decoder) { 2147 DecodeStatus S = MCDisassembler::Success; 2148 2149 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2150 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2151 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2152 2153 if (Pred == 0xF) 2154 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2155 2156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2157 return MCDisassembler::Fail; 2158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2159 return MCDisassembler::Fail; 2160 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2161 return MCDisassembler::Fail; 2162 2163 return S; 2164} 2165 2166static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2167 uint64_t Address, const void *Decoder) { 2168 DecodeStatus S = MCDisassembler::Success; 2169 2170 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2171 2172 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2173 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2174 2175 if (!FeatureBits[ARM::HasV8_1aOps] || 2176 !FeatureBits[ARM::HasV8Ops]) 2177 return MCDisassembler::Fail; 2178 2179 // Decoder can be called from DecodeTST, which does not check the full 2180 // encoding is valid. 2181 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2182 fieldFromInstruction(Insn, 4,4) != 0) 2183 return MCDisassembler::Fail; 2184 if (fieldFromInstruction(Insn, 10,10) != 0 || 2185 fieldFromInstruction(Insn, 0,4) != 0) 2186 S = MCDisassembler::SoftFail; 2187 2188 Inst.setOpcode(ARM::SETPAN); 2189 Inst.addOperand(MCOperand::createImm(Imm)); 2190 2191 return S; 2192} 2193 2194static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2195 uint64_t Address, const void *Decoder) { 2196 DecodeStatus S = MCDisassembler::Success; 2197 2198 unsigned add = fieldFromInstruction(Val, 12, 1); 2199 unsigned imm = fieldFromInstruction(Val, 0, 12); 2200 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2201 2202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2203 return MCDisassembler::Fail; 2204 2205 if (!add) imm *= -1; 2206 if (imm == 0 && !add) imm = INT32_MIN; 2207 Inst.addOperand(MCOperand::createImm(imm)); 2208 if (Rn == 15) 2209 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2210 2211 return S; 2212} 2213 2214static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2215 uint64_t Address, const void *Decoder) { 2216 DecodeStatus S = MCDisassembler::Success; 2217 2218 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2219 // U == 1 to add imm, 0 to subtract it. 2220 unsigned U = fieldFromInstruction(Val, 8, 1); 2221 unsigned imm = fieldFromInstruction(Val, 0, 8); 2222 2223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2224 return MCDisassembler::Fail; 2225 2226 if (U) 2227 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2228 else 2229 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2230 2231 return S; 2232} 2233 2234static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2235 uint64_t Address, const void *Decoder) { 2236 DecodeStatus S = MCDisassembler::Success; 2237 2238 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2239 // U == 1 to add imm, 0 to subtract it. 2240 unsigned U = fieldFromInstruction(Val, 8, 1); 2241 unsigned imm = fieldFromInstruction(Val, 0, 8); 2242 2243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2244 return MCDisassembler::Fail; 2245 2246 if (U) 2247 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2248 else 2249 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2250 2251 return S; 2252} 2253 2254static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2255 uint64_t Address, const void *Decoder) { 2256 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2257} 2258 2259static DecodeStatus 2260DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2261 uint64_t Address, const void *Decoder) { 2262 DecodeStatus Status = MCDisassembler::Success; 2263 2264 // Note the J1 and J2 values are from the encoded instruction. So here 2265 // change them to I1 and I2 values via as documented: 2266 // I1 = NOT(J1 EOR S); 2267 // I2 = NOT(J2 EOR S); 2268 // and build the imm32 with one trailing zero as documented: 2269 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2270 unsigned S = fieldFromInstruction(Insn, 26, 1); 2271 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2272 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2273 unsigned I1 = !(J1 ^ S); 2274 unsigned I2 = !(J2 ^ S); 2275 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2276 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2277 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2278 int imm32 = SignExtend32<25>(tmp << 1); 2279 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2280 true, 4, Inst, Decoder)) 2281 Inst.addOperand(MCOperand::createImm(imm32)); 2282 2283 return Status; 2284} 2285 2286static DecodeStatus 2287DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2288 uint64_t Address, const void *Decoder) { 2289 DecodeStatus S = MCDisassembler::Success; 2290 2291 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2292 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2293 2294 if (pred == 0xF) { 2295 Inst.setOpcode(ARM::BLXi); 2296 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2297 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2298 true, 4, Inst, Decoder)) 2299 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2300 return S; 2301 } 2302 2303 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2304 true, 4, Inst, Decoder)) 2305 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2306 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2307 return MCDisassembler::Fail; 2308 2309 return S; 2310} 2311 2312 2313static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2314 uint64_t Address, const void *Decoder) { 2315 DecodeStatus S = MCDisassembler::Success; 2316 2317 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2318 unsigned align = fieldFromInstruction(Val, 4, 2); 2319 2320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2321 return MCDisassembler::Fail; 2322 if (!align) 2323 Inst.addOperand(MCOperand::createImm(0)); 2324 else 2325 Inst.addOperand(MCOperand::createImm(4 << align)); 2326 2327 return S; 2328} 2329 2330static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2331 uint64_t Address, const void *Decoder) { 2332 DecodeStatus S = MCDisassembler::Success; 2333 2334 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2335 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2336 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2337 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2338 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2339 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2340 2341 // First output register 2342 switch (Inst.getOpcode()) { 2343 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2344 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2345 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2346 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2347 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2348 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2349 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2350 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2351 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2352 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2353 return MCDisassembler::Fail; 2354 break; 2355 case ARM::VLD2b16: 2356 case ARM::VLD2b32: 2357 case ARM::VLD2b8: 2358 case ARM::VLD2b16wb_fixed: 2359 case ARM::VLD2b16wb_register: 2360 case ARM::VLD2b32wb_fixed: 2361 case ARM::VLD2b32wb_register: 2362 case ARM::VLD2b8wb_fixed: 2363 case ARM::VLD2b8wb_register: 2364 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2365 return MCDisassembler::Fail; 2366 break; 2367 default: 2368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2369 return MCDisassembler::Fail; 2370 } 2371 2372 // Second output register 2373 switch (Inst.getOpcode()) { 2374 case ARM::VLD3d8: 2375 case ARM::VLD3d16: 2376 case ARM::VLD3d32: 2377 case ARM::VLD3d8_UPD: 2378 case ARM::VLD3d16_UPD: 2379 case ARM::VLD3d32_UPD: 2380 case ARM::VLD4d8: 2381 case ARM::VLD4d16: 2382 case ARM::VLD4d32: 2383 case ARM::VLD4d8_UPD: 2384 case ARM::VLD4d16_UPD: 2385 case ARM::VLD4d32_UPD: 2386 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2387 return MCDisassembler::Fail; 2388 break; 2389 case ARM::VLD3q8: 2390 case ARM::VLD3q16: 2391 case ARM::VLD3q32: 2392 case ARM::VLD3q8_UPD: 2393 case ARM::VLD3q16_UPD: 2394 case ARM::VLD3q32_UPD: 2395 case ARM::VLD4q8: 2396 case ARM::VLD4q16: 2397 case ARM::VLD4q32: 2398 case ARM::VLD4q8_UPD: 2399 case ARM::VLD4q16_UPD: 2400 case ARM::VLD4q32_UPD: 2401 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2402 return MCDisassembler::Fail; 2403 default: 2404 break; 2405 } 2406 2407 // Third output register 2408 switch(Inst.getOpcode()) { 2409 case ARM::VLD3d8: 2410 case ARM::VLD3d16: 2411 case ARM::VLD3d32: 2412 case ARM::VLD3d8_UPD: 2413 case ARM::VLD3d16_UPD: 2414 case ARM::VLD3d32_UPD: 2415 case ARM::VLD4d8: 2416 case ARM::VLD4d16: 2417 case ARM::VLD4d32: 2418 case ARM::VLD4d8_UPD: 2419 case ARM::VLD4d16_UPD: 2420 case ARM::VLD4d32_UPD: 2421 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2422 return MCDisassembler::Fail; 2423 break; 2424 case ARM::VLD3q8: 2425 case ARM::VLD3q16: 2426 case ARM::VLD3q32: 2427 case ARM::VLD3q8_UPD: 2428 case ARM::VLD3q16_UPD: 2429 case ARM::VLD3q32_UPD: 2430 case ARM::VLD4q8: 2431 case ARM::VLD4q16: 2432 case ARM::VLD4q32: 2433 case ARM::VLD4q8_UPD: 2434 case ARM::VLD4q16_UPD: 2435 case ARM::VLD4q32_UPD: 2436 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2437 return MCDisassembler::Fail; 2438 break; 2439 default: 2440 break; 2441 } 2442 2443 // Fourth output register 2444 switch (Inst.getOpcode()) { 2445 case ARM::VLD4d8: 2446 case ARM::VLD4d16: 2447 case ARM::VLD4d32: 2448 case ARM::VLD4d8_UPD: 2449 case ARM::VLD4d16_UPD: 2450 case ARM::VLD4d32_UPD: 2451 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2452 return MCDisassembler::Fail; 2453 break; 2454 case ARM::VLD4q8: 2455 case ARM::VLD4q16: 2456 case ARM::VLD4q32: 2457 case ARM::VLD4q8_UPD: 2458 case ARM::VLD4q16_UPD: 2459 case ARM::VLD4q32_UPD: 2460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2461 return MCDisassembler::Fail; 2462 break; 2463 default: 2464 break; 2465 } 2466 2467 // Writeback operand 2468 switch (Inst.getOpcode()) { 2469 case ARM::VLD1d8wb_fixed: 2470 case ARM::VLD1d16wb_fixed: 2471 case ARM::VLD1d32wb_fixed: 2472 case ARM::VLD1d64wb_fixed: 2473 case ARM::VLD1d8wb_register: 2474 case ARM::VLD1d16wb_register: 2475 case ARM::VLD1d32wb_register: 2476 case ARM::VLD1d64wb_register: 2477 case ARM::VLD1q8wb_fixed: 2478 case ARM::VLD1q16wb_fixed: 2479 case ARM::VLD1q32wb_fixed: 2480 case ARM::VLD1q64wb_fixed: 2481 case ARM::VLD1q8wb_register: 2482 case ARM::VLD1q16wb_register: 2483 case ARM::VLD1q32wb_register: 2484 case ARM::VLD1q64wb_register: 2485 case ARM::VLD1d8Twb_fixed: 2486 case ARM::VLD1d8Twb_register: 2487 case ARM::VLD1d16Twb_fixed: 2488 case ARM::VLD1d16Twb_register: 2489 case ARM::VLD1d32Twb_fixed: 2490 case ARM::VLD1d32Twb_register: 2491 case ARM::VLD1d64Twb_fixed: 2492 case ARM::VLD1d64Twb_register: 2493 case ARM::VLD1d8Qwb_fixed: 2494 case ARM::VLD1d8Qwb_register: 2495 case ARM::VLD1d16Qwb_fixed: 2496 case ARM::VLD1d16Qwb_register: 2497 case ARM::VLD1d32Qwb_fixed: 2498 case ARM::VLD1d32Qwb_register: 2499 case ARM::VLD1d64Qwb_fixed: 2500 case ARM::VLD1d64Qwb_register: 2501 case ARM::VLD2d8wb_fixed: 2502 case ARM::VLD2d16wb_fixed: 2503 case ARM::VLD2d32wb_fixed: 2504 case ARM::VLD2q8wb_fixed: 2505 case ARM::VLD2q16wb_fixed: 2506 case ARM::VLD2q32wb_fixed: 2507 case ARM::VLD2d8wb_register: 2508 case ARM::VLD2d16wb_register: 2509 case ARM::VLD2d32wb_register: 2510 case ARM::VLD2q8wb_register: 2511 case ARM::VLD2q16wb_register: 2512 case ARM::VLD2q32wb_register: 2513 case ARM::VLD2b8wb_fixed: 2514 case ARM::VLD2b16wb_fixed: 2515 case ARM::VLD2b32wb_fixed: 2516 case ARM::VLD2b8wb_register: 2517 case ARM::VLD2b16wb_register: 2518 case ARM::VLD2b32wb_register: 2519 Inst.addOperand(MCOperand::createImm(0)); 2520 break; 2521 case ARM::VLD3d8_UPD: 2522 case ARM::VLD3d16_UPD: 2523 case ARM::VLD3d32_UPD: 2524 case ARM::VLD3q8_UPD: 2525 case ARM::VLD3q16_UPD: 2526 case ARM::VLD3q32_UPD: 2527 case ARM::VLD4d8_UPD: 2528 case ARM::VLD4d16_UPD: 2529 case ARM::VLD4d32_UPD: 2530 case ARM::VLD4q8_UPD: 2531 case ARM::VLD4q16_UPD: 2532 case ARM::VLD4q32_UPD: 2533 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 break; 2536 default: 2537 break; 2538 } 2539 2540 // AddrMode6 Base (register+alignment) 2541 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2542 return MCDisassembler::Fail; 2543 2544 // AddrMode6 Offset (register) 2545 switch (Inst.getOpcode()) { 2546 default: 2547 // The below have been updated to have explicit am6offset split 2548 // between fixed and register offset. For those instructions not 2549 // yet updated, we need to add an additional reg0 operand for the 2550 // fixed variant. 2551 // 2552 // The fixed offset encodes as Rm == 0xd, so we check for that. 2553 if (Rm == 0xd) { 2554 Inst.addOperand(MCOperand::createReg(0)); 2555 break; 2556 } 2557 // Fall through to handle the register offset variant. 2558 LLVM_FALLTHROUGH; 2559 case ARM::VLD1d8wb_fixed: 2560 case ARM::VLD1d16wb_fixed: 2561 case ARM::VLD1d32wb_fixed: 2562 case ARM::VLD1d64wb_fixed: 2563 case ARM::VLD1d8Twb_fixed: 2564 case ARM::VLD1d16Twb_fixed: 2565 case ARM::VLD1d32Twb_fixed: 2566 case ARM::VLD1d64Twb_fixed: 2567 case ARM::VLD1d8Qwb_fixed: 2568 case ARM::VLD1d16Qwb_fixed: 2569 case ARM::VLD1d32Qwb_fixed: 2570 case ARM::VLD1d64Qwb_fixed: 2571 case ARM::VLD1d8wb_register: 2572 case ARM::VLD1d16wb_register: 2573 case ARM::VLD1d32wb_register: 2574 case ARM::VLD1d64wb_register: 2575 case ARM::VLD1q8wb_fixed: 2576 case ARM::VLD1q16wb_fixed: 2577 case ARM::VLD1q32wb_fixed: 2578 case ARM::VLD1q64wb_fixed: 2579 case ARM::VLD1q8wb_register: 2580 case ARM::VLD1q16wb_register: 2581 case ARM::VLD1q32wb_register: 2582 case ARM::VLD1q64wb_register: 2583 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2584 // variant encodes Rm == 0xf. Anything else is a register offset post- 2585 // increment and we need to add the register operand to the instruction. 2586 if (Rm != 0xD && Rm != 0xF && 2587 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2588 return MCDisassembler::Fail; 2589 break; 2590 case ARM::VLD2d8wb_fixed: 2591 case ARM::VLD2d16wb_fixed: 2592 case ARM::VLD2d32wb_fixed: 2593 case ARM::VLD2b8wb_fixed: 2594 case ARM::VLD2b16wb_fixed: 2595 case ARM::VLD2b32wb_fixed: 2596 case ARM::VLD2q8wb_fixed: 2597 case ARM::VLD2q16wb_fixed: 2598 case ARM::VLD2q32wb_fixed: 2599 break; 2600 } 2601 2602 return S; 2603} 2604 2605static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2606 uint64_t Address, const void *Decoder) { 2607 unsigned type = fieldFromInstruction(Insn, 8, 4); 2608 unsigned align = fieldFromInstruction(Insn, 4, 2); 2609 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2610 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2611 if (type == 10 && align == 3) return MCDisassembler::Fail; 2612 2613 unsigned load = fieldFromInstruction(Insn, 21, 1); 2614 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2615 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2616} 2617 2618static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2619 uint64_t Address, const void *Decoder) { 2620 unsigned size = fieldFromInstruction(Insn, 6, 2); 2621 if (size == 3) return MCDisassembler::Fail; 2622 2623 unsigned type = fieldFromInstruction(Insn, 8, 4); 2624 unsigned align = fieldFromInstruction(Insn, 4, 2); 2625 if (type == 8 && align == 3) return MCDisassembler::Fail; 2626 if (type == 9 && align == 3) return MCDisassembler::Fail; 2627 2628 unsigned load = fieldFromInstruction(Insn, 21, 1); 2629 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2630 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2631} 2632 2633static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2634 uint64_t Address, const void *Decoder) { 2635 unsigned size = fieldFromInstruction(Insn, 6, 2); 2636 if (size == 3) return MCDisassembler::Fail; 2637 2638 unsigned align = fieldFromInstruction(Insn, 4, 2); 2639 if (align & 2) return MCDisassembler::Fail; 2640 2641 unsigned load = fieldFromInstruction(Insn, 21, 1); 2642 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2643 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2644} 2645 2646static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2647 uint64_t Address, const void *Decoder) { 2648 unsigned size = fieldFromInstruction(Insn, 6, 2); 2649 if (size == 3) return MCDisassembler::Fail; 2650 2651 unsigned load = fieldFromInstruction(Insn, 21, 1); 2652 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2653 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2654} 2655 2656static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2657 uint64_t Address, const void *Decoder) { 2658 DecodeStatus S = MCDisassembler::Success; 2659 2660 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2661 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2662 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2663 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2664 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2665 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2666 2667 // Writeback Operand 2668 switch (Inst.getOpcode()) { 2669 case ARM::VST1d8wb_fixed: 2670 case ARM::VST1d16wb_fixed: 2671 case ARM::VST1d32wb_fixed: 2672 case ARM::VST1d64wb_fixed: 2673 case ARM::VST1d8wb_register: 2674 case ARM::VST1d16wb_register: 2675 case ARM::VST1d32wb_register: 2676 case ARM::VST1d64wb_register: 2677 case ARM::VST1q8wb_fixed: 2678 case ARM::VST1q16wb_fixed: 2679 case ARM::VST1q32wb_fixed: 2680 case ARM::VST1q64wb_fixed: 2681 case ARM::VST1q8wb_register: 2682 case ARM::VST1q16wb_register: 2683 case ARM::VST1q32wb_register: 2684 case ARM::VST1q64wb_register: 2685 case ARM::VST1d8Twb_fixed: 2686 case ARM::VST1d16Twb_fixed: 2687 case ARM::VST1d32Twb_fixed: 2688 case ARM::VST1d64Twb_fixed: 2689 case ARM::VST1d8Twb_register: 2690 case ARM::VST1d16Twb_register: 2691 case ARM::VST1d32Twb_register: 2692 case ARM::VST1d64Twb_register: 2693 case ARM::VST1d8Qwb_fixed: 2694 case ARM::VST1d16Qwb_fixed: 2695 case ARM::VST1d32Qwb_fixed: 2696 case ARM::VST1d64Qwb_fixed: 2697 case ARM::VST1d8Qwb_register: 2698 case ARM::VST1d16Qwb_register: 2699 case ARM::VST1d32Qwb_register: 2700 case ARM::VST1d64Qwb_register: 2701 case ARM::VST2d8wb_fixed: 2702 case ARM::VST2d16wb_fixed: 2703 case ARM::VST2d32wb_fixed: 2704 case ARM::VST2d8wb_register: 2705 case ARM::VST2d16wb_register: 2706 case ARM::VST2d32wb_register: 2707 case ARM::VST2q8wb_fixed: 2708 case ARM::VST2q16wb_fixed: 2709 case ARM::VST2q32wb_fixed: 2710 case ARM::VST2q8wb_register: 2711 case ARM::VST2q16wb_register: 2712 case ARM::VST2q32wb_register: 2713 case ARM::VST2b8wb_fixed: 2714 case ARM::VST2b16wb_fixed: 2715 case ARM::VST2b32wb_fixed: 2716 case ARM::VST2b8wb_register: 2717 case ARM::VST2b16wb_register: 2718 case ARM::VST2b32wb_register: 2719 if (Rm == 0xF) 2720 return MCDisassembler::Fail; 2721 Inst.addOperand(MCOperand::createImm(0)); 2722 break; 2723 case ARM::VST3d8_UPD: 2724 case ARM::VST3d16_UPD: 2725 case ARM::VST3d32_UPD: 2726 case ARM::VST3q8_UPD: 2727 case ARM::VST3q16_UPD: 2728 case ARM::VST3q32_UPD: 2729 case ARM::VST4d8_UPD: 2730 case ARM::VST4d16_UPD: 2731 case ARM::VST4d32_UPD: 2732 case ARM::VST4q8_UPD: 2733 case ARM::VST4q16_UPD: 2734 case ARM::VST4q32_UPD: 2735 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 break; 2738 default: 2739 break; 2740 } 2741 2742 // AddrMode6 Base (register+alignment) 2743 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2744 return MCDisassembler::Fail; 2745 2746 // AddrMode6 Offset (register) 2747 switch (Inst.getOpcode()) { 2748 default: 2749 if (Rm == 0xD) 2750 Inst.addOperand(MCOperand::createReg(0)); 2751 else if (Rm != 0xF) { 2752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 } 2755 break; 2756 case ARM::VST1d8wb_fixed: 2757 case ARM::VST1d16wb_fixed: 2758 case ARM::VST1d32wb_fixed: 2759 case ARM::VST1d64wb_fixed: 2760 case ARM::VST1q8wb_fixed: 2761 case ARM::VST1q16wb_fixed: 2762 case ARM::VST1q32wb_fixed: 2763 case ARM::VST1q64wb_fixed: 2764 case ARM::VST1d8Twb_fixed: 2765 case ARM::VST1d16Twb_fixed: 2766 case ARM::VST1d32Twb_fixed: 2767 case ARM::VST1d64Twb_fixed: 2768 case ARM::VST1d8Qwb_fixed: 2769 case ARM::VST1d16Qwb_fixed: 2770 case ARM::VST1d32Qwb_fixed: 2771 case ARM::VST1d64Qwb_fixed: 2772 case ARM::VST2d8wb_fixed: 2773 case ARM::VST2d16wb_fixed: 2774 case ARM::VST2d32wb_fixed: 2775 case ARM::VST2q8wb_fixed: 2776 case ARM::VST2q16wb_fixed: 2777 case ARM::VST2q32wb_fixed: 2778 case ARM::VST2b8wb_fixed: 2779 case ARM::VST2b16wb_fixed: 2780 case ARM::VST2b32wb_fixed: 2781 break; 2782 } 2783 2784 2785 // First input register 2786 switch (Inst.getOpcode()) { 2787 case ARM::VST1q16: 2788 case ARM::VST1q32: 2789 case ARM::VST1q64: 2790 case ARM::VST1q8: 2791 case ARM::VST1q16wb_fixed: 2792 case ARM::VST1q16wb_register: 2793 case ARM::VST1q32wb_fixed: 2794 case ARM::VST1q32wb_register: 2795 case ARM::VST1q64wb_fixed: 2796 case ARM::VST1q64wb_register: 2797 case ARM::VST1q8wb_fixed: 2798 case ARM::VST1q8wb_register: 2799 case ARM::VST2d16: 2800 case ARM::VST2d32: 2801 case ARM::VST2d8: 2802 case ARM::VST2d16wb_fixed: 2803 case ARM::VST2d16wb_register: 2804 case ARM::VST2d32wb_fixed: 2805 case ARM::VST2d32wb_register: 2806 case ARM::VST2d8wb_fixed: 2807 case ARM::VST2d8wb_register: 2808 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2809 return MCDisassembler::Fail; 2810 break; 2811 case ARM::VST2b16: 2812 case ARM::VST2b32: 2813 case ARM::VST2b8: 2814 case ARM::VST2b16wb_fixed: 2815 case ARM::VST2b16wb_register: 2816 case ARM::VST2b32wb_fixed: 2817 case ARM::VST2b32wb_register: 2818 case ARM::VST2b8wb_fixed: 2819 case ARM::VST2b8wb_register: 2820 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2821 return MCDisassembler::Fail; 2822 break; 2823 default: 2824 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2825 return MCDisassembler::Fail; 2826 } 2827 2828 // Second input register 2829 switch (Inst.getOpcode()) { 2830 case ARM::VST3d8: 2831 case ARM::VST3d16: 2832 case ARM::VST3d32: 2833 case ARM::VST3d8_UPD: 2834 case ARM::VST3d16_UPD: 2835 case ARM::VST3d32_UPD: 2836 case ARM::VST4d8: 2837 case ARM::VST4d16: 2838 case ARM::VST4d32: 2839 case ARM::VST4d8_UPD: 2840 case ARM::VST4d16_UPD: 2841 case ARM::VST4d32_UPD: 2842 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2843 return MCDisassembler::Fail; 2844 break; 2845 case ARM::VST3q8: 2846 case ARM::VST3q16: 2847 case ARM::VST3q32: 2848 case ARM::VST3q8_UPD: 2849 case ARM::VST3q16_UPD: 2850 case ARM::VST3q32_UPD: 2851 case ARM::VST4q8: 2852 case ARM::VST4q16: 2853 case ARM::VST4q32: 2854 case ARM::VST4q8_UPD: 2855 case ARM::VST4q16_UPD: 2856 case ARM::VST4q32_UPD: 2857 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2858 return MCDisassembler::Fail; 2859 break; 2860 default: 2861 break; 2862 } 2863 2864 // Third input register 2865 switch (Inst.getOpcode()) { 2866 case ARM::VST3d8: 2867 case ARM::VST3d16: 2868 case ARM::VST3d32: 2869 case ARM::VST3d8_UPD: 2870 case ARM::VST3d16_UPD: 2871 case ARM::VST3d32_UPD: 2872 case ARM::VST4d8: 2873 case ARM::VST4d16: 2874 case ARM::VST4d32: 2875 case ARM::VST4d8_UPD: 2876 case ARM::VST4d16_UPD: 2877 case ARM::VST4d32_UPD: 2878 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2879 return MCDisassembler::Fail; 2880 break; 2881 case ARM::VST3q8: 2882 case ARM::VST3q16: 2883 case ARM::VST3q32: 2884 case ARM::VST3q8_UPD: 2885 case ARM::VST3q16_UPD: 2886 case ARM::VST3q32_UPD: 2887 case ARM::VST4q8: 2888 case ARM::VST4q16: 2889 case ARM::VST4q32: 2890 case ARM::VST4q8_UPD: 2891 case ARM::VST4q16_UPD: 2892 case ARM::VST4q32_UPD: 2893 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2894 return MCDisassembler::Fail; 2895 break; 2896 default: 2897 break; 2898 } 2899 2900 // Fourth input register 2901 switch (Inst.getOpcode()) { 2902 case ARM::VST4d8: 2903 case ARM::VST4d16: 2904 case ARM::VST4d32: 2905 case ARM::VST4d8_UPD: 2906 case ARM::VST4d16_UPD: 2907 case ARM::VST4d32_UPD: 2908 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 break; 2911 case ARM::VST4q8: 2912 case ARM::VST4q16: 2913 case ARM::VST4q32: 2914 case ARM::VST4q8_UPD: 2915 case ARM::VST4q16_UPD: 2916 case ARM::VST4q32_UPD: 2917 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2918 return MCDisassembler::Fail; 2919 break; 2920 default: 2921 break; 2922 } 2923 2924 return S; 2925} 2926 2927static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2928 uint64_t Address, const void *Decoder) { 2929 DecodeStatus S = MCDisassembler::Success; 2930 2931 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2932 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2933 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2934 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2935 unsigned align = fieldFromInstruction(Insn, 4, 1); 2936 unsigned size = fieldFromInstruction(Insn, 6, 2); 2937 2938 if (size == 0 && align == 1) 2939 return MCDisassembler::Fail; 2940 align *= (1 << size); 2941 2942 switch (Inst.getOpcode()) { 2943 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2944 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2945 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2946 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2947 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2948 return MCDisassembler::Fail; 2949 break; 2950 default: 2951 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2952 return MCDisassembler::Fail; 2953 break; 2954 } 2955 if (Rm != 0xF) { 2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 } 2959 2960 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2961 return MCDisassembler::Fail; 2962 Inst.addOperand(MCOperand::createImm(align)); 2963 2964 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2965 // variant encodes Rm == 0xf. Anything else is a register offset post- 2966 // increment and we need to add the register operand to the instruction. 2967 if (Rm != 0xD && Rm != 0xF && 2968 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2969 return MCDisassembler::Fail; 2970 2971 return S; 2972} 2973 2974static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2975 uint64_t Address, const void *Decoder) { 2976 DecodeStatus S = MCDisassembler::Success; 2977 2978 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2979 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2980 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2981 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2982 unsigned align = fieldFromInstruction(Insn, 4, 1); 2983 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2984 align *= 2*size; 2985 2986 switch (Inst.getOpcode()) { 2987 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2988 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2989 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2990 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2991 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2992 return MCDisassembler::Fail; 2993 break; 2994 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2995 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2996 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2997 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2998 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2999 return MCDisassembler::Fail; 3000 break; 3001 default: 3002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3003 return MCDisassembler::Fail; 3004 break; 3005 } 3006 3007 if (Rm != 0xF) 3008 Inst.addOperand(MCOperand::createImm(0)); 3009 3010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3011 return MCDisassembler::Fail; 3012 Inst.addOperand(MCOperand::createImm(align)); 3013 3014 if (Rm != 0xD && Rm != 0xF) { 3015 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3016 return MCDisassembler::Fail; 3017 } 3018 3019 return S; 3020} 3021 3022static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3023 uint64_t Address, const void *Decoder) { 3024 DecodeStatus S = MCDisassembler::Success; 3025 3026 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3027 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3028 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3029 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3030 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3031 3032 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3033 return MCDisassembler::Fail; 3034 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3035 return MCDisassembler::Fail; 3036 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3037 return MCDisassembler::Fail; 3038 if (Rm != 0xF) { 3039 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3040 return MCDisassembler::Fail; 3041 } 3042 3043 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3044 return MCDisassembler::Fail; 3045 Inst.addOperand(MCOperand::createImm(0)); 3046 3047 if (Rm == 0xD) 3048 Inst.addOperand(MCOperand::createReg(0)); 3049 else if (Rm != 0xF) { 3050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 } 3053 3054 return S; 3055} 3056 3057static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3058 uint64_t Address, const void *Decoder) { 3059 DecodeStatus S = MCDisassembler::Success; 3060 3061 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3062 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3063 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3064 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3065 unsigned size = fieldFromInstruction(Insn, 6, 2); 3066 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3067 unsigned align = fieldFromInstruction(Insn, 4, 1); 3068 3069 if (size == 0x3) { 3070 if (align == 0) 3071 return MCDisassembler::Fail; 3072 align = 16; 3073 } else { 3074 if (size == 2) { 3075 align *= 8; 3076 } else { 3077 size = 1 << size; 3078 align *= 4*size; 3079 } 3080 } 3081 3082 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3085 return MCDisassembler::Fail; 3086 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3087 return MCDisassembler::Fail; 3088 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3089 return MCDisassembler::Fail; 3090 if (Rm != 0xF) { 3091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3092 return MCDisassembler::Fail; 3093 } 3094 3095 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3096 return MCDisassembler::Fail; 3097 Inst.addOperand(MCOperand::createImm(align)); 3098 3099 if (Rm == 0xD) 3100 Inst.addOperand(MCOperand::createReg(0)); 3101 else if (Rm != 0xF) { 3102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3103 return MCDisassembler::Fail; 3104 } 3105 3106 return S; 3107} 3108 3109static DecodeStatus 3110DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3111 uint64_t Address, const void *Decoder) { 3112 DecodeStatus S = MCDisassembler::Success; 3113 3114 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3115 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3116 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3117 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3118 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3119 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3120 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3121 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3122 3123 if (Q) { 3124 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3125 return MCDisassembler::Fail; 3126 } else { 3127 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3128 return MCDisassembler::Fail; 3129 } 3130 3131 Inst.addOperand(MCOperand::createImm(imm)); 3132 3133 switch (Inst.getOpcode()) { 3134 case ARM::VORRiv4i16: 3135 case ARM::VORRiv2i32: 3136 case ARM::VBICiv4i16: 3137 case ARM::VBICiv2i32: 3138 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 break; 3141 case ARM::VORRiv8i16: 3142 case ARM::VORRiv4i32: 3143 case ARM::VBICiv8i16: 3144 case ARM::VBICiv4i32: 3145 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3146 return MCDisassembler::Fail; 3147 break; 3148 default: 3149 break; 3150 } 3151 3152 return S; 3153} 3154 3155static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3156 uint64_t Address, const void *Decoder) { 3157 DecodeStatus S = MCDisassembler::Success; 3158 3159 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3160 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3161 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3162 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3163 unsigned size = fieldFromInstruction(Insn, 18, 2); 3164 3165 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3166 return MCDisassembler::Fail; 3167 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3168 return MCDisassembler::Fail; 3169 Inst.addOperand(MCOperand::createImm(8 << size)); 3170 3171 return S; 3172} 3173 3174static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3175 uint64_t Address, const void *Decoder) { 3176 Inst.addOperand(MCOperand::createImm(8 - Val)); 3177 return MCDisassembler::Success; 3178} 3179 3180static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3181 uint64_t Address, const void *Decoder) { 3182 Inst.addOperand(MCOperand::createImm(16 - Val)); 3183 return MCDisassembler::Success; 3184} 3185 3186static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3187 uint64_t Address, const void *Decoder) { 3188 Inst.addOperand(MCOperand::createImm(32 - Val)); 3189 return MCDisassembler::Success; 3190} 3191 3192static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3193 uint64_t Address, const void *Decoder) { 3194 Inst.addOperand(MCOperand::createImm(64 - Val)); 3195 return MCDisassembler::Success; 3196} 3197 3198static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3199 uint64_t Address, const void *Decoder) { 3200 DecodeStatus S = MCDisassembler::Success; 3201 3202 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3203 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3204 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3205 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3206 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3207 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3208 unsigned op = fieldFromInstruction(Insn, 6, 1); 3209 3210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3211 return MCDisassembler::Fail; 3212 if (op) { 3213 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3214 return MCDisassembler::Fail; // Writeback 3215 } 3216 3217 switch (Inst.getOpcode()) { 3218 case ARM::VTBL2: 3219 case ARM::VTBX2: 3220 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3221 return MCDisassembler::Fail; 3222 break; 3223 default: 3224 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3225 return MCDisassembler::Fail; 3226 } 3227 3228 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 3231 return S; 3232} 3233 3234static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3235 uint64_t Address, const void *Decoder) { 3236 DecodeStatus S = MCDisassembler::Success; 3237 3238 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3239 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3240 3241 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3242 return MCDisassembler::Fail; 3243 3244 switch(Inst.getOpcode()) { 3245 default: 3246 return MCDisassembler::Fail; 3247 case ARM::tADR: 3248 break; // tADR does not explicitly represent the PC as an operand. 3249 case ARM::tADDrSPi: 3250 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3251 break; 3252 } 3253 3254 Inst.addOperand(MCOperand::createImm(imm)); 3255 return S; 3256} 3257 3258static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3259 uint64_t Address, const void *Decoder) { 3260 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3261 true, 2, Inst, Decoder)) 3262 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3263 return MCDisassembler::Success; 3264} 3265 3266static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3267 uint64_t Address, const void *Decoder) { 3268 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3269 true, 4, Inst, Decoder)) 3270 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3271 return MCDisassembler::Success; 3272} 3273 3274static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3275 uint64_t Address, const void *Decoder) { 3276 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3277 true, 2, Inst, Decoder)) 3278 Inst.addOperand(MCOperand::createImm(Val << 1)); 3279 return MCDisassembler::Success; 3280} 3281 3282static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3283 uint64_t Address, const void *Decoder) { 3284 DecodeStatus S = MCDisassembler::Success; 3285 3286 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3287 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3288 3289 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3290 return MCDisassembler::Fail; 3291 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 3294 return S; 3295} 3296 3297static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3298 uint64_t Address, const void *Decoder) { 3299 DecodeStatus S = MCDisassembler::Success; 3300 3301 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3302 unsigned imm = fieldFromInstruction(Val, 3, 5); 3303 3304 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3305 return MCDisassembler::Fail; 3306 Inst.addOperand(MCOperand::createImm(imm)); 3307 3308 return S; 3309} 3310 3311static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3312 uint64_t Address, const void *Decoder) { 3313 unsigned imm = Val << 2; 3314 3315 Inst.addOperand(MCOperand::createImm(imm)); 3316 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3317 3318 return MCDisassembler::Success; 3319} 3320 3321static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3322 uint64_t Address, const void *Decoder) { 3323 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3324 Inst.addOperand(MCOperand::createImm(Val)); 3325 3326 return MCDisassembler::Success; 3327} 3328 3329static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3330 uint64_t Address, const void *Decoder) { 3331 DecodeStatus S = MCDisassembler::Success; 3332 3333 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3334 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3335 unsigned imm = fieldFromInstruction(Val, 0, 2); 3336 3337 // Thumb stores cannot use PC as dest register. 3338 switch (Inst.getOpcode()) { 3339 case ARM::t2STRHs: 3340 case ARM::t2STRBs: 3341 case ARM::t2STRs: 3342 if (Rn == 15) 3343 return MCDisassembler::Fail; 3344 default: 3345 break; 3346 } 3347 3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3349 return MCDisassembler::Fail; 3350 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3351 return MCDisassembler::Fail; 3352 Inst.addOperand(MCOperand::createImm(imm)); 3353 3354 return S; 3355} 3356 3357static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3358 uint64_t Address, const void *Decoder) { 3359 DecodeStatus S = MCDisassembler::Success; 3360 3361 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3362 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3363 3364 const FeatureBitset &featureBits = 3365 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3366 3367 bool hasMP = featureBits[ARM::FeatureMP]; 3368 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3369 3370 if (Rn == 15) { 3371 switch (Inst.getOpcode()) { 3372 case ARM::t2LDRBs: 3373 Inst.setOpcode(ARM::t2LDRBpci); 3374 break; 3375 case ARM::t2LDRHs: 3376 Inst.setOpcode(ARM::t2LDRHpci); 3377 break; 3378 case ARM::t2LDRSHs: 3379 Inst.setOpcode(ARM::t2LDRSHpci); 3380 break; 3381 case ARM::t2LDRSBs: 3382 Inst.setOpcode(ARM::t2LDRSBpci); 3383 break; 3384 case ARM::t2LDRs: 3385 Inst.setOpcode(ARM::t2LDRpci); 3386 break; 3387 case ARM::t2PLDs: 3388 Inst.setOpcode(ARM::t2PLDpci); 3389 break; 3390 case ARM::t2PLIs: 3391 Inst.setOpcode(ARM::t2PLIpci); 3392 break; 3393 default: 3394 return MCDisassembler::Fail; 3395 } 3396 3397 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3398 } 3399 3400 if (Rt == 15) { 3401 switch (Inst.getOpcode()) { 3402 case ARM::t2LDRSHs: 3403 return MCDisassembler::Fail; 3404 case ARM::t2LDRHs: 3405 Inst.setOpcode(ARM::t2PLDWs); 3406 break; 3407 case ARM::t2LDRSBs: 3408 Inst.setOpcode(ARM::t2PLIs); 3409 default: 3410 break; 3411 } 3412 } 3413 3414 switch (Inst.getOpcode()) { 3415 case ARM::t2PLDs: 3416 break; 3417 case ARM::t2PLIs: 3418 if (!hasV7Ops) 3419 return MCDisassembler::Fail; 3420 break; 3421 case ARM::t2PLDWs: 3422 if (!hasV7Ops || !hasMP) 3423 return MCDisassembler::Fail; 3424 break; 3425 default: 3426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3427 return MCDisassembler::Fail; 3428 } 3429 3430 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3431 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3432 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3433 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 3436 return S; 3437} 3438 3439static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3440 uint64_t Address, const void* Decoder) { 3441 DecodeStatus S = MCDisassembler::Success; 3442 3443 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3444 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3445 unsigned U = fieldFromInstruction(Insn, 9, 1); 3446 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3447 imm |= (U << 8); 3448 imm |= (Rn << 9); 3449 unsigned add = fieldFromInstruction(Insn, 9, 1); 3450 3451 const FeatureBitset &featureBits = 3452 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3453 3454 bool hasMP = featureBits[ARM::FeatureMP]; 3455 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3456 3457 if (Rn == 15) { 3458 switch (Inst.getOpcode()) { 3459 case ARM::t2LDRi8: 3460 Inst.setOpcode(ARM::t2LDRpci); 3461 break; 3462 case ARM::t2LDRBi8: 3463 Inst.setOpcode(ARM::t2LDRBpci); 3464 break; 3465 case ARM::t2LDRSBi8: 3466 Inst.setOpcode(ARM::t2LDRSBpci); 3467 break; 3468 case ARM::t2LDRHi8: 3469 Inst.setOpcode(ARM::t2LDRHpci); 3470 break; 3471 case ARM::t2LDRSHi8: 3472 Inst.setOpcode(ARM::t2LDRSHpci); 3473 break; 3474 case ARM::t2PLDi8: 3475 Inst.setOpcode(ARM::t2PLDpci); 3476 break; 3477 case ARM::t2PLIi8: 3478 Inst.setOpcode(ARM::t2PLIpci); 3479 break; 3480 default: 3481 return MCDisassembler::Fail; 3482 } 3483 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3484 } 3485 3486 if (Rt == 15) { 3487 switch (Inst.getOpcode()) { 3488 case ARM::t2LDRSHi8: 3489 return MCDisassembler::Fail; 3490 case ARM::t2LDRHi8: 3491 if (!add) 3492 Inst.setOpcode(ARM::t2PLDWi8); 3493 break; 3494 case ARM::t2LDRSBi8: 3495 Inst.setOpcode(ARM::t2PLIi8); 3496 break; 3497 default: 3498 break; 3499 } 3500 } 3501 3502 switch (Inst.getOpcode()) { 3503 case ARM::t2PLDi8: 3504 break; 3505 case ARM::t2PLIi8: 3506 if (!hasV7Ops) 3507 return MCDisassembler::Fail; 3508 break; 3509 case ARM::t2PLDWi8: 3510 if (!hasV7Ops || !hasMP) 3511 return MCDisassembler::Fail; 3512 break; 3513 default: 3514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3515 return MCDisassembler::Fail; 3516 } 3517 3518 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3519 return MCDisassembler::Fail; 3520 return S; 3521} 3522 3523static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3524 uint64_t Address, const void* Decoder) { 3525 DecodeStatus S = MCDisassembler::Success; 3526 3527 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3528 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3529 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3530 imm |= (Rn << 13); 3531 3532 const FeatureBitset &featureBits = 3533 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3534 3535 bool hasMP = featureBits[ARM::FeatureMP]; 3536 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3537 3538 if (Rn == 15) { 3539 switch (Inst.getOpcode()) { 3540 case ARM::t2LDRi12: 3541 Inst.setOpcode(ARM::t2LDRpci); 3542 break; 3543 case ARM::t2LDRHi12: 3544 Inst.setOpcode(ARM::t2LDRHpci); 3545 break; 3546 case ARM::t2LDRSHi12: 3547 Inst.setOpcode(ARM::t2LDRSHpci); 3548 break; 3549 case ARM::t2LDRBi12: 3550 Inst.setOpcode(ARM::t2LDRBpci); 3551 break; 3552 case ARM::t2LDRSBi12: 3553 Inst.setOpcode(ARM::t2LDRSBpci); 3554 break; 3555 case ARM::t2PLDi12: 3556 Inst.setOpcode(ARM::t2PLDpci); 3557 break; 3558 case ARM::t2PLIi12: 3559 Inst.setOpcode(ARM::t2PLIpci); 3560 break; 3561 default: 3562 return MCDisassembler::Fail; 3563 } 3564 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3565 } 3566 3567 if (Rt == 15) { 3568 switch (Inst.getOpcode()) { 3569 case ARM::t2LDRSHi12: 3570 return MCDisassembler::Fail; 3571 case ARM::t2LDRHi12: 3572 Inst.setOpcode(ARM::t2PLDWi12); 3573 break; 3574 case ARM::t2LDRSBi12: 3575 Inst.setOpcode(ARM::t2PLIi12); 3576 break; 3577 default: 3578 break; 3579 } 3580 } 3581 3582 switch (Inst.getOpcode()) { 3583 case ARM::t2PLDi12: 3584 break; 3585 case ARM::t2PLIi12: 3586 if (!hasV7Ops) 3587 return MCDisassembler::Fail; 3588 break; 3589 case ARM::t2PLDWi12: 3590 if (!hasV7Ops || !hasMP) 3591 return MCDisassembler::Fail; 3592 break; 3593 default: 3594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3595 return MCDisassembler::Fail; 3596 } 3597 3598 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3599 return MCDisassembler::Fail; 3600 return S; 3601} 3602 3603static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3604 uint64_t Address, const void* Decoder) { 3605 DecodeStatus S = MCDisassembler::Success; 3606 3607 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3608 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3609 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3610 imm |= (Rn << 9); 3611 3612 if (Rn == 15) { 3613 switch (Inst.getOpcode()) { 3614 case ARM::t2LDRT: 3615 Inst.setOpcode(ARM::t2LDRpci); 3616 break; 3617 case ARM::t2LDRBT: 3618 Inst.setOpcode(ARM::t2LDRBpci); 3619 break; 3620 case ARM::t2LDRHT: 3621 Inst.setOpcode(ARM::t2LDRHpci); 3622 break; 3623 case ARM::t2LDRSBT: 3624 Inst.setOpcode(ARM::t2LDRSBpci); 3625 break; 3626 case ARM::t2LDRSHT: 3627 Inst.setOpcode(ARM::t2LDRSHpci); 3628 break; 3629 default: 3630 return MCDisassembler::Fail; 3631 } 3632 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3633 } 3634 3635 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3638 return MCDisassembler::Fail; 3639 return S; 3640} 3641 3642static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3643 uint64_t Address, const void* Decoder) { 3644 DecodeStatus S = MCDisassembler::Success; 3645 3646 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3647 unsigned U = fieldFromInstruction(Insn, 23, 1); 3648 int imm = fieldFromInstruction(Insn, 0, 12); 3649 3650 const FeatureBitset &featureBits = 3651 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3652 3653 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3654 3655 if (Rt == 15) { 3656 switch (Inst.getOpcode()) { 3657 case ARM::t2LDRBpci: 3658 case ARM::t2LDRHpci: 3659 Inst.setOpcode(ARM::t2PLDpci); 3660 break; 3661 case ARM::t2LDRSBpci: 3662 Inst.setOpcode(ARM::t2PLIpci); 3663 break; 3664 case ARM::t2LDRSHpci: 3665 return MCDisassembler::Fail; 3666 default: 3667 break; 3668 } 3669 } 3670 3671 switch(Inst.getOpcode()) { 3672 case ARM::t2PLDpci: 3673 break; 3674 case ARM::t2PLIpci: 3675 if (!hasV7Ops) 3676 return MCDisassembler::Fail; 3677 break; 3678 default: 3679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 } 3682 3683 if (!U) { 3684 // Special case for #-0. 3685 if (imm == 0) 3686 imm = INT32_MIN; 3687 else 3688 imm = -imm; 3689 } 3690 Inst.addOperand(MCOperand::createImm(imm)); 3691 3692 return S; 3693} 3694 3695static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3696 uint64_t Address, const void *Decoder) { 3697 if (Val == 0) 3698 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3699 else { 3700 int imm = Val & 0xFF; 3701 3702 if (!(Val & 0x100)) imm *= -1; 3703 Inst.addOperand(MCOperand::createImm(imm * 4)); 3704 } 3705 3706 return MCDisassembler::Success; 3707} 3708 3709static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3710 uint64_t Address, const void *Decoder) { 3711 DecodeStatus S = MCDisassembler::Success; 3712 3713 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3714 unsigned imm = fieldFromInstruction(Val, 0, 9); 3715 3716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3717 return MCDisassembler::Fail; 3718 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3719 return MCDisassembler::Fail; 3720 3721 return S; 3722} 3723 3724static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3725 uint64_t Address, const void *Decoder) { 3726 DecodeStatus S = MCDisassembler::Success; 3727 3728 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3729 unsigned imm = fieldFromInstruction(Val, 0, 8); 3730 3731 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3732 return MCDisassembler::Fail; 3733 3734 Inst.addOperand(MCOperand::createImm(imm)); 3735 3736 return S; 3737} 3738 3739static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3740 uint64_t Address, const void *Decoder) { 3741 int imm = Val & 0xFF; 3742 if (Val == 0) 3743 imm = INT32_MIN; 3744 else if (!(Val & 0x100)) 3745 imm *= -1; 3746 Inst.addOperand(MCOperand::createImm(imm)); 3747 3748 return MCDisassembler::Success; 3749} 3750 3751 3752static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3753 uint64_t Address, const void *Decoder) { 3754 DecodeStatus S = MCDisassembler::Success; 3755 3756 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3757 unsigned imm = fieldFromInstruction(Val, 0, 9); 3758 3759 // Thumb stores cannot use PC as dest register. 3760 switch (Inst.getOpcode()) { 3761 case ARM::t2STRT: 3762 case ARM::t2STRBT: 3763 case ARM::t2STRHT: 3764 case ARM::t2STRi8: 3765 case ARM::t2STRHi8: 3766 case ARM::t2STRBi8: 3767 if (Rn == 15) 3768 return MCDisassembler::Fail; 3769 break; 3770 default: 3771 break; 3772 } 3773 3774 // Some instructions always use an additive offset. 3775 switch (Inst.getOpcode()) { 3776 case ARM::t2LDRT: 3777 case ARM::t2LDRBT: 3778 case ARM::t2LDRHT: 3779 case ARM::t2LDRSBT: 3780 case ARM::t2LDRSHT: 3781 case ARM::t2STRT: 3782 case ARM::t2STRBT: 3783 case ARM::t2STRHT: 3784 imm |= 0x100; 3785 break; 3786 default: 3787 break; 3788 } 3789 3790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3791 return MCDisassembler::Fail; 3792 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3793 return MCDisassembler::Fail; 3794 3795 return S; 3796} 3797 3798static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3799 uint64_t Address, const void *Decoder) { 3800 DecodeStatus S = MCDisassembler::Success; 3801 3802 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3803 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3804 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3805 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3806 addr |= Rn << 9; 3807 unsigned load = fieldFromInstruction(Insn, 20, 1); 3808 3809 if (Rn == 15) { 3810 switch (Inst.getOpcode()) { 3811 case ARM::t2LDR_PRE: 3812 case ARM::t2LDR_POST: 3813 Inst.setOpcode(ARM::t2LDRpci); 3814 break; 3815 case ARM::t2LDRB_PRE: 3816 case ARM::t2LDRB_POST: 3817 Inst.setOpcode(ARM::t2LDRBpci); 3818 break; 3819 case ARM::t2LDRH_PRE: 3820 case ARM::t2LDRH_POST: 3821 Inst.setOpcode(ARM::t2LDRHpci); 3822 break; 3823 case ARM::t2LDRSB_PRE: 3824 case ARM::t2LDRSB_POST: 3825 if (Rt == 15) 3826 Inst.setOpcode(ARM::t2PLIpci); 3827 else 3828 Inst.setOpcode(ARM::t2LDRSBpci); 3829 break; 3830 case ARM::t2LDRSH_PRE: 3831 case ARM::t2LDRSH_POST: 3832 Inst.setOpcode(ARM::t2LDRSHpci); 3833 break; 3834 default: 3835 return MCDisassembler::Fail; 3836 } 3837 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3838 } 3839 3840 if (!load) { 3841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3842 return MCDisassembler::Fail; 3843 } 3844 3845 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3846 return MCDisassembler::Fail; 3847 3848 if (load) { 3849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3850 return MCDisassembler::Fail; 3851 } 3852 3853 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3854 return MCDisassembler::Fail; 3855 3856 return S; 3857} 3858 3859static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3860 uint64_t Address, const void *Decoder) { 3861 DecodeStatus S = MCDisassembler::Success; 3862 3863 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3864 unsigned imm = fieldFromInstruction(Val, 0, 12); 3865 3866 // Thumb stores cannot use PC as dest register. 3867 switch (Inst.getOpcode()) { 3868 case ARM::t2STRi12: 3869 case ARM::t2STRBi12: 3870 case ARM::t2STRHi12: 3871 if (Rn == 15) 3872 return MCDisassembler::Fail; 3873 default: 3874 break; 3875 } 3876 3877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 Inst.addOperand(MCOperand::createImm(imm)); 3880 3881 return S; 3882} 3883 3884 3885static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3886 uint64_t Address, const void *Decoder) { 3887 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3888 3889 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3890 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3891 Inst.addOperand(MCOperand::createImm(imm)); 3892 3893 return MCDisassembler::Success; 3894} 3895 3896static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3897 uint64_t Address, const void *Decoder) { 3898 DecodeStatus S = MCDisassembler::Success; 3899 3900 if (Inst.getOpcode() == ARM::tADDrSP) { 3901 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3902 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3903 3904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3905 return MCDisassembler::Fail; 3906 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3907 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3908 return MCDisassembler::Fail; 3909 } else if (Inst.getOpcode() == ARM::tADDspr) { 3910 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3911 3912 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3913 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3915 return MCDisassembler::Fail; 3916 } 3917 3918 return S; 3919} 3920 3921static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3922 uint64_t Address, const void *Decoder) { 3923 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3924 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3925 3926 Inst.addOperand(MCOperand::createImm(imod)); 3927 Inst.addOperand(MCOperand::createImm(flags)); 3928 3929 return MCDisassembler::Success; 3930} 3931 3932static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3933 uint64_t Address, const void *Decoder) { 3934 DecodeStatus S = MCDisassembler::Success; 3935 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3936 unsigned add = fieldFromInstruction(Insn, 4, 1); 3937 3938 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3939 return MCDisassembler::Fail; 3940 Inst.addOperand(MCOperand::createImm(add)); 3941 3942 return S; 3943} 3944 3945static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3946 uint64_t Address, const void *Decoder) { 3947 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3948 // Note only one trailing zero not two. Also the J1 and J2 values are from 3949 // the encoded instruction. So here change to I1 and I2 values via: 3950 // I1 = NOT(J1 EOR S); 3951 // I2 = NOT(J2 EOR S); 3952 // and build the imm32 with two trailing zeros as documented: 3953 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3954 unsigned S = (Val >> 23) & 1; 3955 unsigned J1 = (Val >> 22) & 1; 3956 unsigned J2 = (Val >> 21) & 1; 3957 unsigned I1 = !(J1 ^ S); 3958 unsigned I2 = !(J2 ^ S); 3959 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3960 int imm32 = SignExtend32<25>(tmp << 1); 3961 3962 if (!tryAddingSymbolicOperand(Address, 3963 (Address & ~2u) + imm32 + 4, 3964 true, 4, Inst, Decoder)) 3965 Inst.addOperand(MCOperand::createImm(imm32)); 3966 return MCDisassembler::Success; 3967} 3968 3969static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3970 uint64_t Address, const void *Decoder) { 3971 if (Val == 0xA || Val == 0xB) 3972 return MCDisassembler::Fail; 3973 3974 const FeatureBitset &featureBits = 3975 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3976 3977 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 3978 return MCDisassembler::Fail; 3979 3980 Inst.addOperand(MCOperand::createImm(Val)); 3981 return MCDisassembler::Success; 3982} 3983 3984static DecodeStatus 3985DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3986 uint64_t Address, const void *Decoder) { 3987 DecodeStatus S = MCDisassembler::Success; 3988 3989 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3990 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3991 3992 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3994 return MCDisassembler::Fail; 3995 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3996 return MCDisassembler::Fail; 3997 return S; 3998} 3999 4000static DecodeStatus 4001DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4002 uint64_t Address, const void *Decoder) { 4003 DecodeStatus S = MCDisassembler::Success; 4004 4005 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4006 if (pred == 0xE || pred == 0xF) { 4007 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4008 switch (opc) { 4009 default: 4010 return MCDisassembler::Fail; 4011 case 0xf3bf8f4: 4012 Inst.setOpcode(ARM::t2DSB); 4013 break; 4014 case 0xf3bf8f5: 4015 Inst.setOpcode(ARM::t2DMB); 4016 break; 4017 case 0xf3bf8f6: 4018 Inst.setOpcode(ARM::t2ISB); 4019 break; 4020 } 4021 4022 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4023 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4024 } 4025 4026 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4027 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4028 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4029 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4030 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4031 4032 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4033 return MCDisassembler::Fail; 4034 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4035 return MCDisassembler::Fail; 4036 4037 return S; 4038} 4039 4040// Decode a shifted immediate operand. These basically consist 4041// of an 8-bit value, and a 4-bit directive that specifies either 4042// a splat operation or a rotation. 4043static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4044 uint64_t Address, const void *Decoder) { 4045 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4046 if (ctrl == 0) { 4047 unsigned byte = fieldFromInstruction(Val, 8, 2); 4048 unsigned imm = fieldFromInstruction(Val, 0, 8); 4049 switch (byte) { 4050 case 0: 4051 Inst.addOperand(MCOperand::createImm(imm)); 4052 break; 4053 case 1: 4054 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4055 break; 4056 case 2: 4057 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4058 break; 4059 case 3: 4060 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4061 (imm << 8) | imm)); 4062 break; 4063 } 4064 } else { 4065 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4066 unsigned rot = fieldFromInstruction(Val, 7, 5); 4067 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4068 Inst.addOperand(MCOperand::createImm(imm)); 4069 } 4070 4071 return MCDisassembler::Success; 4072} 4073 4074static DecodeStatus 4075DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4076 uint64_t Address, const void *Decoder){ 4077 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4078 true, 2, Inst, Decoder)) 4079 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4080 return MCDisassembler::Success; 4081} 4082 4083static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4084 uint64_t Address, const void *Decoder){ 4085 // Val is passed in as S:J1:J2:imm10:imm11 4086 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4087 // the encoded instruction. So here change to I1 and I2 values via: 4088 // I1 = NOT(J1 EOR S); 4089 // I2 = NOT(J2 EOR S); 4090 // and build the imm32 with one trailing zero as documented: 4091 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4092 unsigned S = (Val >> 23) & 1; 4093 unsigned J1 = (Val >> 22) & 1; 4094 unsigned J2 = (Val >> 21) & 1; 4095 unsigned I1 = !(J1 ^ S); 4096 unsigned I2 = !(J2 ^ S); 4097 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4098 int imm32 = SignExtend32<25>(tmp << 1); 4099 4100 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4101 true, 4, Inst, Decoder)) 4102 Inst.addOperand(MCOperand::createImm(imm32)); 4103 return MCDisassembler::Success; 4104} 4105 4106static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4107 uint64_t Address, const void *Decoder) { 4108 if (Val & ~0xf) 4109 return MCDisassembler::Fail; 4110 4111 Inst.addOperand(MCOperand::createImm(Val)); 4112 return MCDisassembler::Success; 4113} 4114 4115static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4116 uint64_t Address, const void *Decoder) { 4117 if (Val & ~0xf) 4118 return MCDisassembler::Fail; 4119 4120 Inst.addOperand(MCOperand::createImm(Val)); 4121 return MCDisassembler::Success; 4122} 4123 4124static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4125 uint64_t Address, const void *Decoder) { 4126 DecodeStatus S = MCDisassembler::Success; 4127 const FeatureBitset &FeatureBits = 4128 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4129 4130 if (FeatureBits[ARM::FeatureMClass]) { 4131 unsigned ValLow = Val & 0xff; 4132 4133 // Validate the SYSm value first. 4134 switch (ValLow) { 4135 case 0: // apsr 4136 case 1: // iapsr 4137 case 2: // eapsr 4138 case 3: // xpsr 4139 case 5: // ipsr 4140 case 6: // epsr 4141 case 7: // iepsr 4142 case 8: // msp 4143 case 9: // psp 4144 case 16: // primask 4145 case 20: // control 4146 break; 4147 case 17: // basepri 4148 case 18: // basepri_max 4149 case 19: // faultmask 4150 if (!(FeatureBits[ARM::HasV7Ops])) 4151 // Values basepri, basepri_max and faultmask are only valid for v7m. 4152 return MCDisassembler::Fail; 4153 break; 4154 case 0x8a: // msplim_ns 4155 case 0x8b: // psplim_ns 4156 case 0x91: // basepri_ns 4157 case 0x92: // basepri_max_ns 4158 case 0x93: // faultmask_ns 4159 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4160 return MCDisassembler::Fail; 4161 LLVM_FALLTHROUGH; 4162 case 10: // msplim 4163 case 11: // psplim 4164 case 0x88: // msp_ns 4165 case 0x89: // psp_ns 4166 case 0x90: // primask_ns 4167 case 0x94: // control_ns 4168 case 0x98: // sp_ns 4169 if (!(FeatureBits[ARM::Feature8MSecExt])) 4170 return MCDisassembler::Fail; 4171 break; 4172 default: 4173 return MCDisassembler::Fail; 4174 } 4175 4176 if (Inst.getOpcode() == ARM::t2MSR_M) { 4177 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4178 if (!(FeatureBits[ARM::HasV7Ops])) { 4179 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4180 // unpredictable. 4181 if (Mask != 2) 4182 S = MCDisassembler::SoftFail; 4183 } 4184 else { 4185 // The ARMv7-M architecture stores an additional 2-bit mask value in 4186 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4187 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4188 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4189 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4190 // only if the processor includes the DSP extension. 4191 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4192 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4193 S = MCDisassembler::SoftFail; 4194 } 4195 } 4196 } else { 4197 // A/R class 4198 if (Val == 0) 4199 return MCDisassembler::Fail; 4200 } 4201 Inst.addOperand(MCOperand::createImm(Val)); 4202 return S; 4203} 4204 4205static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4206 uint64_t Address, const void *Decoder) { 4207 4208 unsigned R = fieldFromInstruction(Val, 5, 1); 4209 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4210 4211 // The table of encodings for these banked registers comes from B9.2.3 of the 4212 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4213 // neater. So by fiat, these values are UNPREDICTABLE: 4214 if (!R) { 4215 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 4216 SysM == 0x1a || SysM == 0x1b) 4217 return MCDisassembler::SoftFail; 4218 } else { 4219 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 4220 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 4221 return MCDisassembler::SoftFail; 4222 } 4223 4224 Inst.addOperand(MCOperand::createImm(Val)); 4225 return MCDisassembler::Success; 4226} 4227 4228static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4229 uint64_t Address, const void *Decoder) { 4230 DecodeStatus S = MCDisassembler::Success; 4231 4232 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4233 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4234 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4235 4236 if (Rn == 0xF) 4237 S = MCDisassembler::SoftFail; 4238 4239 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4240 return MCDisassembler::Fail; 4241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 4246 return S; 4247} 4248 4249static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4250 uint64_t Address, const void *Decoder){ 4251 DecodeStatus S = MCDisassembler::Success; 4252 4253 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4254 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4255 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4256 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4257 4258 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4259 return MCDisassembler::Fail; 4260 4261 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4262 S = MCDisassembler::SoftFail; 4263 4264 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4265 return MCDisassembler::Fail; 4266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4267 return MCDisassembler::Fail; 4268 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 4271 return S; 4272} 4273 4274static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4275 uint64_t Address, const void *Decoder) { 4276 DecodeStatus S = MCDisassembler::Success; 4277 4278 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4279 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4280 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4281 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4282 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4283 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4284 4285 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4286 4287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4288 return MCDisassembler::Fail; 4289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4290 return MCDisassembler::Fail; 4291 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4292 return MCDisassembler::Fail; 4293 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4294 return MCDisassembler::Fail; 4295 4296 return S; 4297} 4298 4299static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4300 uint64_t Address, const void *Decoder) { 4301 DecodeStatus S = MCDisassembler::Success; 4302 4303 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4304 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4305 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4306 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4307 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4308 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4309 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4310 4311 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4312 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4313 4314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4315 return MCDisassembler::Fail; 4316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4317 return MCDisassembler::Fail; 4318 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4319 return MCDisassembler::Fail; 4320 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4321 return MCDisassembler::Fail; 4322 4323 return S; 4324} 4325 4326 4327static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4328 uint64_t Address, const void *Decoder) { 4329 DecodeStatus S = MCDisassembler::Success; 4330 4331 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4332 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4333 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4334 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4335 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4336 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4337 4338 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4339 4340 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4341 return MCDisassembler::Fail; 4342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4345 return MCDisassembler::Fail; 4346 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4347 return MCDisassembler::Fail; 4348 4349 return S; 4350} 4351 4352static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4353 uint64_t Address, const void *Decoder) { 4354 DecodeStatus S = MCDisassembler::Success; 4355 4356 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4357 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4358 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4359 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4360 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4361 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4362 4363 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4364 4365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4368 return MCDisassembler::Fail; 4369 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4370 return MCDisassembler::Fail; 4371 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 4374 return S; 4375} 4376 4377static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4378 uint64_t Address, const void *Decoder) { 4379 DecodeStatus S = MCDisassembler::Success; 4380 4381 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4382 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4383 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4384 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4385 unsigned size = fieldFromInstruction(Insn, 10, 2); 4386 4387 unsigned align = 0; 4388 unsigned index = 0; 4389 switch (size) { 4390 default: 4391 return MCDisassembler::Fail; 4392 case 0: 4393 if (fieldFromInstruction(Insn, 4, 1)) 4394 return MCDisassembler::Fail; // UNDEFINED 4395 index = fieldFromInstruction(Insn, 5, 3); 4396 break; 4397 case 1: 4398 if (fieldFromInstruction(Insn, 5, 1)) 4399 return MCDisassembler::Fail; // UNDEFINED 4400 index = fieldFromInstruction(Insn, 6, 2); 4401 if (fieldFromInstruction(Insn, 4, 1)) 4402 align = 2; 4403 break; 4404 case 2: 4405 if (fieldFromInstruction(Insn, 6, 1)) 4406 return MCDisassembler::Fail; // UNDEFINED 4407 index = fieldFromInstruction(Insn, 7, 1); 4408 4409 switch (fieldFromInstruction(Insn, 4, 2)) { 4410 case 0 : 4411 align = 0; break; 4412 case 3: 4413 align = 4; break; 4414 default: 4415 return MCDisassembler::Fail; 4416 } 4417 break; 4418 } 4419 4420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4421 return MCDisassembler::Fail; 4422 if (Rm != 0xF) { // Writeback 4423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4424 return MCDisassembler::Fail; 4425 } 4426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 Inst.addOperand(MCOperand::createImm(align)); 4429 if (Rm != 0xF) { 4430 if (Rm != 0xD) { 4431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4432 return MCDisassembler::Fail; 4433 } else 4434 Inst.addOperand(MCOperand::createReg(0)); 4435 } 4436 4437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4438 return MCDisassembler::Fail; 4439 Inst.addOperand(MCOperand::createImm(index)); 4440 4441 return S; 4442} 4443 4444static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4445 uint64_t Address, const void *Decoder) { 4446 DecodeStatus S = MCDisassembler::Success; 4447 4448 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4449 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4450 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4451 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4452 unsigned size = fieldFromInstruction(Insn, 10, 2); 4453 4454 unsigned align = 0; 4455 unsigned index = 0; 4456 switch (size) { 4457 default: 4458 return MCDisassembler::Fail; 4459 case 0: 4460 if (fieldFromInstruction(Insn, 4, 1)) 4461 return MCDisassembler::Fail; // UNDEFINED 4462 index = fieldFromInstruction(Insn, 5, 3); 4463 break; 4464 case 1: 4465 if (fieldFromInstruction(Insn, 5, 1)) 4466 return MCDisassembler::Fail; // UNDEFINED 4467 index = fieldFromInstruction(Insn, 6, 2); 4468 if (fieldFromInstruction(Insn, 4, 1)) 4469 align = 2; 4470 break; 4471 case 2: 4472 if (fieldFromInstruction(Insn, 6, 1)) 4473 return MCDisassembler::Fail; // UNDEFINED 4474 index = fieldFromInstruction(Insn, 7, 1); 4475 4476 switch (fieldFromInstruction(Insn, 4, 2)) { 4477 case 0: 4478 align = 0; break; 4479 case 3: 4480 align = 4; break; 4481 default: 4482 return MCDisassembler::Fail; 4483 } 4484 break; 4485 } 4486 4487 if (Rm != 0xF) { // Writeback 4488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4489 return MCDisassembler::Fail; 4490 } 4491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4492 return MCDisassembler::Fail; 4493 Inst.addOperand(MCOperand::createImm(align)); 4494 if (Rm != 0xF) { 4495 if (Rm != 0xD) { 4496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4497 return MCDisassembler::Fail; 4498 } else 4499 Inst.addOperand(MCOperand::createReg(0)); 4500 } 4501 4502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4503 return MCDisassembler::Fail; 4504 Inst.addOperand(MCOperand::createImm(index)); 4505 4506 return S; 4507} 4508 4509 4510static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4511 uint64_t Address, const void *Decoder) { 4512 DecodeStatus S = MCDisassembler::Success; 4513 4514 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4515 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4516 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4517 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4518 unsigned size = fieldFromInstruction(Insn, 10, 2); 4519 4520 unsigned align = 0; 4521 unsigned index = 0; 4522 unsigned inc = 1; 4523 switch (size) { 4524 default: 4525 return MCDisassembler::Fail; 4526 case 0: 4527 index = fieldFromInstruction(Insn, 5, 3); 4528 if (fieldFromInstruction(Insn, 4, 1)) 4529 align = 2; 4530 break; 4531 case 1: 4532 index = fieldFromInstruction(Insn, 6, 2); 4533 if (fieldFromInstruction(Insn, 4, 1)) 4534 align = 4; 4535 if (fieldFromInstruction(Insn, 5, 1)) 4536 inc = 2; 4537 break; 4538 case 2: 4539 if (fieldFromInstruction(Insn, 5, 1)) 4540 return MCDisassembler::Fail; // UNDEFINED 4541 index = fieldFromInstruction(Insn, 7, 1); 4542 if (fieldFromInstruction(Insn, 4, 1) != 0) 4543 align = 8; 4544 if (fieldFromInstruction(Insn, 6, 1)) 4545 inc = 2; 4546 break; 4547 } 4548 4549 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4550 return MCDisassembler::Fail; 4551 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4552 return MCDisassembler::Fail; 4553 if (Rm != 0xF) { // Writeback 4554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4555 return MCDisassembler::Fail; 4556 } 4557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4558 return MCDisassembler::Fail; 4559 Inst.addOperand(MCOperand::createImm(align)); 4560 if (Rm != 0xF) { 4561 if (Rm != 0xD) { 4562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4563 return MCDisassembler::Fail; 4564 } else 4565 Inst.addOperand(MCOperand::createReg(0)); 4566 } 4567 4568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4569 return MCDisassembler::Fail; 4570 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4571 return MCDisassembler::Fail; 4572 Inst.addOperand(MCOperand::createImm(index)); 4573 4574 return S; 4575} 4576 4577static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4578 uint64_t Address, const void *Decoder) { 4579 DecodeStatus S = MCDisassembler::Success; 4580 4581 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4582 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4583 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4584 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4585 unsigned size = fieldFromInstruction(Insn, 10, 2); 4586 4587 unsigned align = 0; 4588 unsigned index = 0; 4589 unsigned inc = 1; 4590 switch (size) { 4591 default: 4592 return MCDisassembler::Fail; 4593 case 0: 4594 index = fieldFromInstruction(Insn, 5, 3); 4595 if (fieldFromInstruction(Insn, 4, 1)) 4596 align = 2; 4597 break; 4598 case 1: 4599 index = fieldFromInstruction(Insn, 6, 2); 4600 if (fieldFromInstruction(Insn, 4, 1)) 4601 align = 4; 4602 if (fieldFromInstruction(Insn, 5, 1)) 4603 inc = 2; 4604 break; 4605 case 2: 4606 if (fieldFromInstruction(Insn, 5, 1)) 4607 return MCDisassembler::Fail; // UNDEFINED 4608 index = fieldFromInstruction(Insn, 7, 1); 4609 if (fieldFromInstruction(Insn, 4, 1) != 0) 4610 align = 8; 4611 if (fieldFromInstruction(Insn, 6, 1)) 4612 inc = 2; 4613 break; 4614 } 4615 4616 if (Rm != 0xF) { // Writeback 4617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4618 return MCDisassembler::Fail; 4619 } 4620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4621 return MCDisassembler::Fail; 4622 Inst.addOperand(MCOperand::createImm(align)); 4623 if (Rm != 0xF) { 4624 if (Rm != 0xD) { 4625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4626 return MCDisassembler::Fail; 4627 } else 4628 Inst.addOperand(MCOperand::createReg(0)); 4629 } 4630 4631 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4632 return MCDisassembler::Fail; 4633 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4634 return MCDisassembler::Fail; 4635 Inst.addOperand(MCOperand::createImm(index)); 4636 4637 return S; 4638} 4639 4640 4641static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4642 uint64_t Address, const void *Decoder) { 4643 DecodeStatus S = MCDisassembler::Success; 4644 4645 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4646 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4647 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4648 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4649 unsigned size = fieldFromInstruction(Insn, 10, 2); 4650 4651 unsigned align = 0; 4652 unsigned index = 0; 4653 unsigned inc = 1; 4654 switch (size) { 4655 default: 4656 return MCDisassembler::Fail; 4657 case 0: 4658 if (fieldFromInstruction(Insn, 4, 1)) 4659 return MCDisassembler::Fail; // UNDEFINED 4660 index = fieldFromInstruction(Insn, 5, 3); 4661 break; 4662 case 1: 4663 if (fieldFromInstruction(Insn, 4, 1)) 4664 return MCDisassembler::Fail; // UNDEFINED 4665 index = fieldFromInstruction(Insn, 6, 2); 4666 if (fieldFromInstruction(Insn, 5, 1)) 4667 inc = 2; 4668 break; 4669 case 2: 4670 if (fieldFromInstruction(Insn, 4, 2)) 4671 return MCDisassembler::Fail; // UNDEFINED 4672 index = fieldFromInstruction(Insn, 7, 1); 4673 if (fieldFromInstruction(Insn, 6, 1)) 4674 inc = 2; 4675 break; 4676 } 4677 4678 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4683 return MCDisassembler::Fail; 4684 4685 if (Rm != 0xF) { // Writeback 4686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4687 return MCDisassembler::Fail; 4688 } 4689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4690 return MCDisassembler::Fail; 4691 Inst.addOperand(MCOperand::createImm(align)); 4692 if (Rm != 0xF) { 4693 if (Rm != 0xD) { 4694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4695 return MCDisassembler::Fail; 4696 } else 4697 Inst.addOperand(MCOperand::createReg(0)); 4698 } 4699 4700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4701 return MCDisassembler::Fail; 4702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4703 return MCDisassembler::Fail; 4704 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4705 return MCDisassembler::Fail; 4706 Inst.addOperand(MCOperand::createImm(index)); 4707 4708 return S; 4709} 4710 4711static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4712 uint64_t Address, const void *Decoder) { 4713 DecodeStatus S = MCDisassembler::Success; 4714 4715 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4716 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4717 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4718 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4719 unsigned size = fieldFromInstruction(Insn, 10, 2); 4720 4721 unsigned align = 0; 4722 unsigned index = 0; 4723 unsigned inc = 1; 4724 switch (size) { 4725 default: 4726 return MCDisassembler::Fail; 4727 case 0: 4728 if (fieldFromInstruction(Insn, 4, 1)) 4729 return MCDisassembler::Fail; // UNDEFINED 4730 index = fieldFromInstruction(Insn, 5, 3); 4731 break; 4732 case 1: 4733 if (fieldFromInstruction(Insn, 4, 1)) 4734 return MCDisassembler::Fail; // UNDEFINED 4735 index = fieldFromInstruction(Insn, 6, 2); 4736 if (fieldFromInstruction(Insn, 5, 1)) 4737 inc = 2; 4738 break; 4739 case 2: 4740 if (fieldFromInstruction(Insn, 4, 2)) 4741 return MCDisassembler::Fail; // UNDEFINED 4742 index = fieldFromInstruction(Insn, 7, 1); 4743 if (fieldFromInstruction(Insn, 6, 1)) 4744 inc = 2; 4745 break; 4746 } 4747 4748 if (Rm != 0xF) { // Writeback 4749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4750 return MCDisassembler::Fail; 4751 } 4752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4753 return MCDisassembler::Fail; 4754 Inst.addOperand(MCOperand::createImm(align)); 4755 if (Rm != 0xF) { 4756 if (Rm != 0xD) { 4757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4758 return MCDisassembler::Fail; 4759 } else 4760 Inst.addOperand(MCOperand::createReg(0)); 4761 } 4762 4763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4764 return MCDisassembler::Fail; 4765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4766 return MCDisassembler::Fail; 4767 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4768 return MCDisassembler::Fail; 4769 Inst.addOperand(MCOperand::createImm(index)); 4770 4771 return S; 4772} 4773 4774 4775static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4776 uint64_t Address, const void *Decoder) { 4777 DecodeStatus S = MCDisassembler::Success; 4778 4779 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4780 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4781 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4782 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4783 unsigned size = fieldFromInstruction(Insn, 10, 2); 4784 4785 unsigned align = 0; 4786 unsigned index = 0; 4787 unsigned inc = 1; 4788 switch (size) { 4789 default: 4790 return MCDisassembler::Fail; 4791 case 0: 4792 if (fieldFromInstruction(Insn, 4, 1)) 4793 align = 4; 4794 index = fieldFromInstruction(Insn, 5, 3); 4795 break; 4796 case 1: 4797 if (fieldFromInstruction(Insn, 4, 1)) 4798 align = 8; 4799 index = fieldFromInstruction(Insn, 6, 2); 4800 if (fieldFromInstruction(Insn, 5, 1)) 4801 inc = 2; 4802 break; 4803 case 2: 4804 switch (fieldFromInstruction(Insn, 4, 2)) { 4805 case 0: 4806 align = 0; break; 4807 case 3: 4808 return MCDisassembler::Fail; 4809 default: 4810 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4811 } 4812 4813 index = fieldFromInstruction(Insn, 7, 1); 4814 if (fieldFromInstruction(Insn, 6, 1)) 4815 inc = 2; 4816 break; 4817 } 4818 4819 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4820 return MCDisassembler::Fail; 4821 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4822 return MCDisassembler::Fail; 4823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4824 return MCDisassembler::Fail; 4825 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4826 return MCDisassembler::Fail; 4827 4828 if (Rm != 0xF) { // Writeback 4829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4830 return MCDisassembler::Fail; 4831 } 4832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4833 return MCDisassembler::Fail; 4834 Inst.addOperand(MCOperand::createImm(align)); 4835 if (Rm != 0xF) { 4836 if (Rm != 0xD) { 4837 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4838 return MCDisassembler::Fail; 4839 } else 4840 Inst.addOperand(MCOperand::createReg(0)); 4841 } 4842 4843 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4844 return MCDisassembler::Fail; 4845 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4846 return MCDisassembler::Fail; 4847 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4848 return MCDisassembler::Fail; 4849 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4850 return MCDisassembler::Fail; 4851 Inst.addOperand(MCOperand::createImm(index)); 4852 4853 return S; 4854} 4855 4856static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4857 uint64_t Address, const void *Decoder) { 4858 DecodeStatus S = MCDisassembler::Success; 4859 4860 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4861 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4862 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4863 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4864 unsigned size = fieldFromInstruction(Insn, 10, 2); 4865 4866 unsigned align = 0; 4867 unsigned index = 0; 4868 unsigned inc = 1; 4869 switch (size) { 4870 default: 4871 return MCDisassembler::Fail; 4872 case 0: 4873 if (fieldFromInstruction(Insn, 4, 1)) 4874 align = 4; 4875 index = fieldFromInstruction(Insn, 5, 3); 4876 break; 4877 case 1: 4878 if (fieldFromInstruction(Insn, 4, 1)) 4879 align = 8; 4880 index = fieldFromInstruction(Insn, 6, 2); 4881 if (fieldFromInstruction(Insn, 5, 1)) 4882 inc = 2; 4883 break; 4884 case 2: 4885 switch (fieldFromInstruction(Insn, 4, 2)) { 4886 case 0: 4887 align = 0; break; 4888 case 3: 4889 return MCDisassembler::Fail; 4890 default: 4891 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4892 } 4893 4894 index = fieldFromInstruction(Insn, 7, 1); 4895 if (fieldFromInstruction(Insn, 6, 1)) 4896 inc = 2; 4897 break; 4898 } 4899 4900 if (Rm != 0xF) { // Writeback 4901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4902 return MCDisassembler::Fail; 4903 } 4904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4905 return MCDisassembler::Fail; 4906 Inst.addOperand(MCOperand::createImm(align)); 4907 if (Rm != 0xF) { 4908 if (Rm != 0xD) { 4909 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4910 return MCDisassembler::Fail; 4911 } else 4912 Inst.addOperand(MCOperand::createReg(0)); 4913 } 4914 4915 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4916 return MCDisassembler::Fail; 4917 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4918 return MCDisassembler::Fail; 4919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4920 return MCDisassembler::Fail; 4921 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4922 return MCDisassembler::Fail; 4923 Inst.addOperand(MCOperand::createImm(index)); 4924 4925 return S; 4926} 4927 4928static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4929 uint64_t Address, const void *Decoder) { 4930 DecodeStatus S = MCDisassembler::Success; 4931 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4932 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4933 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4934 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4935 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4936 4937 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4938 S = MCDisassembler::SoftFail; 4939 4940 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4941 return MCDisassembler::Fail; 4942 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4943 return MCDisassembler::Fail; 4944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4945 return MCDisassembler::Fail; 4946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4947 return MCDisassembler::Fail; 4948 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4949 return MCDisassembler::Fail; 4950 4951 return S; 4952} 4953 4954static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4955 uint64_t Address, const void *Decoder) { 4956 DecodeStatus S = MCDisassembler::Success; 4957 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4958 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4959 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4960 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4961 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4962 4963 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4964 S = MCDisassembler::SoftFail; 4965 4966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4967 return MCDisassembler::Fail; 4968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4969 return MCDisassembler::Fail; 4970 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4971 return MCDisassembler::Fail; 4972 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4973 return MCDisassembler::Fail; 4974 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4975 return MCDisassembler::Fail; 4976 4977 return S; 4978} 4979 4980static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4981 uint64_t Address, const void *Decoder) { 4982 DecodeStatus S = MCDisassembler::Success; 4983 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4984 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4985 4986 if (pred == 0xF) { 4987 pred = 0xE; 4988 S = MCDisassembler::SoftFail; 4989 } 4990 4991 if (mask == 0x0) 4992 return MCDisassembler::Fail; 4993 4994 Inst.addOperand(MCOperand::createImm(pred)); 4995 Inst.addOperand(MCOperand::createImm(mask)); 4996 return S; 4997} 4998 4999static DecodeStatus 5000DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5001 uint64_t Address, const void *Decoder) { 5002 DecodeStatus S = MCDisassembler::Success; 5003 5004 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5005 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5006 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5007 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5008 unsigned W = fieldFromInstruction(Insn, 21, 1); 5009 unsigned U = fieldFromInstruction(Insn, 23, 1); 5010 unsigned P = fieldFromInstruction(Insn, 24, 1); 5011 bool writeback = (W == 1) | (P == 0); 5012 5013 addr |= (U << 8) | (Rn << 9); 5014 5015 if (writeback && (Rn == Rt || Rn == Rt2)) 5016 Check(S, MCDisassembler::SoftFail); 5017 if (Rt == Rt2) 5018 Check(S, MCDisassembler::SoftFail); 5019 5020 // Rt 5021 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5022 return MCDisassembler::Fail; 5023 // Rt2 5024 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5025 return MCDisassembler::Fail; 5026 // Writeback operand 5027 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5028 return MCDisassembler::Fail; 5029 // addr 5030 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5031 return MCDisassembler::Fail; 5032 5033 return S; 5034} 5035 5036static DecodeStatus 5037DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5038 uint64_t Address, const void *Decoder) { 5039 DecodeStatus S = MCDisassembler::Success; 5040 5041 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5042 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5043 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5044 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5045 unsigned W = fieldFromInstruction(Insn, 21, 1); 5046 unsigned U = fieldFromInstruction(Insn, 23, 1); 5047 unsigned P = fieldFromInstruction(Insn, 24, 1); 5048 bool writeback = (W == 1) | (P == 0); 5049 5050 addr |= (U << 8) | (Rn << 9); 5051 5052 if (writeback && (Rn == Rt || Rn == Rt2)) 5053 Check(S, MCDisassembler::SoftFail); 5054 5055 // Writeback operand 5056 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5057 return MCDisassembler::Fail; 5058 // Rt 5059 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5060 return MCDisassembler::Fail; 5061 // Rt2 5062 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5063 return MCDisassembler::Fail; 5064 // addr 5065 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5066 return MCDisassembler::Fail; 5067 5068 return S; 5069} 5070 5071static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5072 uint64_t Address, const void *Decoder) { 5073 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5074 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5075 if (sign1 != sign2) return MCDisassembler::Fail; 5076 5077 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5078 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5079 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5080 Val |= sign1 << 12; 5081 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5082 5083 return MCDisassembler::Success; 5084} 5085 5086static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5087 uint64_t Address, 5088 const void *Decoder) { 5089 DecodeStatus S = MCDisassembler::Success; 5090 5091 // Shift of "asr #32" is not allowed in Thumb2 mode. 5092 if (Val == 0x20) S = MCDisassembler::Fail; 5093 Inst.addOperand(MCOperand::createImm(Val)); 5094 return S; 5095} 5096 5097static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5098 uint64_t Address, const void *Decoder) { 5099 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5100 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5101 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5102 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5103 5104 if (pred == 0xF) 5105 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5106 5107 DecodeStatus S = MCDisassembler::Success; 5108 5109 if (Rt == Rn || Rn == Rt2) 5110 S = MCDisassembler::SoftFail; 5111 5112 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5113 return MCDisassembler::Fail; 5114 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5115 return MCDisassembler::Fail; 5116 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5117 return MCDisassembler::Fail; 5118 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5119 return MCDisassembler::Fail; 5120 5121 return S; 5122} 5123 5124static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5125 uint64_t Address, const void *Decoder) { 5126 const FeatureBitset &featureBits = 5127 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5128 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5129 5130 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5131 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5132 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5133 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5134 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5135 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5136 unsigned op = fieldFromInstruction(Insn, 5, 1); 5137 5138 DecodeStatus S = MCDisassembler::Success; 5139 5140 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5141 if (!(imm & 0x38)) { 5142 if (cmode == 0xF) { 5143 if (op == 1) return MCDisassembler::Fail; 5144 Inst.setOpcode(ARM::VMOVv2f32); 5145 } 5146 if (hasFullFP16) { 5147 if (cmode == 0xE) { 5148 if (op == 1) { 5149 Inst.setOpcode(ARM::VMOVv1i64); 5150 } else { 5151 Inst.setOpcode(ARM::VMOVv8i8); 5152 } 5153 } 5154 if (cmode == 0xD) { 5155 if (op == 1) { 5156 Inst.setOpcode(ARM::VMVNv2i32); 5157 } else { 5158 Inst.setOpcode(ARM::VMOVv2i32); 5159 } 5160 } 5161 if (cmode == 0xC) { 5162 if (op == 1) { 5163 Inst.setOpcode(ARM::VMVNv2i32); 5164 } else { 5165 Inst.setOpcode(ARM::VMOVv2i32); 5166 } 5167 } 5168 } 5169 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5170 } 5171 5172 if (!(imm & 0x20)) return MCDisassembler::Fail; 5173 5174 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5175 return MCDisassembler::Fail; 5176 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5177 return MCDisassembler::Fail; 5178 Inst.addOperand(MCOperand::createImm(64 - imm)); 5179 5180 return S; 5181} 5182 5183static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5184 uint64_t Address, const void *Decoder) { 5185 const FeatureBitset &featureBits = 5186 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5187 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5188 5189 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5190 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5191 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5192 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5193 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5194 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5195 unsigned op = fieldFromInstruction(Insn, 5, 1); 5196 5197 DecodeStatus S = MCDisassembler::Success; 5198 5199 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5200 if (!(imm & 0x38)) { 5201 if (cmode == 0xF) { 5202 if (op == 1) return MCDisassembler::Fail; 5203 Inst.setOpcode(ARM::VMOVv4f32); 5204 } 5205 if (hasFullFP16) { 5206 if (cmode == 0xE) { 5207 if (op == 1) { 5208 Inst.setOpcode(ARM::VMOVv2i64); 5209 } else { 5210 Inst.setOpcode(ARM::VMOVv16i8); 5211 } 5212 } 5213 if (cmode == 0xD) { 5214 if (op == 1) { 5215 Inst.setOpcode(ARM::VMVNv4i32); 5216 } else { 5217 Inst.setOpcode(ARM::VMOVv4i32); 5218 } 5219 } 5220 if (cmode == 0xC) { 5221 if (op == 1) { 5222 Inst.setOpcode(ARM::VMVNv4i32); 5223 } else { 5224 Inst.setOpcode(ARM::VMOVv4i32); 5225 } 5226 } 5227 } 5228 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5229 } 5230 5231 if (!(imm & 0x20)) return MCDisassembler::Fail; 5232 5233 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5234 return MCDisassembler::Fail; 5235 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5236 return MCDisassembler::Fail; 5237 Inst.addOperand(MCOperand::createImm(64 - imm)); 5238 5239 return S; 5240} 5241 5242static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5243 uint64_t Address, const void *Decoder) { 5244 DecodeStatus S = MCDisassembler::Success; 5245 5246 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5247 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5248 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5249 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5250 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5251 5252 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5253 S = MCDisassembler::SoftFail; 5254 5255 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5256 return MCDisassembler::Fail; 5257 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5258 return MCDisassembler::Fail; 5259 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5260 return MCDisassembler::Fail; 5261 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5262 return MCDisassembler::Fail; 5263 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5264 return MCDisassembler::Fail; 5265 5266 return S; 5267} 5268 5269static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val, 5270 uint64_t Address, const void *Decoder) { 5271 5272 DecodeStatus S = MCDisassembler::Success; 5273 5274 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5275 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5276 unsigned cop = fieldFromInstruction(Val, 8, 4); 5277 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5278 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5279 5280 if ((cop & ~0x1) == 0xa) 5281 return MCDisassembler::Fail; 5282 5283 if (Rt == Rt2) 5284 S = MCDisassembler::SoftFail; 5285 5286 // We have to check if the instruction is MRRC2 5287 // or MCRR2 when constructing the operands for 5288 // Inst. Reason is because MRRC2 stores to two 5289 // registers so it's tablegen desc has has two 5290 // outputs whereas MCRR doesn't store to any 5291 // registers so all of it's operands are listed 5292 // as inputs, therefore the operand order for 5293 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5294 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5295 5296 if (Inst.getOpcode() == ARM::MRRC2) { 5297 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5298 return MCDisassembler::Fail; 5299 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5300 return MCDisassembler::Fail; 5301 } 5302 Inst.addOperand(MCOperand::createImm(cop)); 5303 Inst.addOperand(MCOperand::createImm(opc1)); 5304 if (Inst.getOpcode() == ARM::MCRR2) { 5305 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5306 return MCDisassembler::Fail; 5307 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5308 return MCDisassembler::Fail; 5309 } 5310 Inst.addOperand(MCOperand::createImm(CRm)); 5311 5312 return S; 5313} 5314