1//===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
12
13#include "llvm/MC/MCRegisterInfo.h"
14
15// Operand Flags
16#define MO_FLAG_CLAMP (1 << 0)
17#define MO_FLAG_NEG   (1 << 1)
18#define MO_FLAG_ABS   (1 << 2)
19#define MO_FLAG_MASK  (1 << 3)
20#define MO_FLAG_PUSH  (1 << 4)
21#define MO_FLAG_NOT_LAST  (1 << 5)
22#define MO_FLAG_LAST  (1 << 6)
23#define NUM_MO_FLAGS 7
24
25/// Helper for getting the operand index for the instruction flags
26/// operand.
27#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
28
29namespace R600_InstFlag {
30  enum TIF {
31    TRANS_ONLY = (1 << 0),
32    TEX = (1 << 1),
33    REDUCTION = (1 << 2),
34    FC = (1 << 3),
35    TRIG = (1 << 4),
36    OP3 = (1 << 5),
37    VECTOR = (1 << 6),
38    //FlagOperand bits 7, 8
39    NATIVE_OPERANDS = (1 << 9),
40    OP1 = (1 << 10),
41    OP2 = (1 << 11),
42    VTX_INST  = (1 << 12),
43    TEX_INST = (1 << 13),
44    ALU_INST = (1 << 14),
45    LDS_1A = (1 << 15),
46    LDS_1A1D = (1 << 16),
47    IS_EXPORT = (1 << 17),
48    LDS_1A2D = (1 << 18)
49  };
50}
51
52#define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
53
54/// Defines for extracting register information from register encoding
55#define HW_REG_MASK 0x1ff
56#define HW_CHAN_SHIFT 9
57
58#define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
59#define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
60
61#define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
62#define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
63
64namespace OpName {
65
66  enum VecOps {
67    UPDATE_EXEC_MASK_X,
68    UPDATE_PREDICATE_X,
69    WRITE_X,
70    OMOD_X,
71    DST_REL_X,
72    CLAMP_X,
73    SRC0_X,
74    SRC0_NEG_X,
75    SRC0_REL_X,
76    SRC0_ABS_X,
77    SRC0_SEL_X,
78    SRC1_X,
79    SRC1_NEG_X,
80    SRC1_REL_X,
81    SRC1_ABS_X,
82    SRC1_SEL_X,
83    PRED_SEL_X,
84    UPDATE_EXEC_MASK_Y,
85    UPDATE_PREDICATE_Y,
86    WRITE_Y,
87    OMOD_Y,
88    DST_REL_Y,
89    CLAMP_Y,
90    SRC0_Y,
91    SRC0_NEG_Y,
92    SRC0_REL_Y,
93    SRC0_ABS_Y,
94    SRC0_SEL_Y,
95    SRC1_Y,
96    SRC1_NEG_Y,
97    SRC1_REL_Y,
98    SRC1_ABS_Y,
99    SRC1_SEL_Y,
100    PRED_SEL_Y,
101    UPDATE_EXEC_MASK_Z,
102    UPDATE_PREDICATE_Z,
103    WRITE_Z,
104    OMOD_Z,
105    DST_REL_Z,
106    CLAMP_Z,
107    SRC0_Z,
108    SRC0_NEG_Z,
109    SRC0_REL_Z,
110    SRC0_ABS_Z,
111    SRC0_SEL_Z,
112    SRC1_Z,
113    SRC1_NEG_Z,
114    SRC1_REL_Z,
115    SRC1_ABS_Z,
116    SRC1_SEL_Z,
117    PRED_SEL_Z,
118    UPDATE_EXEC_MASK_W,
119    UPDATE_PREDICATE_W,
120    WRITE_W,
121    OMOD_W,
122    DST_REL_W,
123    CLAMP_W,
124    SRC0_W,
125    SRC0_NEG_W,
126    SRC0_REL_W,
127    SRC0_ABS_W,
128    SRC0_SEL_W,
129    SRC1_W,
130    SRC1_NEG_W,
131    SRC1_REL_W,
132    SRC1_ABS_W,
133    SRC1_SEL_W,
134    PRED_SEL_W,
135    IMM_0,
136    IMM_1,
137    VEC_COUNT
138 };
139
140}
141
142//===----------------------------------------------------------------------===//
143// Config register definitions
144//===----------------------------------------------------------------------===//
145
146#define R_02880C_DB_SHADER_CONTROL                    0x02880C
147#define   S_02880C_KILL_ENABLE(x)                      (((x) & 0x1) << 6)
148
149// These fields are the same for all shader types and families.
150#define   S_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
151#define   S_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
152//===----------------------------------------------------------------------===//
153// R600, R700 Registers
154//===----------------------------------------------------------------------===//
155
156#define R_028850_SQ_PGM_RESOURCES_PS                 0x028850
157#define R_028868_SQ_PGM_RESOURCES_VS                 0x028868
158
159//===----------------------------------------------------------------------===//
160// Evergreen, Northern Islands Registers
161//===----------------------------------------------------------------------===//
162
163#define R_028844_SQ_PGM_RESOURCES_PS                 0x028844
164#define R_028860_SQ_PGM_RESOURCES_VS                 0x028860
165#define R_028878_SQ_PGM_RESOURCES_GS                 0x028878
166#define R_0288D4_SQ_PGM_RESOURCES_LS                 0x0288d4
167
168#define R_0288E8_SQ_LDS_ALLOC                        0x0288E8
169
170#endif
171