1//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This file contains declaration for AMDGPU ISA disassembler
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/MC/MCContext.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCDisassembler/MCDisassembler.h"
22#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
23#include "llvm/MC/MCDisassembler/MCSymbolizer.h"
24
25#include <algorithm>
26#include <cstdint>
27#include <memory>
28
29namespace llvm {
30
31class MCInst;
32class MCOperand;
33class MCSubtargetInfo;
34class Twine;
35
36//===----------------------------------------------------------------------===//
37// AMDGPUDisassembler
38//===----------------------------------------------------------------------===//
39
40class AMDGPUDisassembler : public MCDisassembler {
41private:
42  std::unique_ptr<MCInstrInfo const> const MCII;
43  const MCRegisterInfo &MRI;
44  const unsigned TargetMaxInstBytes;
45  mutable ArrayRef<uint8_t> Bytes;
46  mutable uint32_t Literal;
47  mutable bool HasLiteral;
48
49public:
50  AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
51                     MCInstrInfo const *MCII);
52  ~AMDGPUDisassembler() override = default;
53
54  DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
55                              ArrayRef<uint8_t> Bytes, uint64_t Address,
56                              raw_ostream &CS) const override;
57
58  const char* getRegClassName(unsigned RegClassID) const;
59
60  MCOperand createRegOperand(unsigned int RegId) const;
61  MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
62  MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
63
64  MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
65
66  DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
67                             uint64_t Address) const;
68
69  DecodeStatus convertSDWAInst(MCInst &MI) const;
70  DecodeStatus convertDPP8Inst(MCInst &MI) const;
71  DecodeStatus convertMIMGInst(MCInst &MI) const;
72
73  MCOperand decodeOperand_VGPR_32(unsigned Val) const;
74  MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
75
76  MCOperand decodeOperand_VS_32(unsigned Val) const;
77  MCOperand decodeOperand_VS_64(unsigned Val) const;
78  MCOperand decodeOperand_VS_128(unsigned Val) const;
79  MCOperand decodeOperand_VSrc16(unsigned Val) const;
80  MCOperand decodeOperand_VSrcV216(unsigned Val) const;
81
82  MCOperand decodeOperand_VReg_64(unsigned Val) const;
83  MCOperand decodeOperand_VReg_96(unsigned Val) const;
84  MCOperand decodeOperand_VReg_128(unsigned Val) const;
85  MCOperand decodeOperand_VReg_256(unsigned Val) const;
86  MCOperand decodeOperand_VReg_512(unsigned Val) const;
87
88  MCOperand decodeOperand_SReg_32(unsigned Val) const;
89  MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
90  MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
91  MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const;
92  MCOperand decodeOperand_SReg_64(unsigned Val) const;
93  MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
94  MCOperand decodeOperand_SReg_128(unsigned Val) const;
95  MCOperand decodeOperand_SReg_256(unsigned Val) const;
96  MCOperand decodeOperand_SReg_512(unsigned Val) const;
97
98  MCOperand decodeOperand_AGPR_32(unsigned Val) const;
99  MCOperand decodeOperand_AReg_128(unsigned Val) const;
100  MCOperand decodeOperand_AReg_512(unsigned Val) const;
101  MCOperand decodeOperand_AReg_1024(unsigned Val) const;
102  MCOperand decodeOperand_AV_32(unsigned Val) const;
103  MCOperand decodeOperand_AV_64(unsigned Val) const;
104
105  enum OpWidthTy {
106    OPW32,
107    OPW64,
108    OPW128,
109    OPW256,
110    OPW512,
111    OPW1024,
112    OPW16,
113    OPWV216,
114    OPW_LAST_,
115    OPW_FIRST_ = OPW32
116  };
117
118  unsigned getVgprClassId(const OpWidthTy Width) const;
119  unsigned getAgprClassId(const OpWidthTy Width) const;
120  unsigned getSgprClassId(const OpWidthTy Width) const;
121  unsigned getTtmpClassId(const OpWidthTy Width) const;
122
123  static MCOperand decodeIntImmed(unsigned Imm);
124  static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
125  MCOperand decodeLiteralConstant() const;
126
127  MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
128  MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
129  MCOperand decodeSpecialReg32(unsigned Val) const;
130  MCOperand decodeSpecialReg64(unsigned Val) const;
131
132  MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
133  MCOperand decodeSDWASrc16(unsigned Val) const;
134  MCOperand decodeSDWASrc32(unsigned Val) const;
135  MCOperand decodeSDWAVopcDst(unsigned Val) const;
136
137  MCOperand decodeBoolReg(unsigned Val) const;
138
139  int getTTmpIdx(unsigned Val) const;
140
141  bool isVI() const;
142  bool isGFX9() const;
143  bool isGFX10() const;
144};
145
146//===----------------------------------------------------------------------===//
147// AMDGPUSymbolizer
148//===----------------------------------------------------------------------===//
149
150class AMDGPUSymbolizer : public MCSymbolizer {
151private:
152  void *DisInfo;
153
154public:
155  AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
156                   void *disInfo)
157                   : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
158
159  bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
160                                int64_t Value, uint64_t Address,
161                                bool IsBranch, uint64_t Offset,
162                                uint64_t InstSize) override;
163
164  void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
165                                       int64_t Value,
166                                       uint64_t Address) override;
167};
168
169} // end namespace llvm
170
171#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
172