1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13#include "llvm/Target/TargetMachine.h"
14#include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this.
15#include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this.
16
17namespace llvm {
18
19class AMDGPUTargetMachine;
20class FunctionPass;
21class GCNTargetMachine;
22class ModulePass;
23class Pass;
24class Target;
25class TargetMachine;
26class TargetOptions;
27class PassRegistry;
28class Module;
29
30// R600 Passes
31FunctionPass *createR600VectorRegMerger();
32FunctionPass *createR600ExpandSpecialInstrsPass();
33FunctionPass *createR600EmitClauseMarkers();
34FunctionPass *createR600ClauseMergePass();
35FunctionPass *createR600Packetizer();
36FunctionPass *createR600ControlFlowFinalizer();
37FunctionPass *createAMDGPUCFGStructurizerPass();
38FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
39
40// SI Passes
41FunctionPass *createGCNDPPCombinePass();
42FunctionPass *createSIAnnotateControlFlowPass();
43FunctionPass *createSIFoldOperandsPass();
44FunctionPass *createSIPeepholeSDWAPass();
45FunctionPass *createSILowerI1CopiesPass();
46FunctionPass *createSIFixupVectorISelPass();
47FunctionPass *createSIAddIMGInitPass();
48FunctionPass *createSIShrinkInstructionsPass();
49FunctionPass *createSILoadStoreOptimizerPass();
50FunctionPass *createSIWholeQuadModePass();
51FunctionPass *createSIFixControlFlowLiveIntervalsPass();
52FunctionPass *createSIOptimizeExecMaskingPreRAPass();
53FunctionPass *createSIFixSGPRCopiesPass();
54FunctionPass *createSIMemoryLegalizerPass();
55FunctionPass *createSIInsertWaitcntsPass();
56FunctionPass *createSIPreAllocateWWMRegsPass();
57FunctionPass *createSIFormMemoryClausesPass();
58FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &,
59                                               const TargetMachine *);
60FunctionPass *createAMDGPUUseNativeCallsPass();
61FunctionPass *createAMDGPUCodeGenPreparePass();
62FunctionPass *createAMDGPUMachineCFGStructurizerPass();
63FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
64ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
65FunctionPass *createAMDGPURewriteOutArgumentsPass();
66FunctionPass *createSIModeRegisterPass();
67
68void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
69
70void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
71extern char &AMDGPUMachineCFGStructurizerID;
72
73void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
74
75Pass *createAMDGPUAnnotateKernelFeaturesPass();
76void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
77extern char &AMDGPUAnnotateKernelFeaturesID;
78
79FunctionPass *createAMDGPUAtomicOptimizerPass();
80void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
81extern char &AMDGPUAtomicOptimizerID;
82
83ModulePass *createAMDGPULowerIntrinsicsPass();
84void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
85extern char &AMDGPULowerIntrinsicsID;
86
87ModulePass *createAMDGPUFixFunctionBitcastsPass();
88void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
89extern char &AMDGPUFixFunctionBitcastsID;
90
91FunctionPass *createAMDGPULowerKernelArgumentsPass();
92void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
93extern char &AMDGPULowerKernelArgumentsID;
94
95ModulePass *createAMDGPULowerKernelAttributesPass();
96void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
97extern char &AMDGPULowerKernelAttributesID;
98
99void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &);
100extern char &AMDGPUPropagateAttributesEarlyID;
101
102void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &);
103extern char &AMDGPUPropagateAttributesLateID;
104
105void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
106extern char &AMDGPURewriteOutArgumentsID;
107
108void initializeGCNDPPCombinePass(PassRegistry &);
109extern char &GCNDPPCombineID;
110
111void initializeR600ClauseMergePassPass(PassRegistry &);
112extern char &R600ClauseMergePassID;
113
114void initializeR600ControlFlowFinalizerPass(PassRegistry &);
115extern char &R600ControlFlowFinalizerID;
116
117void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
118extern char &R600ExpandSpecialInstrsPassID;
119
120void initializeR600VectorRegMergerPass(PassRegistry &);
121extern char &R600VectorRegMergerID;
122
123void initializeR600PacketizerPass(PassRegistry &);
124extern char &R600PacketizerID;
125
126void initializeSIFoldOperandsPass(PassRegistry &);
127extern char &SIFoldOperandsID;
128
129void initializeSIPeepholeSDWAPass(PassRegistry &);
130extern char &SIPeepholeSDWAID;
131
132void initializeSIShrinkInstructionsPass(PassRegistry&);
133extern char &SIShrinkInstructionsID;
134
135void initializeSIFixSGPRCopiesPass(PassRegistry &);
136extern char &SIFixSGPRCopiesID;
137
138void initializeSIFixVGPRCopiesPass(PassRegistry &);
139extern char &SIFixVGPRCopiesID;
140
141void initializeSIFixupVectorISelPass(PassRegistry &);
142extern char &SIFixupVectorISelID;
143
144void initializeSILowerI1CopiesPass(PassRegistry &);
145extern char &SILowerI1CopiesID;
146
147void initializeSILowerSGPRSpillsPass(PassRegistry &);
148extern char &SILowerSGPRSpillsID;
149
150void initializeSILoadStoreOptimizerPass(PassRegistry &);
151extern char &SILoadStoreOptimizerID;
152
153void initializeSIWholeQuadModePass(PassRegistry &);
154extern char &SIWholeQuadModeID;
155
156void initializeSILowerControlFlowPass(PassRegistry &);
157extern char &SILowerControlFlowID;
158
159void initializeSIInsertSkipsPass(PassRegistry &);
160extern char &SIInsertSkipsPassID;
161
162void initializeSIOptimizeExecMaskingPass(PassRegistry &);
163extern char &SIOptimizeExecMaskingID;
164
165void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
166extern char &SIPreAllocateWWMRegsID;
167
168void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
169extern char &AMDGPUSimplifyLibCallsID;
170
171void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
172extern char &AMDGPUUseNativeCallsID;
173
174void initializeSIAddIMGInitPass(PassRegistry &);
175extern char &SIAddIMGInitID;
176
177void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
178extern char &AMDGPUPerfHintAnalysisID;
179
180// Passes common to R600 and SI
181FunctionPass *createAMDGPUPromoteAlloca();
182void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
183extern char &AMDGPUPromoteAllocaID;
184
185Pass *createAMDGPUStructurizeCFGPass();
186FunctionPass *createAMDGPUISelDag(
187  TargetMachine *TM = nullptr,
188  CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
189ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
190ModulePass *createR600OpenCLImageTypeLoweringPass();
191FunctionPass *createAMDGPUAnnotateUniformValues();
192
193ModulePass *createAMDGPUPrintfRuntimeBinding();
194void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
195extern char &AMDGPUPrintfRuntimeBindingID;
196
197ModulePass* createAMDGPUUnifyMetadataPass();
198void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
199extern char &AMDGPUUnifyMetadataID;
200
201void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
202extern char &SIOptimizeExecMaskingPreRAID;
203
204void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
205extern char &AMDGPUAnnotateUniformValuesPassID;
206
207void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
208extern char &AMDGPUCodeGenPrepareID;
209
210void initializeSIAnnotateControlFlowPass(PassRegistry&);
211extern char &SIAnnotateControlFlowPassID;
212
213void initializeSIMemoryLegalizerPass(PassRegistry&);
214extern char &SIMemoryLegalizerID;
215
216void initializeSIModeRegisterPass(PassRegistry&);
217extern char &SIModeRegisterID;
218
219void initializeSIInsertWaitcntsPass(PassRegistry&);
220extern char &SIInsertWaitcntsID;
221
222void initializeSIFormMemoryClausesPass(PassRegistry&);
223extern char &SIFormMemoryClausesID;
224
225void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
226extern char &AMDGPUUnifyDivergentExitNodesID;
227
228ImmutablePass *createAMDGPUAAWrapperPass();
229void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
230ImmutablePass *createAMDGPUExternalAAWrapperPass();
231void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
232
233void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
234
235Pass *createAMDGPUFunctionInliningPass();
236void initializeAMDGPUInlinerPass(PassRegistry&);
237
238ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
239void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
240extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
241
242void initializeGCNRegBankReassignPass(PassRegistry &);
243extern char &GCNRegBankReassignID;
244
245void initializeGCNNSAReassignPass(PassRegistry &);
246extern char &GCNNSAReassignID;
247
248namespace AMDGPU {
249enum TargetIndex {
250  TI_CONSTDATA_START,
251  TI_SCRATCH_RSRC_DWORD0,
252  TI_SCRATCH_RSRC_DWORD1,
253  TI_SCRATCH_RSRC_DWORD2,
254  TI_SCRATCH_RSRC_DWORD3
255};
256}
257
258} // End namespace llvm
259
260/// OpenCL uses address spaces to differentiate between
261/// various memory regions on the hardware. On the CPU
262/// all of the address spaces point to the same memory,
263/// however on the GPU, each address space points to
264/// a separate piece of memory that is unique from other
265/// memory locations.
266namespace AMDGPUAS {
267  enum : unsigned {
268    // The maximum value for flat, generic, local, private, constant and region.
269    MAX_AMDGPU_ADDRESS = 7,
270
271    FLAT_ADDRESS = 0,     ///< Address space for flat memory.
272    GLOBAL_ADDRESS = 1,   ///< Address space for global memory (RAT0, VTX0).
273    REGION_ADDRESS = 2,   ///< Address space for region memory. (GDS)
274
275    CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
276    LOCAL_ADDRESS = 3,    ///< Address space for local memory.
277    PRIVATE_ADDRESS = 5,  ///< Address space for private memory.
278
279    CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
280
281    BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
282
283    /// Address space for direct addressible parameter memory (CONST0).
284    PARAM_D_ADDRESS = 6,
285    /// Address space for indirect addressible parameter memory (VTX1).
286    PARAM_I_ADDRESS = 7,
287
288    // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on
289    // this order to be able to dynamically index a constant buffer, for
290    // example:
291    //
292    // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
293
294    CONSTANT_BUFFER_0 = 8,
295    CONSTANT_BUFFER_1 = 9,
296    CONSTANT_BUFFER_2 = 10,
297    CONSTANT_BUFFER_3 = 11,
298    CONSTANT_BUFFER_4 = 12,
299    CONSTANT_BUFFER_5 = 13,
300    CONSTANT_BUFFER_6 = 14,
301    CONSTANT_BUFFER_7 = 15,
302    CONSTANT_BUFFER_8 = 16,
303    CONSTANT_BUFFER_9 = 17,
304    CONSTANT_BUFFER_10 = 18,
305    CONSTANT_BUFFER_11 = 19,
306    CONSTANT_BUFFER_12 = 20,
307    CONSTANT_BUFFER_13 = 21,
308    CONSTANT_BUFFER_14 = 22,
309    CONSTANT_BUFFER_15 = 23,
310
311    // Some places use this if the address space can't be determined.
312    UNKNOWN_ADDRESS_SPACE = ~0u,
313  };
314}
315
316#endif
317