Host.cpp revision 223017 
1//===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//  This header file implements the operating system Host concept.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Support/Host.h"
15#include "llvm/Config/config.h"
16#include <string.h>
17
18// Include the platform-specific parts of this class.
19#ifdef LLVM_ON_UNIX
20#include "Unix/Host.inc"
21#endif
22#ifdef LLVM_ON_WIN32
23#include "Windows/Host.inc"
24#endif
25#ifdef _MSC_VER
26#include <intrin.h>
27#endif
28
29//===----------------------------------------------------------------------===//
30//
31//  Implementations of the CPU detection routines
32//
33//===----------------------------------------------------------------------===//
34
35using namespace llvm;
36
37#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
38 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
39
40/// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
41/// specified arguments.  If we can't run cpuid on the host, return true.
42static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
43                            unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
44#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
45  #if defined(__GNUC__)
46    // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
47    asm ("movq\t%%rbx, %%rsi\n\t"
48         "cpuid\n\t"
49         "xchgq\t%%rbx, %%rsi\n\t"
50         : "=a" (*rEAX),
51           "=S" (*rEBX),
52           "=c" (*rECX),
53           "=d" (*rEDX)
54         :  "a" (value));
55    return false;
56  #elif defined(_MSC_VER)
57    int registers[4];
58    __cpuid(registers, value);
59    *rEAX = registers[0];
60    *rEBX = registers[1];
61    *rECX = registers[2];
62    *rEDX = registers[3];
63    return false;
64  #endif
65#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
66  #if defined(__GNUC__)
67    asm ("movl\t%%ebx, %%esi\n\t"
68         "cpuid\n\t"
69         "xchgl\t%%ebx, %%esi\n\t"
70         : "=a" (*rEAX),
71           "=S" (*rEBX),
72           "=c" (*rECX),
73           "=d" (*rEDX)
74         :  "a" (value));
75    return false;
76  #elif defined(_MSC_VER)
77    __asm {
78      mov   eax,value
79      cpuid
80      mov   esi,rEAX
81      mov   dword ptr [esi],eax
82      mov   esi,rEBX
83      mov   dword ptr [esi],ebx
84      mov   esi,rECX
85      mov   dword ptr [esi],ecx
86      mov   esi,rEDX
87      mov   dword ptr [esi],edx
88    }
89    return false;
90  #endif
91#endif
92  return true;
93}
94
95static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
96                                 unsigned &Model) {
97  Family = (EAX >> 8) & 0xf; // Bits 8 - 11
98  Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
99  if (Family == 6 || Family == 0xf) {
100    if (Family == 0xf)
101      // Examine extended family ID if family ID is F.
102      Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
103    // Examine extended model ID if family ID is 6 or F.
104    Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
105  }
106}
107
108std::string sys::getHostCPUName() {
109  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
110  if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
111    return "generic";
112  unsigned Family = 0;
113  unsigned Model  = 0;
114  DetectX86FamilyModel(EAX, Family, Model);
115
116  bool HasSSE3 = (ECX & 0x1);
117  GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
118  bool Em64T = (EDX >> 29) & 0x1;
119
120  union {
121    unsigned u[3];
122    char     c[12];
123  } text;
124
125  GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
126  if (memcmp(text.c, "GenuineIntel", 12) == 0) {
127    switch (Family) {
128    case 3:
129      return "i386";
130    case 4:
131      switch (Model) {
132      case 0: // Intel486 DX processors
133      case 1: // Intel486 DX processors
134      case 2: // Intel486 SX processors
135      case 3: // Intel487 processors, IntelDX2 OverDrive processors,
136              // IntelDX2 processors
137      case 4: // Intel486 SL processor
138      case 5: // IntelSX2 processors
139      case 7: // Write-Back Enhanced IntelDX2 processors
140      case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
141      default: return "i486";
142      }
143    case 5:
144      switch (Model) {
145      case  1: // Pentium OverDrive processor for Pentium processor (60, 66),
146               // Pentium processors (60, 66)
147      case  2: // Pentium OverDrive processor for Pentium processor (75, 90,
148               // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
149               // 150, 166, 200)
150      case  3: // Pentium OverDrive processors for Intel486 processor-based
151               // systems
152        return "pentium";
153
154      case  4: // Pentium OverDrive processor with MMX technology for Pentium
155               // processor (75, 90, 100, 120, 133), Pentium processor with
156               // MMX technology (166, 200)
157        return "pentium-mmx";
158
159      default: return "pentium";
160      }
161    case 6:
162      switch (Model) {
163      case  1: // Pentium Pro processor
164        return "pentiumpro";
165
166      case  3: // Intel Pentium II OverDrive processor, Pentium II processor,
167               // model 03
168      case  5: // Pentium II processor, model 05, Pentium II Xeon processor,
169               // model 05, and Intel Celeron processor, model 05
170      case  6: // Celeron processor, model 06
171        return "pentium2";
172
173      case  7: // Pentium III processor, model 07, and Pentium III Xeon
174               // processor, model 07
175      case  8: // Pentium III processor, model 08, Pentium III Xeon processor,
176               // model 08, and Celeron processor, model 08
177      case 10: // Pentium III Xeon processor, model 0Ah
178      case 11: // Pentium III processor, model 0Bh
179        return "pentium3";
180
181      case  9: // Intel Pentium M processor, Intel Celeron M processor model 09.
182      case 13: // Intel Pentium M processor, Intel Celeron M processor, model
183               // 0Dh. All processors are manufactured using the 90 nm process.
184        return "pentium-m";
185
186      case 14: // Intel Core Duo processor, Intel Core Solo processor, model
187               // 0Eh. All processors are manufactured using the 65 nm process.
188        return "yonah";
189
190      case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
191               // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
192               // mobile processor, Intel Core 2 Extreme processor, Intel
193               // Pentium Dual-Core processor, Intel Xeon processor, model
194               // 0Fh. All processors are manufactured using the 65 nm process.
195      case 22: // Intel Celeron processor model 16h. All processors are
196               // manufactured using the 65 nm process
197        return "core2";
198
199      case 21: // Intel EP80579 Integrated Processor and Intel EP80579
200               // Integrated Processor with Intel QuickAssist Technology
201        return "i686"; // FIXME: ???
202
203      case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
204               // 17h. All processors are manufactured using the 45 nm process.
205               //
206               // 45nm: Penryn , Wolfdale, Yorkfield (XE)
207        return "penryn";
208
209      case 26: // Intel Core i7 processor and Intel Xeon processor. All
210               // processors are manufactured using the 45 nm process.
211      case 29: // Intel Xeon processor MP. All processors are manufactured using
212               // the 45 nm process.
213      case 30: // Intel(R) Core(TM) i7 CPU         870  @ 2.93GHz.
214               // As found in a Summer 2010 model iMac.
215      case 37: // Intel Core i7, laptop version.
216        return "corei7";
217      case 42: // SandyBridge
218      case 45:
219        return "corei7-avx";
220
221      case 28: // Intel Atom processor. All processors are manufactured using
222               // the 45 nm process
223        return "atom";
224
225      default: return "i686";
226      }
227    case 15: {
228      switch (Model) {
229      case  0: // Pentium 4 processor, Intel Xeon processor. All processors are
230               // model 00h and manufactured using the 0.18 micron process.
231      case  1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
232               // processor MP, and Intel Celeron processor. All processors are
233               // model 01h and manufactured using the 0.18 micron process.
234      case  2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
235               // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
236               // processor, and Mobile Intel Celeron processor. All processors
237               // are model 02h and manufactured using the 0.13 micron process.
238        return (Em64T) ? "x86-64" : "pentium4";
239
240      case  3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
241               // processor. All processors are model 03h and manufactured using
242               // the 90 nm process.
243      case  4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
244               // Pentium D processor, Intel Xeon processor, Intel Xeon
245               // processor MP, Intel Celeron D processor. All processors are
246               // model 04h and manufactured using the 90 nm process.
247      case  6: // Pentium 4 processor, Pentium D processor, Pentium processor
248               // Extreme Edition, Intel Xeon processor, Intel Xeon processor
249               // MP, Intel Celeron D processor. All processors are model 06h
250               // and manufactured using the 65 nm process.
251        return (Em64T) ? "nocona" : "prescott";
252
253      default:
254        return (Em64T) ? "x86-64" : "pentium4";
255      }
256    }
257
258    default:
259      return "generic";
260    }
261  } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
262    // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
263    // appears to be no way to generate the wide variety of AMD-specific targets
264    // from the information returned from CPUID.
265    switch (Family) {
266      case 4:
267        return "i486";
268      case 5:
269        switch (Model) {
270        case 6:
271        case 7:  return "k6";
272        case 8:  return "k6-2";
273        case 9:
274        case 13: return "k6-3";
275        default: return "pentium";
276        }
277      case 6:
278        switch (Model) {
279        case 4:  return "athlon-tbird";
280        case 6:
281        case 7:
282        case 8:  return "athlon-mp";
283        case 10: return "athlon-xp";
284        default: return "athlon";
285        }
286      case 15:
287        if (HasSSE3)
288          return "k8-sse3";
289        switch (Model) {
290        case 1:  return "opteron";
291        case 5:  return "athlon-fx"; // also opteron
292        default: return "athlon64";
293        }
294      case 16:
295        return "amdfam10";
296    default:
297      return "generic";
298    }
299  }
300  return "generic";
301}
302#else
303std::string sys::getHostCPUName() {
304  return "generic";
305}
306#endif
307
308bool sys::getHostCPUFeatures(StringMap<bool> &Features){
309  return false;
310}
311