1//===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file implements the operating system Host concept. 10// 11//===----------------------------------------------------------------------===// 12 13#include "llvm/Support/Host.h" 14#include "llvm/Support/TargetParser.h" 15#include "llvm/ADT/SmallSet.h" 16#include "llvm/ADT/SmallVector.h" 17#include "llvm/ADT/StringRef.h" 18#include "llvm/ADT/StringSwitch.h" 19#include "llvm/ADT/Triple.h" 20#include "llvm/Config/llvm-config.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/FileSystem.h" 23#include "llvm/Support/MemoryBuffer.h" 24#include "llvm/Support/raw_ostream.h" 25#include <assert.h> 26#include <string.h> 27 28// Include the platform-specific parts of this class. 29#ifdef LLVM_ON_UNIX 30#include "Unix/Host.inc" 31#endif 32#ifdef _WIN32 33#include "Windows/Host.inc" 34#endif 35#ifdef _MSC_VER 36#include <intrin.h> 37#endif 38#if defined(__APPLE__) && (!defined(__x86_64__)) 39#include <mach/host_info.h> 40#include <mach/mach.h> 41#include <mach/mach_host.h> 42#include <mach/machine.h> 43#endif 44 45#define DEBUG_TYPE "host-detection" 46 47//===----------------------------------------------------------------------===// 48// 49// Implementations of the CPU detection routines 50// 51//===----------------------------------------------------------------------===// 52 53using namespace llvm; 54 55static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65} 66 67StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 68 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 69 // and so we must use an operating-system interface to determine the current 70 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 71 const char *generic = "generic"; 72 73 // The cpu line is second (after the 'processor: 0' line), so if this 74 // buffer is too small then something has changed (or is wrong). 75 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 76 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 77 78 StringRef::const_iterator CIP = CPUInfoStart; 79 80 StringRef::const_iterator CPUStart = 0; 81 size_t CPULen = 0; 82 83 // We need to find the first line which starts with cpu, spaces, and a colon. 84 // After the colon, there may be some additional spaces and then the cpu type. 85 while (CIP < CPUInfoEnd && CPUStart == 0) { 86 if (CIP < CPUInfoEnd && *CIP == '\n') 87 ++CIP; 88 89 if (CIP < CPUInfoEnd && *CIP == 'c') { 90 ++CIP; 91 if (CIP < CPUInfoEnd && *CIP == 'p') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'u') { 94 ++CIP; 95 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 96 ++CIP; 97 98 if (CIP < CPUInfoEnd && *CIP == ':') { 99 ++CIP; 100 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 101 ++CIP; 102 103 if (CIP < CPUInfoEnd) { 104 CPUStart = CIP; 105 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 106 *CIP != ',' && *CIP != '\n')) 107 ++CIP; 108 CPULen = CIP - CPUStart; 109 } 110 } 111 } 112 } 113 } 114 115 if (CPUStart == 0) 116 while (CIP < CPUInfoEnd && *CIP != '\n') 117 ++CIP; 118 } 119 120 if (CPUStart == 0) 121 return generic; 122 123 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 124 .Case("604e", "604e") 125 .Case("604", "604") 126 .Case("7400", "7400") 127 .Case("7410", "7400") 128 .Case("7447", "7400") 129 .Case("7455", "7450") 130 .Case("G4", "g4") 131 .Case("POWER4", "970") 132 .Case("PPC970FX", "970") 133 .Case("PPC970MP", "970") 134 .Case("G5", "g5") 135 .Case("POWER5", "g5") 136 .Case("A2", "a2") 137 .Case("POWER6", "pwr6") 138 .Case("POWER7", "pwr7") 139 .Case("POWER8", "pwr8") 140 .Case("POWER8E", "pwr8") 141 .Case("POWER8NVL", "pwr8") 142 .Case("POWER9", "pwr9") 143 // FIXME: If we get a simulator or machine with the capabilities of 144 // mcpu=future, we should revisit this and add the name reported by the 145 // simulator/machine. 146 .Default(generic); 147} 148 149StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 150 // The cpuid register on arm is not accessible from user space. On Linux, 151 // it is exposed through the /proc/cpuinfo file. 152 153 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 154 // in all cases. 155 SmallVector<StringRef, 32> Lines; 156 ProcCpuinfoContent.split(Lines, "\n"); 157 158 // Look for the CPU implementer line. 159 StringRef Implementer; 160 StringRef Hardware; 161 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 162 if (Lines[I].startswith("CPU implementer")) 163 Implementer = Lines[I].substr(15).ltrim("\t :"); 164 if (Lines[I].startswith("Hardware")) 165 Hardware = Lines[I].substr(8).ltrim("\t :"); 166 } 167 168 if (Implementer == "0x41") { // ARM Ltd. 169 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 170 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 171 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 172 return "cortex-a53"; 173 174 175 // Look for the CPU part line. 176 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 177 if (Lines[I].startswith("CPU part")) 178 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 179 // values correspond to the "Part number" in the CP15/c0 register. The 180 // contents are specified in the various processor manuals. 181 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 182 .Case("0x926", "arm926ej-s") 183 .Case("0xb02", "mpcore") 184 .Case("0xb36", "arm1136j-s") 185 .Case("0xb56", "arm1156t2-s") 186 .Case("0xb76", "arm1176jz-s") 187 .Case("0xc08", "cortex-a8") 188 .Case("0xc09", "cortex-a9") 189 .Case("0xc0f", "cortex-a15") 190 .Case("0xc20", "cortex-m0") 191 .Case("0xc23", "cortex-m3") 192 .Case("0xc24", "cortex-m4") 193 .Case("0xd04", "cortex-a35") 194 .Case("0xd03", "cortex-a53") 195 .Case("0xd07", "cortex-a57") 196 .Case("0xd08", "cortex-a72") 197 .Case("0xd09", "cortex-a73") 198 .Case("0xd0a", "cortex-a75") 199 .Case("0xd0b", "cortex-a76") 200 .Default("generic"); 201 } 202 203 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 204 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 205 if (Lines[I].startswith("CPU part")) { 206 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 207 .Case("0x516", "thunderx2t99") 208 .Case("0x0516", "thunderx2t99") 209 .Case("0xaf", "thunderx2t99") 210 .Case("0x0af", "thunderx2t99") 211 .Case("0xa1", "thunderxt88") 212 .Case("0x0a1", "thunderxt88") 213 .Default("generic"); 214 } 215 } 216 } 217 218 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 219 // Look for the CPU part line. 220 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 221 if (Lines[I].startswith("CPU part")) 222 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 223 // values correspond to the "Part number" in the CP15/c0 register. The 224 // contents are specified in the various processor manuals. 225 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 226 .Case("0xd01", "tsv110") 227 .Default("generic"); 228 229 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 230 // Look for the CPU part line. 231 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 232 if (Lines[I].startswith("CPU part")) 233 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 234 // values correspond to the "Part number" in the CP15/c0 register. The 235 // contents are specified in the various processor manuals. 236 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 237 .Case("0x06f", "krait") // APQ8064 238 .Case("0x201", "kryo") 239 .Case("0x205", "kryo") 240 .Case("0x211", "kryo") 241 .Case("0x800", "cortex-a73") 242 .Case("0x801", "cortex-a73") 243 .Case("0x802", "cortex-a73") 244 .Case("0x803", "cortex-a73") 245 .Case("0x804", "cortex-a73") 246 .Case("0x805", "cortex-a73") 247 .Case("0xc00", "falkor") 248 .Case("0xc01", "saphira") 249 .Default("generic"); 250 251 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 252 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 253 // any predictive pattern across variants and parts. 254 unsigned Variant = 0, Part = 0; 255 256 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 257 // number, corresponding to the Variant bits in the CP15/C0 register. 258 for (auto I : Lines) 259 if (I.consume_front("CPU variant")) 260 I.ltrim("\t :").getAsInteger(0, Variant); 261 262 // Look for the CPU part line, whose value is a 3 digit hexadecimal 263 // number, corresponding to the PartNum bits in the CP15/C0 register. 264 for (auto I : Lines) 265 if (I.consume_front("CPU part")) 266 I.ltrim("\t :").getAsInteger(0, Part); 267 268 unsigned Exynos = (Variant << 12) | Part; 269 switch (Exynos) { 270 default: 271 // Default by falling through to Exynos M3. 272 LLVM_FALLTHROUGH; 273 case 0x1002: 274 return "exynos-m3"; 275 case 0x1003: 276 return "exynos-m4"; 277 } 278 } 279 280 return "generic"; 281} 282 283StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 284 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 285 286 // The "processor 0:" line comes after a fair amount of other information, 287 // including a cache breakdown, but this should be plenty. 288 SmallVector<StringRef, 32> Lines; 289 ProcCpuinfoContent.split(Lines, "\n"); 290 291 // Look for the CPU features. 292 SmallVector<StringRef, 32> CPUFeatures; 293 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 294 if (Lines[I].startswith("features")) { 295 size_t Pos = Lines[I].find(":"); 296 if (Pos != StringRef::npos) { 297 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 298 break; 299 } 300 } 301 302 // We need to check for the presence of vector support independently of 303 // the machine type, since we may only use the vector register set when 304 // supported by the kernel (and hypervisor). 305 bool HaveVectorSupport = false; 306 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 307 if (CPUFeatures[I] == "vx") 308 HaveVectorSupport = true; 309 } 310 311 // Now check the processor machine type. 312 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 313 if (Lines[I].startswith("processor ")) { 314 size_t Pos = Lines[I].find("machine = "); 315 if (Pos != StringRef::npos) { 316 Pos += sizeof("machine = ") - 1; 317 unsigned int Id; 318 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 319 if (Id >= 8561 && HaveVectorSupport) 320 return "z15"; 321 if (Id >= 3906 && HaveVectorSupport) 322 return "z14"; 323 if (Id >= 2964 && HaveVectorSupport) 324 return "z13"; 325 if (Id >= 2827) 326 return "zEC12"; 327 if (Id >= 2817) 328 return "z196"; 329 } 330 } 331 break; 332 } 333 } 334 335 return "generic"; 336} 337 338StringRef sys::detail::getHostCPUNameForBPF() { 339#if !defined(__linux__) || !defined(__x86_64__) 340 return "generic"; 341#else 342 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 343 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 344 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 345 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 346 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 347 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 348 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 349 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 350 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 351 /* BPF_EXIT_INSN() */ 352 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 353 354 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 355 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 356 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 357 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 358 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 359 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 360 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 361 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 362 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 363 /* BPF_EXIT_INSN() */ 364 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 365 366 struct bpf_prog_load_attr { 367 uint32_t prog_type; 368 uint32_t insn_cnt; 369 uint64_t insns; 370 uint64_t license; 371 uint32_t log_level; 372 uint32_t log_size; 373 uint64_t log_buf; 374 uint32_t kern_version; 375 uint32_t prog_flags; 376 } attr = {}; 377 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 378 attr.insn_cnt = 5; 379 attr.insns = (uint64_t)v3_insns; 380 attr.license = (uint64_t)"DUMMY"; 381 382 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 383 sizeof(attr)); 384 if (fd >= 0) { 385 close(fd); 386 return "v3"; 387 } 388 389 /* Clear the whole attr in case its content changed by syscall. */ 390 memset(&attr, 0, sizeof(attr)); 391 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 392 attr.insn_cnt = 5; 393 attr.insns = (uint64_t)v2_insns; 394 attr.license = (uint64_t)"DUMMY"; 395 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 396 if (fd >= 0) { 397 close(fd); 398 return "v2"; 399 } 400 return "v1"; 401#endif 402} 403 404#if defined(__i386__) || defined(_M_IX86) || \ 405 defined(__x86_64__) || defined(_M_X64) 406 407enum VendorSignatures { 408 SIG_INTEL = 0x756e6547 /* Genu */, 409 SIG_AMD = 0x68747541 /* Auth */ 410}; 411 412// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 413// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 414// support. Consequently, for i386, the presence of CPUID is checked first 415// via the corresponding eflags bit. 416// Removal of cpuid.h header motivated by PR30384 417// Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 418// or test-suite, but are used in external projects e.g. libstdcxx 419static bool isCpuIdSupported() { 420#if defined(__GNUC__) || defined(__clang__) 421#if defined(__i386__) 422 int __cpuid_supported; 423 __asm__(" pushfl\n" 424 " popl %%eax\n" 425 " movl %%eax,%%ecx\n" 426 " xorl $0x00200000,%%eax\n" 427 " pushl %%eax\n" 428 " popfl\n" 429 " pushfl\n" 430 " popl %%eax\n" 431 " movl $0,%0\n" 432 " cmpl %%eax,%%ecx\n" 433 " je 1f\n" 434 " movl $1,%0\n" 435 "1:" 436 : "=r"(__cpuid_supported) 437 : 438 : "eax", "ecx"); 439 if (!__cpuid_supported) 440 return false; 441#endif 442 return true; 443#endif 444 return true; 445} 446 447/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 448/// the specified arguments. If we can't run cpuid on the host, return true. 449static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 450 unsigned *rECX, unsigned *rEDX) { 451#if defined(__GNUC__) || defined(__clang__) 452#if defined(__x86_64__) 453 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 454 // FIXME: should we save this for Clang? 455 __asm__("movq\t%%rbx, %%rsi\n\t" 456 "cpuid\n\t" 457 "xchgq\t%%rbx, %%rsi\n\t" 458 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 459 : "a"(value)); 460 return false; 461#elif defined(__i386__) 462 __asm__("movl\t%%ebx, %%esi\n\t" 463 "cpuid\n\t" 464 "xchgl\t%%ebx, %%esi\n\t" 465 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 466 : "a"(value)); 467 return false; 468#else 469 return true; 470#endif 471#elif defined(_MSC_VER) 472 // The MSVC intrinsic is portable across x86 and x64. 473 int registers[4]; 474 __cpuid(registers, value); 475 *rEAX = registers[0]; 476 *rEBX = registers[1]; 477 *rECX = registers[2]; 478 *rEDX = registers[3]; 479 return false; 480#else 481 return true; 482#endif 483} 484 485/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 486/// the 4 values in the specified arguments. If we can't run cpuid on the host, 487/// return true. 488static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 489 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 490 unsigned *rEDX) { 491#if defined(__GNUC__) || defined(__clang__) 492#if defined(__x86_64__) 493 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 494 // FIXME: should we save this for Clang? 495 __asm__("movq\t%%rbx, %%rsi\n\t" 496 "cpuid\n\t" 497 "xchgq\t%%rbx, %%rsi\n\t" 498 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 499 : "a"(value), "c"(subleaf)); 500 return false; 501#elif defined(__i386__) 502 __asm__("movl\t%%ebx, %%esi\n\t" 503 "cpuid\n\t" 504 "xchgl\t%%ebx, %%esi\n\t" 505 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 506 : "a"(value), "c"(subleaf)); 507 return false; 508#else 509 return true; 510#endif 511#elif defined(_MSC_VER) 512 int registers[4]; 513 __cpuidex(registers, value, subleaf); 514 *rEAX = registers[0]; 515 *rEBX = registers[1]; 516 *rECX = registers[2]; 517 *rEDX = registers[3]; 518 return false; 519#else 520 return true; 521#endif 522} 523 524// Read control register 0 (XCR0). Used to detect features such as AVX. 525static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 526#if defined(__GNUC__) || defined(__clang__) 527 // Check xgetbv; this uses a .byte sequence instead of the instruction 528 // directly because older assemblers do not include support for xgetbv and 529 // there is no easy way to conditionally compile based on the assembler used. 530 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 531 return false; 532#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 533 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 534 *rEAX = Result; 535 *rEDX = Result >> 32; 536 return false; 537#else 538 return true; 539#endif 540} 541 542static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 543 unsigned *Model) { 544 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 545 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 546 if (*Family == 6 || *Family == 0xf) { 547 if (*Family == 0xf) 548 // Examine extended family ID if family ID is F. 549 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 550 // Examine extended model ID if family ID is 6 or F. 551 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 552 } 553} 554 555static void 556getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 557 unsigned Brand_id, unsigned Features, 558 unsigned Features2, unsigned Features3, 559 unsigned *Type, unsigned *Subtype) { 560 if (Brand_id != 0) 561 return; 562 switch (Family) { 563 case 3: 564 *Type = X86::INTEL_i386; 565 break; 566 case 4: 567 *Type = X86::INTEL_i486; 568 break; 569 case 5: 570 if (Features & (1 << X86::FEATURE_MMX)) { 571 *Type = X86::INTEL_PENTIUM_MMX; 572 break; 573 } 574 *Type = X86::INTEL_PENTIUM; 575 break; 576 case 6: 577 switch (Model) { 578 case 0x01: // Pentium Pro processor 579 *Type = X86::INTEL_PENTIUM_PRO; 580 break; 581 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 582 // model 03 583 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 584 // model 05, and Intel Celeron processor, model 05 585 case 0x06: // Celeron processor, model 06 586 *Type = X86::INTEL_PENTIUM_II; 587 break; 588 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 589 // processor, model 07 590 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 591 // model 08, and Celeron processor, model 08 592 case 0x0a: // Pentium III Xeon processor, model 0Ah 593 case 0x0b: // Pentium III processor, model 0Bh 594 *Type = X86::INTEL_PENTIUM_III; 595 break; 596 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 597 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 598 // 0Dh. All processors are manufactured using the 90 nm process. 599 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 600 // Integrated Processor with Intel QuickAssist Technology 601 *Type = X86::INTEL_PENTIUM_M; 602 break; 603 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 604 // 0Eh. All processors are manufactured using the 65 nm process. 605 *Type = X86::INTEL_CORE_DUO; 606 break; // yonah 607 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 608 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 609 // mobile processor, Intel Core 2 Extreme processor, Intel 610 // Pentium Dual-Core processor, Intel Xeon processor, model 611 // 0Fh. All processors are manufactured using the 65 nm process. 612 case 0x16: // Intel Celeron processor model 16h. All processors are 613 // manufactured using the 65 nm process 614 *Type = X86::INTEL_CORE2; // "core2" 615 *Subtype = X86::INTEL_CORE2_65; 616 break; 617 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 618 // 17h. All processors are manufactured using the 45 nm process. 619 // 620 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 621 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 622 // the 45 nm process. 623 *Type = X86::INTEL_CORE2; // "penryn" 624 *Subtype = X86::INTEL_CORE2_45; 625 break; 626 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 627 // processors are manufactured using the 45 nm process. 628 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 629 // As found in a Summer 2010 model iMac. 630 case 0x1f: 631 case 0x2e: // Nehalem EX 632 *Type = X86::INTEL_COREI7; // "nehalem" 633 *Subtype = X86::INTEL_COREI7_NEHALEM; 634 break; 635 case 0x25: // Intel Core i7, laptop version. 636 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 637 // processors are manufactured using the 32 nm process. 638 case 0x2f: // Westmere EX 639 *Type = X86::INTEL_COREI7; // "westmere" 640 *Subtype = X86::INTEL_COREI7_WESTMERE; 641 break; 642 case 0x2a: // Intel Core i7 processor. All processors are manufactured 643 // using the 32 nm process. 644 case 0x2d: 645 *Type = X86::INTEL_COREI7; //"sandybridge" 646 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 647 break; 648 case 0x3a: 649 case 0x3e: // Ivy Bridge EP 650 *Type = X86::INTEL_COREI7; // "ivybridge" 651 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 652 break; 653 654 // Haswell: 655 case 0x3c: 656 case 0x3f: 657 case 0x45: 658 case 0x46: 659 *Type = X86::INTEL_COREI7; // "haswell" 660 *Subtype = X86::INTEL_COREI7_HASWELL; 661 break; 662 663 // Broadwell: 664 case 0x3d: 665 case 0x47: 666 case 0x4f: 667 case 0x56: 668 *Type = X86::INTEL_COREI7; // "broadwell" 669 *Subtype = X86::INTEL_COREI7_BROADWELL; 670 break; 671 672 // Skylake: 673 case 0x4e: // Skylake mobile 674 case 0x5e: // Skylake desktop 675 case 0x8e: // Kaby Lake mobile 676 case 0x9e: // Kaby Lake desktop 677 *Type = X86::INTEL_COREI7; // "skylake" 678 *Subtype = X86::INTEL_COREI7_SKYLAKE; 679 break; 680 681 // Skylake Xeon: 682 case 0x55: 683 *Type = X86::INTEL_COREI7; 684 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) 685 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 686 else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 687 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 688 else 689 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 690 break; 691 692 // Cannonlake: 693 case 0x66: 694 *Type = X86::INTEL_COREI7; 695 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 696 break; 697 698 // Icelake: 699 case 0x7d: 700 case 0x7e: 701 *Type = X86::INTEL_COREI7; 702 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 703 break; 704 705 // Icelake Xeon: 706 case 0x6a: 707 case 0x6c: 708 *Type = X86::INTEL_COREI7; 709 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 710 break; 711 712 case 0x1c: // Most 45 nm Intel Atom processors 713 case 0x26: // 45 nm Atom Lincroft 714 case 0x27: // 32 nm Atom Medfield 715 case 0x35: // 32 nm Atom Midview 716 case 0x36: // 32 nm Atom Midview 717 *Type = X86::INTEL_BONNELL; 718 break; // "bonnell" 719 720 // Atom Silvermont codes from the Intel software optimization guide. 721 case 0x37: 722 case 0x4a: 723 case 0x4d: 724 case 0x5a: 725 case 0x5d: 726 case 0x4c: // really airmont 727 *Type = X86::INTEL_SILVERMONT; 728 break; // "silvermont" 729 // Goldmont: 730 case 0x5c: // Apollo Lake 731 case 0x5f: // Denverton 732 *Type = X86::INTEL_GOLDMONT; 733 break; // "goldmont" 734 case 0x7a: 735 *Type = X86::INTEL_GOLDMONT_PLUS; 736 break; 737 case 0x86: 738 *Type = X86::INTEL_TREMONT; 739 break; 740 741 case 0x57: 742 *Type = X86::INTEL_KNL; // knl 743 break; 744 745 case 0x85: 746 *Type = X86::INTEL_KNM; // knm 747 break; 748 749 default: // Unknown family 6 CPU, try to guess. 750 // TODO detect tigerlake host 751 if (Features3 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 64))) { 752 *Type = X86::INTEL_COREI7; 753 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 754 break; 755 } 756 757 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 758 *Type = X86::INTEL_COREI7; 759 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 760 break; 761 } 762 763 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 764 *Type = X86::INTEL_COREI7; 765 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 766 break; 767 } 768 769 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) { 770 *Type = X86::INTEL_COREI7; 771 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 772 break; 773 } 774 775 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 776 *Type = X86::INTEL_COREI7; 777 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 778 break; 779 } 780 781 if (Features & (1 << X86::FEATURE_AVX512VL)) { 782 *Type = X86::INTEL_COREI7; 783 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 784 break; 785 } 786 787 if (Features & (1 << X86::FEATURE_AVX512ER)) { 788 *Type = X86::INTEL_KNL; // knl 789 break; 790 } 791 792 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 793 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 794 *Type = X86::INTEL_GOLDMONT; 795 } else { 796 *Type = X86::INTEL_COREI7; 797 *Subtype = X86::INTEL_COREI7_SKYLAKE; 798 } 799 break; 800 } 801 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 802 *Type = X86::INTEL_COREI7; 803 *Subtype = X86::INTEL_COREI7_BROADWELL; 804 break; 805 } 806 if (Features & (1 << X86::FEATURE_AVX2)) { 807 *Type = X86::INTEL_COREI7; 808 *Subtype = X86::INTEL_COREI7_HASWELL; 809 break; 810 } 811 if (Features & (1 << X86::FEATURE_AVX)) { 812 *Type = X86::INTEL_COREI7; 813 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 814 break; 815 } 816 if (Features & (1 << X86::FEATURE_SSE4_2)) { 817 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 818 *Type = X86::INTEL_SILVERMONT; 819 } else { 820 *Type = X86::INTEL_COREI7; 821 *Subtype = X86::INTEL_COREI7_NEHALEM; 822 } 823 break; 824 } 825 if (Features & (1 << X86::FEATURE_SSE4_1)) { 826 *Type = X86::INTEL_CORE2; // "penryn" 827 *Subtype = X86::INTEL_CORE2_45; 828 break; 829 } 830 if (Features & (1 << X86::FEATURE_SSSE3)) { 831 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 832 *Type = X86::INTEL_BONNELL; // "bonnell" 833 } else { 834 *Type = X86::INTEL_CORE2; // "core2" 835 *Subtype = X86::INTEL_CORE2_65; 836 } 837 break; 838 } 839 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 840 *Type = X86::INTEL_CORE2; // "core2" 841 *Subtype = X86::INTEL_CORE2_65; 842 break; 843 } 844 if (Features & (1 << X86::FEATURE_SSE3)) { 845 *Type = X86::INTEL_CORE_DUO; 846 break; 847 } 848 if (Features & (1 << X86::FEATURE_SSE2)) { 849 *Type = X86::INTEL_PENTIUM_M; 850 break; 851 } 852 if (Features & (1 << X86::FEATURE_SSE)) { 853 *Type = X86::INTEL_PENTIUM_III; 854 break; 855 } 856 if (Features & (1 << X86::FEATURE_MMX)) { 857 *Type = X86::INTEL_PENTIUM_II; 858 break; 859 } 860 *Type = X86::INTEL_PENTIUM_PRO; 861 break; 862 } 863 break; 864 case 15: { 865 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 866 *Type = X86::INTEL_NOCONA; 867 break; 868 } 869 if (Features & (1 << X86::FEATURE_SSE3)) { 870 *Type = X86::INTEL_PRESCOTT; 871 break; 872 } 873 *Type = X86::INTEL_PENTIUM_IV; 874 break; 875 } 876 default: 877 break; /*"generic"*/ 878 } 879} 880 881static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 882 unsigned Features, unsigned *Type, 883 unsigned *Subtype) { 884 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 885 // appears to be no way to generate the wide variety of AMD-specific targets 886 // from the information returned from CPUID. 887 switch (Family) { 888 case 4: 889 *Type = X86::AMD_i486; 890 break; 891 case 5: 892 *Type = X86::AMDPENTIUM; 893 switch (Model) { 894 case 6: 895 case 7: 896 *Subtype = X86::AMDPENTIUM_K6; 897 break; // "k6" 898 case 8: 899 *Subtype = X86::AMDPENTIUM_K62; 900 break; // "k6-2" 901 case 9: 902 case 13: 903 *Subtype = X86::AMDPENTIUM_K63; 904 break; // "k6-3" 905 case 10: 906 *Subtype = X86::AMDPENTIUM_GEODE; 907 break; // "geode" 908 } 909 break; 910 case 6: 911 if (Features & (1 << X86::FEATURE_SSE)) { 912 *Type = X86::AMD_ATHLON_XP; 913 break; // "athlon-xp" 914 } 915 *Type = X86::AMD_ATHLON; 916 break; // "athlon" 917 case 15: 918 if (Features & (1 << X86::FEATURE_SSE3)) { 919 *Type = X86::AMD_K8SSE3; 920 break; // "k8-sse3" 921 } 922 *Type = X86::AMD_K8; 923 break; // "k8" 924 case 16: 925 *Type = X86::AMDFAM10H; // "amdfam10" 926 switch (Model) { 927 case 2: 928 *Subtype = X86::AMDFAM10H_BARCELONA; 929 break; 930 case 4: 931 *Subtype = X86::AMDFAM10H_SHANGHAI; 932 break; 933 case 8: 934 *Subtype = X86::AMDFAM10H_ISTANBUL; 935 break; 936 } 937 break; 938 case 20: 939 *Type = X86::AMD_BTVER1; 940 break; // "btver1"; 941 case 21: 942 *Type = X86::AMDFAM15H; 943 if (Model >= 0x60 && Model <= 0x7f) { 944 *Subtype = X86::AMDFAM15H_BDVER4; 945 break; // "bdver4"; 60h-7Fh: Excavator 946 } 947 if (Model >= 0x30 && Model <= 0x3f) { 948 *Subtype = X86::AMDFAM15H_BDVER3; 949 break; // "bdver3"; 30h-3Fh: Steamroller 950 } 951 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 952 *Subtype = X86::AMDFAM15H_BDVER2; 953 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 954 } 955 if (Model <= 0x0f) { 956 *Subtype = X86::AMDFAM15H_BDVER1; 957 break; // "bdver1"; 00h-0Fh: Bulldozer 958 } 959 break; 960 case 22: 961 *Type = X86::AMD_BTVER2; 962 break; // "btver2" 963 case 23: 964 *Type = X86::AMDFAM17H; 965 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 966 *Subtype = X86::AMDFAM17H_ZNVER2; 967 break; // "znver2"; 30h-3fh, 71h: Zen2 968 } 969 if (Model <= 0x0f) { 970 *Subtype = X86::AMDFAM17H_ZNVER1; 971 break; // "znver1"; 00h-0Fh: Zen1 972 } 973 break; 974 default: 975 break; // "generic" 976 } 977} 978 979static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 980 unsigned *FeaturesOut, unsigned *Features2Out, 981 unsigned *Features3Out) { 982 unsigned Features = 0; 983 unsigned Features2 = 0; 984 unsigned Features3 = 0; 985 unsigned EAX, EBX; 986 987 auto setFeature = [&](unsigned F) { 988 if (F < 32) 989 Features |= 1U << (F & 0x1f); 990 else if (F < 64) 991 Features2 |= 1U << ((F - 32) & 0x1f); 992 else if (F < 96) 993 Features3 |= 1U << ((F - 64) & 0x1f); 994 else 995 llvm_unreachable("Unexpected FeatureBit"); 996 }; 997 998 if ((EDX >> 15) & 1) 999 setFeature(X86::FEATURE_CMOV); 1000 if ((EDX >> 23) & 1) 1001 setFeature(X86::FEATURE_MMX); 1002 if ((EDX >> 25) & 1) 1003 setFeature(X86::FEATURE_SSE); 1004 if ((EDX >> 26) & 1) 1005 setFeature(X86::FEATURE_SSE2); 1006 1007 if ((ECX >> 0) & 1) 1008 setFeature(X86::FEATURE_SSE3); 1009 if ((ECX >> 1) & 1) 1010 setFeature(X86::FEATURE_PCLMUL); 1011 if ((ECX >> 9) & 1) 1012 setFeature(X86::FEATURE_SSSE3); 1013 if ((ECX >> 12) & 1) 1014 setFeature(X86::FEATURE_FMA); 1015 if ((ECX >> 19) & 1) 1016 setFeature(X86::FEATURE_SSE4_1); 1017 if ((ECX >> 20) & 1) 1018 setFeature(X86::FEATURE_SSE4_2); 1019 if ((ECX >> 23) & 1) 1020 setFeature(X86::FEATURE_POPCNT); 1021 if ((ECX >> 25) & 1) 1022 setFeature(X86::FEATURE_AES); 1023 1024 if ((ECX >> 22) & 1) 1025 setFeature(X86::FEATURE_MOVBE); 1026 1027 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1028 // indicates that the AVX registers will be saved and restored on context 1029 // switch, then we have full AVX support. 1030 const unsigned AVXBits = (1 << 27) | (1 << 28); 1031 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1032 ((EAX & 0x6) == 0x6); 1033#if defined(__APPLE__) 1034 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1035 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1036 // set right now. 1037 bool HasAVX512Save = true; 1038#else 1039 // AVX512 requires additional context to be saved by the OS. 1040 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1041#endif 1042 1043 if (HasAVX) 1044 setFeature(X86::FEATURE_AVX); 1045 1046 bool HasLeaf7 = 1047 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1048 1049 if (HasLeaf7 && ((EBX >> 3) & 1)) 1050 setFeature(X86::FEATURE_BMI); 1051 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1052 setFeature(X86::FEATURE_AVX2); 1053 if (HasLeaf7 && ((EBX >> 8) & 1)) 1054 setFeature(X86::FEATURE_BMI2); 1055 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1056 setFeature(X86::FEATURE_AVX512F); 1057 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1058 setFeature(X86::FEATURE_AVX512DQ); 1059 if (HasLeaf7 && ((EBX >> 19) & 1)) 1060 setFeature(X86::FEATURE_ADX); 1061 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1062 setFeature(X86::FEATURE_AVX512IFMA); 1063 if (HasLeaf7 && ((EBX >> 23) & 1)) 1064 setFeature(X86::FEATURE_CLFLUSHOPT); 1065 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1066 setFeature(X86::FEATURE_AVX512PF); 1067 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1068 setFeature(X86::FEATURE_AVX512ER); 1069 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1070 setFeature(X86::FEATURE_AVX512CD); 1071 if (HasLeaf7 && ((EBX >> 29) & 1)) 1072 setFeature(X86::FEATURE_SHA); 1073 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1074 setFeature(X86::FEATURE_AVX512BW); 1075 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1076 setFeature(X86::FEATURE_AVX512VL); 1077 1078 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1079 setFeature(X86::FEATURE_AVX512VBMI); 1080 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1081 setFeature(X86::FEATURE_AVX512VBMI2); 1082 if (HasLeaf7 && ((ECX >> 8) & 1)) 1083 setFeature(X86::FEATURE_GFNI); 1084 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1085 setFeature(X86::FEATURE_VPCLMULQDQ); 1086 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1087 setFeature(X86::FEATURE_AVX512VNNI); 1088 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1089 setFeature(X86::FEATURE_AVX512BITALG); 1090 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1091 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1092 1093 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1094 setFeature(X86::FEATURE_AVX5124VNNIW); 1095 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1096 setFeature(X86::FEATURE_AVX5124FMAPS); 1097 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1098 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1099 1100 bool HasLeaf7Subleaf1 = 1101 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1102 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1103 setFeature(X86::FEATURE_AVX512BF16); 1104 1105 unsigned MaxExtLevel; 1106 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1107 1108 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1109 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1110 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1111 setFeature(X86::FEATURE_SSE4_A); 1112 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1113 setFeature(X86::FEATURE_XOP); 1114 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1115 setFeature(X86::FEATURE_FMA4); 1116 1117 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1118 setFeature(X86::FEATURE_EM64T); 1119 1120 *FeaturesOut = Features; 1121 *Features2Out = Features2; 1122 *Features3Out = Features3; 1123} 1124 1125StringRef sys::getHostCPUName() { 1126 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1127 unsigned MaxLeaf, Vendor; 1128 1129#if defined(__GNUC__) || defined(__clang__) 1130 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1131 // and simplify it to not invoke __cpuid (like cpu_model.c in 1132 // compiler-rt/lib/builtins/cpu_model.c? 1133 // Opting for the second option. 1134 if(!isCpuIdSupported()) 1135 return "generic"; 1136#endif 1137 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1138 return "generic"; 1139 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1140 1141 unsigned Brand_id = EBX & 0xff; 1142 unsigned Family = 0, Model = 0; 1143 unsigned Features = 0, Features2 = 0, Features3 = 0; 1144 detectX86FamilyModel(EAX, &Family, &Model); 1145 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1146 1147 unsigned Type = 0; 1148 unsigned Subtype = 0; 1149 1150 if (Vendor == SIG_INTEL) { 1151 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1152 Features2, Features3, &Type, &Subtype); 1153 } else if (Vendor == SIG_AMD) { 1154 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1155 } 1156 1157 // Check subtypes first since those are more specific. 1158#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1159 if (Subtype == X86::ENUM) \ 1160 return ARCHNAME; 1161#include "llvm/Support/X86TargetParser.def" 1162 1163 // Now check types. 1164#define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1165 if (Type == X86::ENUM) \ 1166 return ARCHNAME; 1167#include "llvm/Support/X86TargetParser.def" 1168 1169 return "generic"; 1170} 1171 1172#elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1173StringRef sys::getHostCPUName() { 1174 host_basic_info_data_t hostInfo; 1175 mach_msg_type_number_t infoCount; 1176 1177 infoCount = HOST_BASIC_INFO_COUNT; 1178 mach_port_t hostPort = mach_host_self(); 1179 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1180 &infoCount); 1181 mach_port_deallocate(mach_task_self(), hostPort); 1182 1183 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1184 return "generic"; 1185 1186 switch (hostInfo.cpu_subtype) { 1187 case CPU_SUBTYPE_POWERPC_601: 1188 return "601"; 1189 case CPU_SUBTYPE_POWERPC_602: 1190 return "602"; 1191 case CPU_SUBTYPE_POWERPC_603: 1192 return "603"; 1193 case CPU_SUBTYPE_POWERPC_603e: 1194 return "603e"; 1195 case CPU_SUBTYPE_POWERPC_603ev: 1196 return "603ev"; 1197 case CPU_SUBTYPE_POWERPC_604: 1198 return "604"; 1199 case CPU_SUBTYPE_POWERPC_604e: 1200 return "604e"; 1201 case CPU_SUBTYPE_POWERPC_620: 1202 return "620"; 1203 case CPU_SUBTYPE_POWERPC_750: 1204 return "750"; 1205 case CPU_SUBTYPE_POWERPC_7400: 1206 return "7400"; 1207 case CPU_SUBTYPE_POWERPC_7450: 1208 return "7450"; 1209 case CPU_SUBTYPE_POWERPC_970: 1210 return "970"; 1211 default:; 1212 } 1213 1214 return "generic"; 1215} 1216#elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1217StringRef sys::getHostCPUName() { 1218 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1219 StringRef Content = P ? P->getBuffer() : ""; 1220 return detail::getHostCPUNameForPowerPC(Content); 1221} 1222#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1223StringRef sys::getHostCPUName() { 1224 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1225 StringRef Content = P ? P->getBuffer() : ""; 1226 return detail::getHostCPUNameForARM(Content); 1227} 1228#elif defined(__linux__) && defined(__s390x__) 1229StringRef sys::getHostCPUName() { 1230 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1231 StringRef Content = P ? P->getBuffer() : ""; 1232 return detail::getHostCPUNameForS390x(Content); 1233} 1234#elif defined(__APPLE__) && defined(__aarch64__) 1235StringRef sys::getHostCPUName() { 1236 return "cyclone"; 1237} 1238#elif defined(__APPLE__) && defined(__arm__) 1239StringRef sys::getHostCPUName() { 1240 host_basic_info_data_t hostInfo; 1241 mach_msg_type_number_t infoCount; 1242 1243 infoCount = HOST_BASIC_INFO_COUNT; 1244 mach_port_t hostPort = mach_host_self(); 1245 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1246 &infoCount); 1247 mach_port_deallocate(mach_task_self(), hostPort); 1248 1249 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1250 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1251 return "generic"; 1252 } 1253 switch (hostInfo.cpu_subtype) { 1254 case CPU_SUBTYPE_ARM_V7S: 1255 return "swift"; 1256 default:; 1257 } 1258 1259 return "generic"; 1260} 1261#else 1262StringRef sys::getHostCPUName() { return "generic"; } 1263#endif 1264 1265#if defined(__linux__) && defined(__x86_64__) 1266// On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1267// using the number of unique physical/core id pairs. The following 1268// implementation reads the /proc/cpuinfo format on an x86_64 system. 1269static int computeHostNumPhysicalCores() { 1270 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1271 // mmapped because it appears to have 0 size. 1272 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1273 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1274 if (std::error_code EC = Text.getError()) { 1275 llvm::errs() << "Can't read " 1276 << "/proc/cpuinfo: " << EC.message() << "\n"; 1277 return -1; 1278 } 1279 SmallVector<StringRef, 8> strs; 1280 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1281 /*KeepEmpty=*/false); 1282 int CurPhysicalId = -1; 1283 int CurCoreId = -1; 1284 SmallSet<std::pair<int, int>, 32> UniqueItems; 1285 for (auto &Line : strs) { 1286 Line = Line.trim(); 1287 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1288 continue; 1289 std::pair<StringRef, StringRef> Data = Line.split(':'); 1290 auto Name = Data.first.trim(); 1291 auto Val = Data.second.trim(); 1292 if (Name == "physical id") { 1293 assert(CurPhysicalId == -1 && 1294 "Expected a core id before seeing another physical id"); 1295 Val.getAsInteger(10, CurPhysicalId); 1296 } 1297 if (Name == "core id") { 1298 assert(CurCoreId == -1 && 1299 "Expected a physical id before seeing another core id"); 1300 Val.getAsInteger(10, CurCoreId); 1301 } 1302 if (CurPhysicalId != -1 && CurCoreId != -1) { 1303 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1304 CurPhysicalId = -1; 1305 CurCoreId = -1; 1306 } 1307 } 1308 return UniqueItems.size(); 1309} 1310#elif defined(__APPLE__) && defined(__x86_64__) 1311#include <sys/param.h> 1312#include <sys/sysctl.h> 1313 1314// Gets the number of *physical cores* on the machine. 1315static int computeHostNumPhysicalCores() { 1316 uint32_t count; 1317 size_t len = sizeof(count); 1318 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1319 if (count < 1) { 1320 int nm[2]; 1321 nm[0] = CTL_HW; 1322 nm[1] = HW_AVAILCPU; 1323 sysctl(nm, 2, &count, &len, NULL, 0); 1324 if (count < 1) 1325 return -1; 1326 } 1327 return count; 1328} 1329#else 1330// On other systems, return -1 to indicate unknown. 1331static int computeHostNumPhysicalCores() { return -1; } 1332#endif 1333 1334int sys::getHostNumPhysicalCores() { 1335 static int NumCores = computeHostNumPhysicalCores(); 1336 return NumCores; 1337} 1338 1339#if defined(__i386__) || defined(_M_IX86) || \ 1340 defined(__x86_64__) || defined(_M_X64) 1341bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1342 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1343 unsigned MaxLevel; 1344 union { 1345 unsigned u[3]; 1346 char c[12]; 1347 } text; 1348 1349 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1350 MaxLevel < 1) 1351 return false; 1352 1353 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1354 1355 Features["cx8"] = (EDX >> 8) & 1; 1356 Features["cmov"] = (EDX >> 15) & 1; 1357 Features["mmx"] = (EDX >> 23) & 1; 1358 Features["fxsr"] = (EDX >> 24) & 1; 1359 Features["sse"] = (EDX >> 25) & 1; 1360 Features["sse2"] = (EDX >> 26) & 1; 1361 1362 Features["sse3"] = (ECX >> 0) & 1; 1363 Features["pclmul"] = (ECX >> 1) & 1; 1364 Features["ssse3"] = (ECX >> 9) & 1; 1365 Features["cx16"] = (ECX >> 13) & 1; 1366 Features["sse4.1"] = (ECX >> 19) & 1; 1367 Features["sse4.2"] = (ECX >> 20) & 1; 1368 Features["movbe"] = (ECX >> 22) & 1; 1369 Features["popcnt"] = (ECX >> 23) & 1; 1370 Features["aes"] = (ECX >> 25) & 1; 1371 Features["rdrnd"] = (ECX >> 30) & 1; 1372 1373 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1374 // indicates that the AVX registers will be saved and restored on context 1375 // switch, then we have full AVX support. 1376 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1377 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1378#if defined(__APPLE__) 1379 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1380 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1381 // set right now. 1382 bool HasAVX512Save = true; 1383#else 1384 // AVX512 requires additional context to be saved by the OS. 1385 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1386#endif 1387 1388 Features["avx"] = HasAVXSave; 1389 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1390 // Only enable XSAVE if OS has enabled support for saving YMM state. 1391 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1392 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1393 1394 unsigned MaxExtLevel; 1395 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1396 1397 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1398 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1399 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1400 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1401 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1402 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1403 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1404 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1405 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1406 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1407 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1408 1409 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1410 1411 // Miscellaneous memory related features, detected by 1412 // using the 0x80000008 leaf of the CPUID instruction 1413 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1414 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1415 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1416 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1417 1418 bool HasLeaf7 = 1419 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1420 1421 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1422 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1423 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1424 // AVX2 is only supported if we have the OS save support from AVX. 1425 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1426 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1427 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1428 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1429 // AVX512 is only supported if the OS supports the context save for it. 1430 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1431 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1432 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1433 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1434 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1435 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1436 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1437 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1438 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1439 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1440 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1441 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1442 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1443 1444 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1445 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1446 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1447 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1448 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1449 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1450 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1451 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1452 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1453 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1454 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1455 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1456 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1457 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1458 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1459 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1460 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1461 1462 // There are two CPUID leafs which information associated with the pconfig 1463 // instruction: 1464 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1465 // bit of EDX), while the EAX=0x1b leaf returns information on the 1466 // availability of specific pconfig leafs. 1467 // The target feature here only refers to the the first of these two. 1468 // Users might need to check for the availability of specific pconfig 1469 // leaves using cpuid, since that information is ignored while 1470 // detecting features using the "-march=native" flag. 1471 // For more info, see X86 ISA docs. 1472 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1473 bool HasLeaf7Subleaf1 = 1474 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1475 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1476 1477 bool HasLeafD = MaxLevel >= 0xd && 1478 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1479 1480 // Only enable XSAVE if OS has enabled support for saving YMM state. 1481 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1482 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1483 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1484 1485 bool HasLeaf14 = MaxLevel >= 0x14 && 1486 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1487 1488 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1489 1490 return true; 1491} 1492#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1493bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1494 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1495 if (!P) 1496 return false; 1497 1498 SmallVector<StringRef, 32> Lines; 1499 P->getBuffer().split(Lines, "\n"); 1500 1501 SmallVector<StringRef, 32> CPUFeatures; 1502 1503 // Look for the CPU features. 1504 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1505 if (Lines[I].startswith("Features")) { 1506 Lines[I].split(CPUFeatures, ' '); 1507 break; 1508 } 1509 1510#if defined(__aarch64__) 1511 // Keep track of which crypto features we have seen 1512 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1513 uint32_t crypto = 0; 1514#endif 1515 1516 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1517 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1518#if defined(__aarch64__) 1519 .Case("asimd", "neon") 1520 .Case("fp", "fp-armv8") 1521 .Case("crc32", "crc") 1522#else 1523 .Case("half", "fp16") 1524 .Case("neon", "neon") 1525 .Case("vfpv3", "vfp3") 1526 .Case("vfpv3d16", "d16") 1527 .Case("vfpv4", "vfp4") 1528 .Case("idiva", "hwdiv-arm") 1529 .Case("idivt", "hwdiv") 1530#endif 1531 .Default(""); 1532 1533#if defined(__aarch64__) 1534 // We need to check crypto separately since we need all of the crypto 1535 // extensions to enable the subtarget feature 1536 if (CPUFeatures[I] == "aes") 1537 crypto |= CAP_AES; 1538 else if (CPUFeatures[I] == "pmull") 1539 crypto |= CAP_PMULL; 1540 else if (CPUFeatures[I] == "sha1") 1541 crypto |= CAP_SHA1; 1542 else if (CPUFeatures[I] == "sha2") 1543 crypto |= CAP_SHA2; 1544#endif 1545 1546 if (LLVMFeatureStr != "") 1547 Features[LLVMFeatureStr] = true; 1548 } 1549 1550#if defined(__aarch64__) 1551 // If we have all crypto bits we can add the feature 1552 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1553 Features["crypto"] = true; 1554#endif 1555 1556 return true; 1557} 1558#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1559bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1560 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1561 Features["neon"] = true; 1562 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1563 Features["crc"] = true; 1564 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1565 Features["crypto"] = true; 1566 1567 return true; 1568} 1569#else 1570bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1571#endif 1572 1573std::string sys::getProcessTriple() { 1574 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1575 Triple PT(Triple::normalize(TargetTripleString)); 1576 1577 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1578 PT = PT.get64BitArchVariant(); 1579 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1580 PT = PT.get32BitArchVariant(); 1581 1582 return PT.str(); 1583} 1584