Context.cpp revision 343171 
1//===---------------------------- Context.cpp -------------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10///
11/// This file defines a class for holding ownership of various simulated
12/// hardware units.  A Context also provides a utility routine for constructing
13/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
14/// stages.
15///
16//===----------------------------------------------------------------------===//
17
18#include "llvm/MCA/Context.h"
19#include "llvm/MCA/HardwareUnits/RegisterFile.h"
20#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
21#include "llvm/MCA/HardwareUnits/Scheduler.h"
22#include "llvm/MCA/Stages/DispatchStage.h"
23#include "llvm/MCA/Stages/EntryStage.h"
24#include "llvm/MCA/Stages/ExecuteStage.h"
25#include "llvm/MCA/Stages/RetireStage.h"
26
27namespace llvm {
28namespace mca {
29
30std::unique_ptr<Pipeline>
31Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
32                               SourceMgr &SrcMgr) {
33  const MCSchedModel &SM = STI.getSchedModel();
34
35  // Create the hardware units defining the backend.
36  auto RCU = llvm::make_unique<RetireControlUnit>(SM);
37  auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
38  auto LSU = llvm::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
39                                       Opts.StoreQueueSize, Opts.AssumeNoAlias);
40  auto HWS = llvm::make_unique<Scheduler>(SM, *LSU);
41
42  // Create the pipeline stages.
43  auto Fetch = llvm::make_unique<EntryStage>(SrcMgr);
44  auto Dispatch = llvm::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
45                                                   *RCU, *PRF);
46  auto Execute = llvm::make_unique<ExecuteStage>(*HWS);
47  auto Retire = llvm::make_unique<RetireStage>(*RCU, *PRF);
48
49  // Pass the ownership of all the hardware units to this Context.
50  addHardwareUnit(std::move(RCU));
51  addHardwareUnit(std::move(PRF));
52  addHardwareUnit(std::move(LSU));
53  addHardwareUnit(std::move(HWS));
54
55  // Build the pipeline.
56  auto StagePipeline = llvm::make_unique<Pipeline>();
57  StagePipeline->appendStage(std::move(Fetch));
58  StagePipeline->appendStage(std::move(Dispatch));
59  StagePipeline->appendStage(std::move(Execute));
60  StagePipeline->appendStage(std::move(Retire));
61  return StagePipeline;
62}
63
64} // namespace mca
65} // namespace llvm
66