1//===-- RegisterContextPOSIXCore_mips64.cpp ---------------------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9#include "RegisterContextPOSIXCore_mips64.h" 10 11#include "lldb/Target/Thread.h" 12#include "lldb/Utility/RegisterValue.h" 13 14#include <memory> 15 16using namespace lldb_private; 17 18RegisterContextCorePOSIX_mips64::RegisterContextCorePOSIX_mips64( 19 Thread &thread, RegisterInfoInterface *register_info, 20 const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes) 21 : RegisterContextPOSIX_mips64(thread, 0, register_info) { 22 m_gpr_buffer = std::make_shared<DataBufferHeap>(gpregset.GetDataStart(), 23 gpregset.GetByteSize()); 24 m_gpr.SetData(m_gpr_buffer); 25 m_gpr.SetByteOrder(gpregset.GetByteOrder()); 26 27 DataExtractor fpregset = getRegset( 28 notes, register_info->GetTargetArchitecture().GetTriple(), FPR_Desc); 29 m_fpr_buffer = std::make_shared<DataBufferHeap>(fpregset.GetDataStart(), 30 fpregset.GetByteSize()); 31 m_fpr.SetData(m_fpr_buffer); 32 m_fpr.SetByteOrder(fpregset.GetByteOrder()); 33} 34 35RegisterContextCorePOSIX_mips64::~RegisterContextCorePOSIX_mips64() {} 36 37bool RegisterContextCorePOSIX_mips64::ReadGPR() { return true; } 38 39bool RegisterContextCorePOSIX_mips64::ReadFPR() { return false; } 40 41bool RegisterContextCorePOSIX_mips64::WriteGPR() { 42 assert(0); 43 return false; 44} 45 46bool RegisterContextCorePOSIX_mips64::WriteFPR() { 47 assert(0); 48 return false; 49} 50 51bool RegisterContextCorePOSIX_mips64::ReadRegister(const RegisterInfo *reg_info, 52 RegisterValue &value) { 53 54 lldb::offset_t offset = reg_info->byte_offset; 55 lldb_private::ArchSpec arch = m_register_info_up->GetTargetArchitecture(); 56 uint64_t v; 57 if (IsGPR(reg_info->kinds[lldb::eRegisterKindLLDB])) { 58 if (reg_info->byte_size == 4 && !(arch.GetMachine() == llvm::Triple::mips64el)) 59 // In case of 32bit core file, the register data are placed at 4 byte 60 // offset. 61 offset = offset / 2; 62 v = m_gpr.GetMaxU64(&offset, reg_info->byte_size); 63 value = v; 64 return true; 65 } else if (IsFPR(reg_info->kinds[lldb::eRegisterKindLLDB])) { 66 offset = offset - sizeof(GPR_linux_mips); 67 v =m_fpr.GetMaxU64(&offset, reg_info->byte_size); 68 value = v; 69 return true; 70 } 71 return false; 72} 73 74bool RegisterContextCorePOSIX_mips64::ReadAllRegisterValues( 75 lldb::DataBufferSP &data_sp) { 76 return false; 77} 78 79bool RegisterContextCorePOSIX_mips64::WriteRegister( 80 const RegisterInfo *reg_info, const RegisterValue &value) { 81 return false; 82} 83 84bool RegisterContextCorePOSIX_mips64::WriteAllRegisterValues( 85 const lldb::DataBufferSP &data_sp) { 86 return false; 87} 88 89bool RegisterContextCorePOSIX_mips64::HardwareSingleStep(bool enable) { 90 return false; 91} 92