1//===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares Hexagon TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
15
16#include "clang/Basic/TargetInfo.h"
17#include "clang/Basic/TargetOptions.h"
18#include "llvm/ADT/Triple.h"
19#include "llvm/Support/Compiler.h"
20
21namespace clang {
22namespace targets {
23
24// Hexagon abstract base class
25class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
26
27  static const Builtin::Info BuiltinInfo[];
28  static const char *const GCCRegNames[];
29  static const TargetInfo::GCCRegAlias GCCRegAliases[];
30  std::string CPU;
31  std::string HVXVersion;
32  bool HasHVX = false;
33  bool HasHVX64B = false;
34  bool HasHVX128B = false;
35  bool UseLongCalls = false;
36
37public:
38  HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
39      : TargetInfo(Triple) {
40    // Specify the vector alignment explicitly. For v512x1, the calculated
41    // alignment would be 512*alignment(i1), which is 512 bytes, instead of
42    // the required minimum of 64 bytes.
43    resetDataLayout(
44        "e-m:e-p:32:32:32-a:0-n16:32-"
45        "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
46        "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
47    SizeType = UnsignedInt;
48    PtrDiffType = SignedInt;
49    IntPtrType = SignedInt;
50
51    // {} in inline assembly are packet specifiers, not assembly variant
52    // specifiers.
53    NoAsmVariants = true;
54
55    LargeArrayMinWidth = 64;
56    LargeArrayAlign = 64;
57    UseBitFieldTypeAlignment = true;
58    ZeroLengthBitfieldBoundary = 32;
59  }
60
61  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
62
63  bool validateAsmConstraint(const char *&Name,
64                             TargetInfo::ConstraintInfo &Info) const override {
65    switch (*Name) {
66    case 'v':
67    case 'q':
68      if (HasHVX) {
69        Info.setAllowsRegister();
70        return true;
71      }
72      break;
73    case 'a': // Modifier register m0-m1.
74      Info.setAllowsRegister();
75      return true;
76    case 's':
77      // Relocatable constant.
78      return true;
79    }
80    return false;
81  }
82
83  void getTargetDefines(const LangOptions &Opts,
84                        MacroBuilder &Builder) const override;
85
86  bool isCLZForZeroUndef() const override { return false; }
87
88  bool hasFeature(StringRef Feature) const override;
89
90  bool
91  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
92                 StringRef CPU,
93                 const std::vector<std::string> &FeaturesVec) const override;
94
95  bool handleTargetFeatures(std::vector<std::string> &Features,
96                            DiagnosticsEngine &Diags) override;
97
98  BuiltinVaListKind getBuiltinVaListKind() const override {
99    return TargetInfo::CharPtrBuiltinVaList;
100  }
101
102  ArrayRef<const char *> getGCCRegNames() const override;
103
104  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
105
106  const char *getClobbers() const override { return ""; }
107
108  static const char *getHexagonCPUSuffix(StringRef Name);
109
110  bool isValidCPUName(StringRef Name) const override {
111    return getHexagonCPUSuffix(Name);
112  }
113
114  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
115
116  bool setCPU(const std::string &Name) override {
117    if (!isValidCPUName(Name))
118      return false;
119    CPU = Name;
120    return true;
121  }
122
123  int getEHDataRegisterNumber(unsigned RegNo) const override {
124    return RegNo < 2 ? RegNo : -1;
125  }
126};
127} // namespace targets
128} // namespace clang
129#endif // LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
130