1;; Scheduling description for IBM RS64 processors.
2;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5
6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published
8;; by the Free Software Foundation; either version 2, or (at your
9;; option) any later version.
10
11;; GCC is distributed in the hope that it will be useful, but WITHOUT
12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14;; License for more details.
15
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING.  If not, write to the
18;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19;; MA 02110-1301, USA.
20
21(define_automaton "rs64,rs64fp")
22(define_cpu_unit "iu_rs64" "rs64")
23(define_cpu_unit "mciu_rs64" "rs64")
24(define_cpu_unit "fpu_rs64" "rs64fp")
25(define_cpu_unit "lsu_rs64,bpu_rs64" "rs64")
26
27;; RS64a 64-bit IU, LSU, FPU, BPU
28
29(define_insn_reservation "rs64a-load" 2
30  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
31       (eq_attr "cpu" "rs64a"))
32  "lsu_rs64")
33
34(define_insn_reservation "rs64a-store" 2
35  (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
36       (eq_attr "cpu" "rs64a"))
37  "lsu_rs64")
38
39(define_insn_reservation "rs64a-fpload" 3
40  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
41       (eq_attr "cpu" "rs64a"))
42  "lsu_rs64")
43
44(define_insn_reservation "rs64a-llsc" 2
45  (and (eq_attr "type" "load_l,store_c")
46       (eq_attr "cpu" "rs64a"))
47  "lsu_rs64")
48
49(define_insn_reservation "rs64a-integer" 1
50  (and (eq_attr "type" "integer,insert_word")
51       (eq_attr "cpu" "rs64a"))
52  "iu_rs64")
53
54(define_insn_reservation "rs64a-two" 1
55  (and (eq_attr "type" "two")
56       (eq_attr "cpu" "rs64a"))
57  "iu_rs64,iu_rs64")
58
59(define_insn_reservation "rs64a-three" 1
60  (and (eq_attr "type" "three")
61       (eq_attr "cpu" "rs64a"))
62  "iu_rs64,iu_rs64,iu_rs64")
63
64(define_insn_reservation "rs64a-imul" 20
65  (and (eq_attr "type" "imul,imul_compare")
66       (eq_attr "cpu" "rs64a"))
67  "mciu_rs64*13")
68
69(define_insn_reservation "rs64a-imul2" 12
70  (and (eq_attr "type" "imul2")
71       (eq_attr "cpu" "rs64a"))
72  "mciu_rs64*5")
73
74(define_insn_reservation "rs64a-imul3" 8
75  (and (eq_attr "type" "imul3")
76       (eq_attr "cpu" "rs64a"))
77  "mciu_rs64*2")
78
79(define_insn_reservation "rs64a-lmul" 34
80  (and (eq_attr "type" "lmul,lmul_compare")
81       (eq_attr "cpu" "rs64a"))
82  "mciu_rs64*34")
83
84(define_insn_reservation "rs64a-idiv" 66
85  (and (eq_attr "type" "idiv")
86       (eq_attr "cpu" "rs64a"))
87  "mciu_rs64*66")
88
89(define_insn_reservation "rs64a-ldiv" 66
90  (and (eq_attr "type" "ldiv")
91       (eq_attr "cpu" "rs64a"))
92  "mciu_rs64*66")
93
94(define_insn_reservation "rs64a-compare" 3
95  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
96       (eq_attr "cpu" "rs64a"))
97  "iu_rs64,nothing,bpu_rs64")
98
99(define_insn_reservation "rs64a-fpcompare" 5
100  (and (eq_attr "type" "fpcompare")
101       (eq_attr "cpu" "rs64a"))
102  "mciu_rs64,fpu_rs64,bpu_rs64")
103
104(define_insn_reservation "rs64a-fp" 4
105  (and (eq_attr "type" "fp,dmul")
106       (eq_attr "cpu" "rs64a"))
107  "mciu_rs64,fpu_rs64")
108
109(define_insn_reservation "rs64a-sdiv" 31
110  (and (eq_attr "type" "sdiv,ddiv")
111       (eq_attr "cpu" "rs64a"))
112  "mciu_rs64,fpu_rs64*31")
113
114(define_insn_reservation "rs64a-sqrt" 49
115  (and (eq_attr "type" "ssqrt,dsqrt")
116       (eq_attr "cpu" "rs64a"))
117  "mciu_rs64,fpu_rs64*49")
118
119(define_insn_reservation "rs64a-mfcr" 2
120  (and (eq_attr "type" "mfcr")
121       (eq_attr "cpu" "rs64a"))
122  "lsu_rs64")
123
124(define_insn_reservation "rs64a-mtcr" 3
125  (and (eq_attr "type" "mtcr")
126       (eq_attr "cpu" "rs64a"))
127  "lsu_rs64")
128
129(define_insn_reservation "rs64a-mtjmpr" 3
130  (and (eq_attr "type" "mtjmpr")
131       (eq_attr "cpu" "rs64a"))
132  "lsu_rs64")
133
134(define_insn_reservation "rs64a-mfjmpr" 2
135  (and (eq_attr "type" "mfjmpr")
136       (eq_attr "cpu" "rs64a"))
137  "lsu_rs64")
138
139(define_insn_reservation "rs64a-jmpreg" 1
140  (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
141       (eq_attr "cpu" "rs64a"))
142  "bpu_rs64")
143
144(define_insn_reservation "rs64a-isync" 6
145  (and (eq_attr "type" "isync")
146       (eq_attr "cpu" "rs64a"))
147  "bpu_rs64")
148
149(define_insn_reservation "rs64a-sync" 1
150  (and (eq_attr "type" "sync")
151       (eq_attr "cpu" "rs64a"))
152  "lsu_rs64")
153
154