1;; Pipeline description for Motorola PowerPC 8540 processor.
2;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5
6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published
8;; by the Free Software Foundation; either version 2, or (at your
9;; option) any later version.
10
11;; GCC is distributed in the hope that it will be useful, but WITHOUT
12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14;; License for more details.
15
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING.  If not, write to the
18;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19;; MA 02110-1301, USA.
20
21(define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire")
22(define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
23
24;; We don't simulate general issue queue (GIC).  If we have SU insn
25;; and then SU1 insn, they cannot be issued on the same cycle
26;; (although SU1 insn and then SU insn can be issued) because the SU
27;; insn will go to SU1 from GIC0 entry.  Fortunately, the first cycle
28;; multipass insn scheduling will find the situation and issue the SU1
29;; insn and then the SU insn.
30(define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1"   "ppc8540_most")
31
32;; We could describe completion buffers slots in combination with the
33;; retirement units and the order of completion but the result
34;; automaton would behave in the same way because we cannot describe
35;; real latency time with taking in order completion into account.
36;; Actually we could define the real latency time by querying reserved
37;; automaton units but the current scheduler uses latency time before
38;; issuing insns and making any reservations.
39;;
40;; So our description is aimed to achieve a insn schedule in which the
41;; insns would not wait in the completion buffer.
42(define_cpu_unit "ppc8540_retire_0,ppc8540_retire_1" "ppc8540_retire")
43
44;; Branch unit:
45(define_cpu_unit "ppc8540_bu" "ppc8540_most")
46
47;; SU:
48(define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most")
49
50;; We could describe here MU subunits for float multiply, float add
51;; etc.  But the result automaton would behave the same way as the
52;; described one pipeline below because MU can start only one insn
53;; per cycle.  Actually we could simplify the automaton more not
54;; describing stages 1-3, the result automata would be the same.
55(define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most")
56(define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most")
57
58;; The following unit is used to describe non-pipelined division.
59(define_cpu_unit "ppc8540_mu_div" "ppc8540_long")
60
61;; Here we simplified LSU unit description not describing the stages.
62(define_cpu_unit "ppc8540_lsu" "ppc8540_most")
63
64;; The following units are used to make automata deterministic
65(define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most")
66(define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most")
67(define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire")
68(define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most")
69
70;; The following sets to make automata deterministic when option ndfa is used.
71(presence_set "present_ppc8540_decode_0" "ppc8540_decode_0")
72(presence_set "present_ppc8540_issue_0" "ppc8540_issue_0")
73(presence_set "present_ppc8540_retire_0" "ppc8540_retire_0")
74(presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0")
75
76;; Some useful abbreviations.
77(define_reservation "ppc8540_decode"
78    "ppc8540_decode_0|ppc8540_decode_1+present_ppc8540_decode_0")
79(define_reservation "ppc8540_issue"
80    "ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0")
81(define_reservation "ppc8540_retire"
82   "ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0")
83(define_reservation "ppc8540_su_stage0"
84   "ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0")
85
86;; Simple SU insns
87(define_insn_reservation "ppc8540_su" 1
88  (and (eq_attr "type" "integer,insert_word,cmp,compare,delayed_compare,fast_compare")
89       (eq_attr "cpu" "ppc8540"))
90  "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
91
92(define_insn_reservation "ppc8540_two" 1
93  (and (eq_attr "type" "two")
94       (eq_attr "cpu" "ppc8540"))
95  "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
96   ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
97
98(define_insn_reservation "ppc8540_three" 1
99  (and (eq_attr "type" "three")
100       (eq_attr "cpu" "ppc8540"))
101  "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
102   ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
103   ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
104
105;; Branch.  Actually this latency time is not used by the scheduler.
106(define_insn_reservation "ppc8540_branch" 1
107  (and (eq_attr "type" "jmpreg,branch,isync")
108       (eq_attr "cpu" "ppc8540"))
109  "ppc8540_decode,ppc8540_bu,ppc8540_retire")
110
111;; Multiply
112(define_insn_reservation "ppc8540_multiply" 4
113  (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
114       (eq_attr "cpu" "ppc8540"))
115  "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
116   ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
117
118;; Divide.  We use the average latency time here.  We omit reserving a
119;; retire unit because of the result automata will be huge.  We ignore
120;; reservation of miu_stage3 here because we use the average latency
121;; time.
122(define_insn_reservation "ppc8540_divide" 14
123  (and (eq_attr "type" "idiv")
124       (eq_attr "cpu" "ppc8540"))
125  "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
126   ppc8540_mu_div*13")
127
128;; CR logical
129(define_insn_reservation "ppc8540_cr_logical" 1
130  (and (eq_attr "type" "cr_logical,delayed_cr")
131       (eq_attr "cpu" "ppc8540"))
132  "ppc8540_decode,ppc8540_bu,ppc8540_retire")
133
134;; Mfcr
135(define_insn_reservation "ppc8540_mfcr" 1
136  (and (eq_attr "type" "mfcr")
137       (eq_attr "cpu" "ppc8540"))
138  "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
139
140;; Mtcrf
141(define_insn_reservation "ppc8540_mtcrf" 1
142  (and (eq_attr "type" "mtcr")
143       (eq_attr "cpu" "ppc8540"))
144  "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
145
146;; Mtjmpr
147(define_insn_reservation "ppc8540_mtjmpr" 1
148  (and (eq_attr "type" "mtjmpr,mfjmpr")
149       (eq_attr "cpu" "ppc8540"))
150  "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
151
152;; Loads
153(define_insn_reservation "ppc8540_load" 3
154  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
155			load_l,sync")
156       (eq_attr "cpu" "ppc8540"))
157  "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
158
159;; Stores.
160(define_insn_reservation "ppc8540_store" 3
161  (and (eq_attr "type" "store,store_ux,store_u,store_c")
162       (eq_attr "cpu" "ppc8540"))
163  "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
164
165;; Simple FP
166(define_insn_reservation "ppc8540_simple_float" 1
167  (and (eq_attr "type" "fpsimple")
168       (eq_attr "cpu" "ppc8540"))
169  "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
170
171;; FP
172(define_insn_reservation "ppc8540_float" 4
173  (and (eq_attr "type" "fp")
174       (eq_attr "cpu" "ppc8540"))
175  "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
176   ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
177
178;; float divides.  We omit reserving a retire unit and miu_stage3
179;; because of the result automata will be huge.
180(define_insn_reservation "ppc8540_float_vector_divide" 29
181  (and (eq_attr "type" "vecfdiv")
182       (eq_attr "cpu" "ppc8540"))
183  "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
184   ppc8540_mu_div*28")
185
186;; Brinc
187(define_insn_reservation "ppc8540_brinc" 1
188  (and (eq_attr "type" "brinc")
189       (eq_attr "cpu" "ppc8540"))
190  "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
191
192;; Simple vector
193(define_insn_reservation "ppc8540_simple_vector" 1
194  (and (eq_attr "type" "vecsimple")
195       (eq_attr "cpu" "ppc8540"))
196  "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
197
198;; Simple vector compare
199(define_insn_reservation "ppc8540_simple_vector_compare" 1
200  (and (eq_attr "type" "veccmpsimple")
201       (eq_attr "cpu" "ppc8540"))
202  "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
203
204;; Vector compare
205(define_insn_reservation "ppc8540_vector_compare" 1
206  (and (eq_attr "type" "veccmp")
207       (eq_attr "cpu" "ppc8540"))
208  "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
209
210;; evsplatfi evsplati
211(define_insn_reservation "ppc8540_vector_perm" 1
212  (and (eq_attr "type" "vecperm")
213       (eq_attr "cpu" "ppc8540"))
214  "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
215
216;; Vector float
217(define_insn_reservation "ppc8540_float_vector" 4
218  (and (eq_attr "type" "vecfloat")
219       (eq_attr "cpu" "ppc8540"))
220  "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
221   ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
222
223;; Vector divides: Use the average.  We omit reserving a retire unit
224;; because of the result automata will be huge.  We ignore reservation
225;; of miu_stage3 here because we use the average latency time.
226(define_insn_reservation "ppc8540_vector_divide" 14
227  (and (eq_attr "type" "vecdiv")
228       (eq_attr "cpu" "ppc8540"))
229  "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
230   ppc8540_mu_div*13")
231
232;; Complex vector.
233(define_insn_reservation "ppc8540_complex_vector" 4
234  (and (eq_attr "type" "veccomplex")
235       (eq_attr "cpu" "ppc8540"))
236  "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
237   ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
238
239;; Vector load
240(define_insn_reservation "ppc8540_vector_load" 3
241  (and (eq_attr "type" "vecload")
242       (eq_attr "cpu" "ppc8540"))
243  "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
244
245;; Vector store
246(define_insn_reservation "ppc8540_vector_store" 3
247  (and (eq_attr "type" "vecstore")
248       (eq_attr "cpu" "ppc8540"))
249  "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
250