mips.h revision 208737
1169689Skan/* Definitions of target machine for GNU compiler. MIPS version. 2169689Skan Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 3169689Skan 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4169689Skan Contributed by A. Lichnewsky (lich@inria.inria.fr). 5169689Skan Changed by Michael Meissner (meissner@osf.org). 6169689Skan 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and 7169689Skan Brendan Eich (brendan@microunity.com). 8169689Skan 9169689SkanThis file is part of GCC. 10169689Skan 11169689SkanGCC is free software; you can redistribute it and/or modify 12169689Skanit under the terms of the GNU General Public License as published by 13169689Skanthe Free Software Foundation; either version 2, or (at your option) 14169689Skanany later version. 15169689Skan 16169689SkanGCC is distributed in the hope that it will be useful, 17169689Skanbut WITHOUT ANY WARRANTY; without even the implied warranty of 18169689SkanMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19169689SkanGNU General Public License for more details. 20169689Skan 21169689SkanYou should have received a copy of the GNU General Public License 22169689Skanalong with GCC; see the file COPYING. If not, write to 23169689Skanthe Free Software Foundation, 51 Franklin Street, Fifth Floor, 24169689SkanBoston, MA 02110-1301, USA. */ 25169689Skan 26169689Skan 27169689Skan/* MIPS external variables defined in mips.c. */ 28169689Skan 29169689Skan/* Which processor to schedule for. Since there is no difference between 30169689Skan a R2000 and R3000 in terms of the scheduler, we collapse them into 31169689Skan just an R3000. The elements of the enumeration must match exactly 32169689Skan the cpu attribute in the mips.md machine description. */ 33169689Skan 34169689Skanenum processor_type { 35169689Skan PROCESSOR_R3000, 36169689Skan PROCESSOR_4KC, 37169689Skan PROCESSOR_4KP, 38169689Skan PROCESSOR_5KC, 39169689Skan PROCESSOR_5KF, 40169689Skan PROCESSOR_20KC, 41169689Skan PROCESSOR_24K, 42169689Skan PROCESSOR_24KX, 43169689Skan PROCESSOR_M4K, 44208737Sjmallett PROCESSOR_OCTEON, 45169689Skan PROCESSOR_R3900, 46169689Skan PROCESSOR_R6000, 47169689Skan PROCESSOR_R4000, 48169689Skan PROCESSOR_R4100, 49169689Skan PROCESSOR_R4111, 50169689Skan PROCESSOR_R4120, 51169689Skan PROCESSOR_R4130, 52169689Skan PROCESSOR_R4300, 53169689Skan PROCESSOR_R4600, 54169689Skan PROCESSOR_R4650, 55169689Skan PROCESSOR_R5000, 56169689Skan PROCESSOR_R5400, 57169689Skan PROCESSOR_R5500, 58169689Skan PROCESSOR_R7000, 59169689Skan PROCESSOR_R8000, 60169689Skan PROCESSOR_R9000, 61169689Skan PROCESSOR_SB1, 62169689Skan PROCESSOR_SB1A, 63169689Skan PROCESSOR_SR71000, 64169689Skan PROCESSOR_MAX 65169689Skan}; 66169689Skan 67169689Skan/* Costs of various operations on the different architectures. */ 68169689Skan 69169689Skanstruct mips_rtx_cost_data 70169689Skan{ 71169689Skan unsigned short fp_add; 72169689Skan unsigned short fp_mult_sf; 73169689Skan unsigned short fp_mult_df; 74169689Skan unsigned short fp_div_sf; 75169689Skan unsigned short fp_div_df; 76169689Skan unsigned short int_mult_si; 77169689Skan unsigned short int_mult_di; 78169689Skan unsigned short int_div_si; 79169689Skan unsigned short int_div_di; 80169689Skan unsigned short branch_cost; 81169689Skan unsigned short memory_latency; 82169689Skan}; 83169689Skan 84169689Skan/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), 85169689Skan ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended 86169689Skan to work on a 64 bit machine. */ 87169689Skan 88169689Skan#define ABI_32 0 89169689Skan#define ABI_N32 1 90169689Skan#define ABI_64 2 91169689Skan#define ABI_EABI 3 92169689Skan#define ABI_O64 4 93169689Skan 94169689Skan/* Information about one recognized processor. Defined here for the 95169689Skan benefit of TARGET_CPU_CPP_BUILTINS. */ 96169689Skanstruct mips_cpu_info { 97169689Skan /* The 'canonical' name of the processor as far as GCC is concerned. 98169689Skan It's typically a manufacturer's prefix followed by a numerical 99169689Skan designation. It should be lower case. */ 100169689Skan const char *name; 101169689Skan 102169689Skan /* The internal processor number that most closely matches this 103169689Skan entry. Several processors can have the same value, if there's no 104169689Skan difference between them from GCC's point of view. */ 105169689Skan enum processor_type cpu; 106169689Skan 107169689Skan /* The ISA level that the processor implements. */ 108169689Skan int isa; 109169689Skan}; 110169689Skan 111169689Skan#ifndef USED_FOR_TARGET 112169689Skanextern char mips_print_operand_punct[256]; /* print_operand punctuation chars */ 113169689Skanextern const char *current_function_file; /* filename current function is in */ 114169689Skanextern int num_source_filenames; /* current .file # */ 115169689Skanextern int mips_section_threshold; /* # bytes of data/sdata cutoff */ 116169689Skanextern int sym_lineno; /* sgi next label # for each stmt */ 117169689Skanextern int set_noreorder; /* # of nested .set noreorder's */ 118169689Skanextern int set_nomacro; /* # of nested .set nomacro's */ 119169689Skanextern int set_noat; /* # of nested .set noat's */ 120169689Skanextern int set_volatile; /* # of nested .set volatile's */ 121169689Skanextern int mips_branch_likely; /* emit 'l' after br (branch likely) */ 122169689Skanextern int mips_dbx_regno[]; /* Map register # to debug register # */ 123169689Skanextern bool mips_split_p[]; 124169689Skanextern GTY(()) rtx cmp_operands[2]; 125169689Skanextern enum processor_type mips_arch; /* which cpu to codegen for */ 126169689Skanextern enum processor_type mips_tune; /* which cpu to schedule for */ 127169689Skanextern int mips_isa; /* architectural level */ 128169689Skanextern int mips_abi; /* which ABI to use */ 129169689Skanextern int mips16_hard_float; /* mips16 without -msoft-float */ 130169689Skanextern const struct mips_cpu_info mips_cpu_info_table[]; 131169689Skanextern const struct mips_cpu_info *mips_arch_info; 132169689Skanextern const struct mips_cpu_info *mips_tune_info; 133169689Skanextern const struct mips_rtx_cost_data *mips_cost; 134169689Skan#endif 135169689Skan 136169689Skan/* Macros to silence warnings about numbers being signed in traditional 137169689Skan C and unsigned in ISO C when compiled on 32-bit hosts. */ 138169689Skan 139169689Skan#define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ 140169689Skan#define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ 141169689Skan#define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ 142169689Skan 143169689Skan 144169689Skan/* Run-time compilation parameters selecting different hardware subsets. */ 145169689Skan 146169689Skan/* True if the call patterns should be split into a jalr followed by 147169689Skan an instruction to restore $gp. This is only ever true for SVR4 PIC, 148169689Skan in which $gp is call-clobbered. It is only safe to split the load 149169689Skan from the call when every use of $gp is explicit. */ 150169689Skan 151169689Skan#define TARGET_SPLIT_CALLS \ 152169689Skan (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI) 153169689Skan 154169689Skan/* True if we're generating a form of -mabicalls in which we can use 155169689Skan operators like %hi and %lo to refer to locally-binding symbols. 156169689Skan We can only do this for -mno-shared, and only then if we can use 157169689Skan relocation operations instead of assembly macros. It isn't really 158169689Skan worth using absolute sequences for 64-bit symbols because GOT 159169689Skan accesses are so much shorter. */ 160169689Skan 161169689Skan#define TARGET_ABSOLUTE_ABICALLS \ 162169689Skan (TARGET_ABICALLS \ 163169689Skan && !TARGET_SHARED \ 164169689Skan && TARGET_EXPLICIT_RELOCS \ 165169689Skan && !ABI_HAS_64BIT_SYMBOLS) 166169689Skan 167169689Skan/* True if we can optimize sibling calls. For simplicity, we only 168169689Skan handle cases in which call_insn_operand will reject invalid 169169689Skan sibcall addresses. There are two cases in which this isn't true: 170169689Skan 171169689Skan - TARGET_MIPS16. call_insn_operand accepts constant addresses 172169689Skan but there is no direct jump instruction. It isn't worth 173169689Skan using sibling calls in this case anyway; they would usually 174169689Skan be longer than normal calls. 175169689Skan 176169689Skan - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand 177169689Skan accepts global constants, but "jr $25" is the only allowed 178169689Skan sibcall. */ 179169689Skan 180169689Skan#define TARGET_SIBCALLS \ 181169689Skan (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS)) 182169689Skan 183169689Skan/* True if .gpword or .gpdword should be used for switch tables. 184169689Skan 185169689Skan Although GAS does understand .gpdword, the SGI linker mishandles 186169689Skan the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64). 187169689Skan We therefore disable GP-relative switch tables for n64 on IRIX targets. */ 188169689Skan#define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX)) 189169689Skan 190169689Skan/* Generate mips16 code */ 191169689Skan#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) 192169689Skan/* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */ 193169689Skan#define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) 194169689Skan 195169689Skan/* Generic ISA defines. */ 196169689Skan#define ISA_MIPS1 (mips_isa == 1) 197169689Skan#define ISA_MIPS2 (mips_isa == 2) 198169689Skan#define ISA_MIPS3 (mips_isa == 3) 199169689Skan#define ISA_MIPS4 (mips_isa == 4) 200169689Skan#define ISA_MIPS32 (mips_isa == 32) 201169689Skan#define ISA_MIPS32R2 (mips_isa == 33) 202169689Skan#define ISA_MIPS64 (mips_isa == 64) 203208737Sjmallett#define ISA_MIPS64R2 (mips_isa == 65) 204169689Skan 205169689Skan/* Architecture target defines. */ 206169689Skan#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) 207169689Skan#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) 208169689Skan#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) 209169689Skan#define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) 210169689Skan#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) 211169689Skan#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) 212169689Skan#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) 213169689Skan#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) 214169689Skan#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ 215169689Skan || mips_arch == PROCESSOR_SB1A) 216169689Skan#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) 217208737Sjmallett#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON) 218169689Skan 219169689Skan/* Scheduling target defines. */ 220169689Skan#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) 221169689Skan#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) 222169689Skan#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) 223169689Skan#define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) 224169689Skan#define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) 225169689Skan#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) 226169689Skan#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) 227169689Skan#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) 228169689Skan#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) 229169689Skan#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) 230169689Skan#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) 231169689Skan#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ 232169689Skan || mips_tune == PROCESSOR_SB1A) 233208737Sjmallett#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON) 234169689Skan 235169689Skan/* True if the pre-reload scheduler should try to create chains of 236169689Skan multiply-add or multiply-subtract instructions. For example, 237169689Skan suppose we have: 238169689Skan 239169689Skan t1 = a * b 240169689Skan t2 = t1 + c * d 241169689Skan t3 = e * f 242169689Skan t4 = t3 - g * h 243169689Skan 244169689Skan t1 will have a higher priority than t2 and t3 will have a higher 245169689Skan priority than t4. However, before reload, there is no dependence 246169689Skan between t1 and t3, and they can often have similar priorities. 247169689Skan The scheduler will then tend to prefer: 248169689Skan 249169689Skan t1 = a * b 250169689Skan t3 = e * f 251169689Skan t2 = t1 + c * d 252169689Skan t4 = t3 - g * h 253169689Skan 254169689Skan which stops us from making full use of macc/madd-style instructions. 255169689Skan This sort of situation occurs frequently in Fourier transforms and 256169689Skan in unrolled loops. 257169689Skan 258169689Skan To counter this, the TUNE_MACC_CHAINS code will reorder the ready 259169689Skan queue so that chained multiply-add and multiply-subtract instructions 260169689Skan appear ahead of any other instruction that is likely to clobber lo. 261169689Skan In the example above, if t2 and t3 become ready at the same time, 262169689Skan the code ensures that t2 is scheduled first. 263169689Skan 264169689Skan Multiply-accumulate instructions are a bigger win for some targets 265169689Skan than others, so this macro is defined on an opt-in basis. */ 266169689Skan#define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ 267169689Skan || TUNE_MIPS4120 \ 268169689Skan || TUNE_MIPS4130) 269169689Skan 270169689Skan#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) 271169689Skan#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) 272169689Skan 273169689Skan/* IRIX specific stuff. */ 274169689Skan#define TARGET_IRIX 0 275169689Skan#define TARGET_IRIX6 0 276169689Skan 277169689Skan/* Define preprocessor macros for the -march and -mtune options. 278169689Skan PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected 279169689Skan processor. If INFO's canonical name is "foo", define PREFIX to 280169689Skan be "foo", and define an additional macro PREFIX_FOO. */ 281169689Skan#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ 282169689Skan do \ 283169689Skan { \ 284169689Skan char *macro, *p; \ 285169689Skan \ 286169689Skan macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ 287169689Skan for (p = macro; *p != 0; p++) \ 288169689Skan *p = TOUPPER (*p); \ 289169689Skan \ 290169689Skan builtin_define (macro); \ 291169689Skan builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ 292169689Skan free (macro); \ 293169689Skan } \ 294169689Skan while (0) 295169689Skan 296169689Skan/* Target CPU builtins. */ 297169689Skan#define TARGET_CPU_CPP_BUILTINS() \ 298169689Skan do \ 299169689Skan { \ 300169689Skan /* Everyone but IRIX defines this to mips. */ \ 301169689Skan if (!TARGET_IRIX) \ 302169689Skan builtin_assert ("machine=mips"); \ 303169689Skan \ 304169689Skan builtin_assert ("cpu=mips"); \ 305169689Skan builtin_define ("__mips__"); \ 306169689Skan builtin_define ("_mips"); \ 307169689Skan \ 308169689Skan /* We do this here because __mips is defined below \ 309169689Skan and so we can't use builtin_define_std. */ \ 310169689Skan if (!flag_iso) \ 311169689Skan builtin_define ("mips"); \ 312169689Skan \ 313169689Skan if (TARGET_64BIT) \ 314169689Skan builtin_define ("__mips64"); \ 315169689Skan \ 316169689Skan if (!TARGET_IRIX) \ 317169689Skan { \ 318169689Skan /* Treat _R3000 and _R4000 like register-size \ 319169689Skan defines, which is how they've historically \ 320169689Skan been used. */ \ 321169689Skan if (TARGET_64BIT) \ 322169689Skan { \ 323169689Skan builtin_define_std ("R4000"); \ 324169689Skan builtin_define ("_R4000"); \ 325169689Skan } \ 326169689Skan else \ 327169689Skan { \ 328169689Skan builtin_define_std ("R3000"); \ 329169689Skan builtin_define ("_R3000"); \ 330169689Skan } \ 331169689Skan } \ 332169689Skan if (TARGET_FLOAT64) \ 333169689Skan builtin_define ("__mips_fpr=64"); \ 334169689Skan else \ 335169689Skan builtin_define ("__mips_fpr=32"); \ 336169689Skan \ 337169689Skan if (TARGET_MIPS16) \ 338169689Skan builtin_define ("__mips16"); \ 339169689Skan \ 340169689Skan if (TARGET_MIPS3D) \ 341169689Skan builtin_define ("__mips3d"); \ 342169689Skan \ 343169689Skan if (TARGET_DSP) \ 344169689Skan builtin_define ("__mips_dsp"); \ 345169689Skan \ 346169689Skan MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ 347169689Skan MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ 348169689Skan \ 349169689Skan if (ISA_MIPS1) \ 350169689Skan { \ 351169689Skan builtin_define ("__mips=1"); \ 352169689Skan builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ 353169689Skan } \ 354169689Skan else if (ISA_MIPS2) \ 355169689Skan { \ 356169689Skan builtin_define ("__mips=2"); \ 357169689Skan builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ 358169689Skan } \ 359169689Skan else if (ISA_MIPS3) \ 360169689Skan { \ 361169689Skan builtin_define ("__mips=3"); \ 362169689Skan builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ 363169689Skan } \ 364169689Skan else if (ISA_MIPS4) \ 365169689Skan { \ 366169689Skan builtin_define ("__mips=4"); \ 367169689Skan builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ 368169689Skan } \ 369169689Skan else if (ISA_MIPS32) \ 370169689Skan { \ 371169689Skan builtin_define ("__mips=32"); \ 372169689Skan builtin_define ("__mips_isa_rev=1"); \ 373169689Skan builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 374169689Skan } \ 375169689Skan else if (ISA_MIPS32R2) \ 376169689Skan { \ 377169689Skan builtin_define ("__mips=32"); \ 378169689Skan builtin_define ("__mips_isa_rev=2"); \ 379169689Skan builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 380169689Skan } \ 381169689Skan else if (ISA_MIPS64) \ 382169689Skan { \ 383169689Skan builtin_define ("__mips=64"); \ 384169689Skan builtin_define ("__mips_isa_rev=1"); \ 385169689Skan builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 386169689Skan } \ 387208737Sjmallett else if (ISA_MIPS64R2) \ 388208737Sjmallett { \ 389208737Sjmallett builtin_define ("__mips=64"); \ 390208737Sjmallett builtin_define ("__mips_isa_rev=2"); \ 391208737Sjmallett builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 392208737Sjmallett } \ 393169689Skan \ 394169689Skan if (TARGET_HARD_FLOAT) \ 395169689Skan builtin_define ("__mips_hard_float"); \ 396169689Skan else if (TARGET_SOFT_FLOAT) \ 397169689Skan builtin_define ("__mips_soft_float"); \ 398169689Skan \ 399169689Skan if (TARGET_SINGLE_FLOAT) \ 400169689Skan builtin_define ("__mips_single_float"); \ 401169689Skan \ 402169689Skan if (TARGET_PAIRED_SINGLE_FLOAT) \ 403169689Skan builtin_define ("__mips_paired_single_float"); \ 404169689Skan \ 405169689Skan if (TARGET_BIG_ENDIAN) \ 406169689Skan { \ 407169689Skan builtin_define_std ("MIPSEB"); \ 408169689Skan builtin_define ("_MIPSEB"); \ 409169689Skan } \ 410169689Skan else \ 411169689Skan { \ 412169689Skan builtin_define_std ("MIPSEL"); \ 413169689Skan builtin_define ("_MIPSEL"); \ 414169689Skan } \ 415169689Skan \ 416169689Skan /* Macros dependent on the C dialect. */ \ 417169689Skan if (preprocessing_asm_p ()) \ 418169689Skan { \ 419169689Skan builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 420169689Skan builtin_define ("_LANGUAGE_ASSEMBLY"); \ 421169689Skan } \ 422169689Skan else if (c_dialect_cxx ()) \ 423169689Skan { \ 424169689Skan builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ 425169689Skan builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 426169689Skan builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 427169689Skan } \ 428169689Skan else \ 429169689Skan { \ 430169689Skan builtin_define_std ("LANGUAGE_C"); \ 431169689Skan builtin_define ("_LANGUAGE_C"); \ 432169689Skan } \ 433169689Skan if (c_dialect_objc ()) \ 434169689Skan { \ 435169689Skan builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ 436169689Skan builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 437169689Skan /* Bizarre, but needed at least for Irix. */ \ 438169689Skan builtin_define_std ("LANGUAGE_C"); \ 439169689Skan builtin_define ("_LANGUAGE_C"); \ 440169689Skan } \ 441169689Skan \ 442169689Skan if (mips_abi == ABI_EABI) \ 443169689Skan builtin_define ("__mips_eabi"); \ 444169689Skan \ 445169689Skan} while (0) 446169689Skan 447169689Skan/* Default target_flags if no switches are specified */ 448169689Skan 449169689Skan#ifndef TARGET_DEFAULT 450169689Skan#define TARGET_DEFAULT 0 451169689Skan#endif 452169689Skan 453169689Skan#ifndef TARGET_CPU_DEFAULT 454169689Skan#define TARGET_CPU_DEFAULT 0 455169689Skan#endif 456169689Skan 457169689Skan#ifndef TARGET_ENDIAN_DEFAULT 458169689Skan#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN 459169689Skan#endif 460169689Skan 461169689Skan#ifndef TARGET_FP_EXCEPTIONS_DEFAULT 462169689Skan#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS 463169689Skan#endif 464169689Skan 465169689Skan/* 'from-abi' makes a good default: you get whatever the ABI requires. */ 466169689Skan#ifndef MIPS_ISA_DEFAULT 467169689Skan#ifndef MIPS_CPU_STRING_DEFAULT 468169689Skan#define MIPS_CPU_STRING_DEFAULT "from-abi" 469169689Skan#endif 470169689Skan#endif 471169689Skan 472169689Skan#ifdef IN_LIBGCC2 473169689Skan#undef TARGET_64BIT 474169689Skan/* Make this compile time constant for libgcc2 */ 475169689Skan#ifdef __mips64 476169689Skan#define TARGET_64BIT 1 477169689Skan#else 478169689Skan#define TARGET_64BIT 0 479169689Skan#endif 480169689Skan#endif /* IN_LIBGCC2 */ 481169689Skan 482169689Skan#define TARGET_LIBGCC_SDATA_SECTION ".sdata" 483169689Skan 484169689Skan#ifndef MULTILIB_ENDIAN_DEFAULT 485169689Skan#if TARGET_ENDIAN_DEFAULT == 0 486169689Skan#define MULTILIB_ENDIAN_DEFAULT "EL" 487169689Skan#else 488169689Skan#define MULTILIB_ENDIAN_DEFAULT "EB" 489169689Skan#endif 490169689Skan#endif 491169689Skan 492169689Skan#ifndef MULTILIB_ISA_DEFAULT 493169689Skan# if MIPS_ISA_DEFAULT == 1 494169689Skan# define MULTILIB_ISA_DEFAULT "mips1" 495169689Skan# else 496169689Skan# if MIPS_ISA_DEFAULT == 2 497169689Skan# define MULTILIB_ISA_DEFAULT "mips2" 498169689Skan# else 499169689Skan# if MIPS_ISA_DEFAULT == 3 500169689Skan# define MULTILIB_ISA_DEFAULT "mips3" 501169689Skan# else 502169689Skan# if MIPS_ISA_DEFAULT == 4 503169689Skan# define MULTILIB_ISA_DEFAULT "mips4" 504169689Skan# else 505169689Skan# if MIPS_ISA_DEFAULT == 32 506169689Skan# define MULTILIB_ISA_DEFAULT "mips32" 507169689Skan# else 508169689Skan# if MIPS_ISA_DEFAULT == 33 509169689Skan# define MULTILIB_ISA_DEFAULT "mips32r2" 510169689Skan# else 511169689Skan# if MIPS_ISA_DEFAULT == 64 512169689Skan# define MULTILIB_ISA_DEFAULT "mips64" 513169689Skan# else 514208737Sjmallett# if MIPS_ISA_DEFAULT == 65 515208737Sjmallett# define MULTILIB_ISA_DEFAULT "mips64r2" 516208737Sjmallett# else 517208737Sjmallett# define MULTILIB_ISA_DEFAULT "mips1" 518208737Sjmallett# endif 519169689Skan# endif 520169689Skan# endif 521169689Skan# endif 522169689Skan# endif 523169689Skan# endif 524169689Skan# endif 525169689Skan# endif 526169689Skan#endif 527169689Skan 528169689Skan#ifndef MULTILIB_DEFAULTS 529169689Skan#define MULTILIB_DEFAULTS \ 530169689Skan { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } 531169689Skan#endif 532169689Skan 533169689Skan/* We must pass -EL to the linker by default for little endian embedded 534169689Skan targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the 535169689Skan linker will default to using big-endian output files. The OUTPUT_FORMAT 536169689Skan line must be in the linker script, otherwise -EB/-EL will not work. */ 537169689Skan 538169689Skan#ifndef ENDIAN_SPEC 539169689Skan#if TARGET_ENDIAN_DEFAULT == 0 540169689Skan#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" 541169689Skan#else 542169689Skan#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" 543169689Skan#endif 544169689Skan#endif 545169689Skan 546169689Skan/* Support for a compile-time default CPU, et cetera. The rules are: 547169689Skan --with-arch is ignored if -march is specified or a -mips is specified 548169689Skan (other than -mips16). 549169689Skan --with-tune is ignored if -mtune is specified. 550169689Skan --with-abi is ignored if -mabi is specified. 551169689Skan --with-float is ignored if -mhard-float or -msoft-float are 552169689Skan specified. 553169689Skan --with-divide is ignored if -mdivide-traps or -mdivide-breaks are 554169689Skan specified. */ 555169689Skan#define OPTION_DEFAULT_SPECS \ 556169689Skan {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \ 557169689Skan {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 558169689Skan {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 559169689Skan {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ 560169689Skan {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" } 561169689Skan 562169689Skan 563169689Skan#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ 564169689Skan && ISA_HAS_COND_TRAP) 565169689Skan 566169689Skan#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \ 567169689Skan && !TARGET_SR71K \ 568169689Skan && !TARGET_MIPS16) 569169689Skan 570169689Skan/* Generate three-operand multiply instructions for SImode. */ 571169689Skan#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \ 572169689Skan || TARGET_MIPS5400 \ 573169689Skan || TARGET_MIPS5500 \ 574169689Skan || TARGET_MIPS7000 \ 575169689Skan || TARGET_MIPS9000 \ 576169689Skan || TARGET_MAD \ 577169689Skan || ISA_MIPS32 \ 578169689Skan || ISA_MIPS32R2 \ 579208737Sjmallett || ISA_MIPS64 \ 580208737Sjmallett || ISA_MIPS64R2) \ 581169689Skan && !TARGET_MIPS16) 582169689Skan 583169689Skan/* Generate three-operand multiply instructions for DImode. */ 584169689Skan#define GENERATE_MULT3_DI ((TARGET_MIPS3900) \ 585169689Skan && !TARGET_MIPS16) 586169689Skan 587169689Skan/* True if the ABI can only work with 64-bit integer registers. We 588169689Skan generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but 589169689Skan otherwise floating-point registers must also be 64-bit. */ 590169689Skan#define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) 591169689Skan 592169689Skan/* Likewise for 32-bit regs. */ 593169689Skan#define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) 594169689Skan 595169689Skan/* True if symbols are 64 bits wide. At present, n64 is the only 596169689Skan ABI for which this is true. */ 597169689Skan#define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32) 598169689Skan 599169689Skan/* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */ 600169689Skan#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ 601169689Skan || ISA_MIPS4 \ 602208737Sjmallett || ISA_MIPS64 \ 603208737Sjmallett || ISA_MIPS64R2) 604169689Skan 605169689Skan/* ISA has branch likely instructions (e.g. mips2). */ 606169689Skan/* Disable branchlikely for tx39 until compare rewrite. They haven't 607169689Skan been generated up to this point. */ 608169689Skan#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1) 609169689Skan 610169689Skan/* ISA has the conditional move instructions introduced in mips4. */ 611169689Skan#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \ 612169689Skan || ISA_MIPS32 \ 613169689Skan || ISA_MIPS32R2 \ 614208737Sjmallett || ISA_MIPS64 \ 615208737Sjmallett || ISA_MIPS64R2) \ 616169689Skan && !TARGET_MIPS5500 \ 617169689Skan && !TARGET_MIPS16) 618169689Skan 619169689Skan/* ISA has the mips4 FP condition code instructions: FP-compare to CC, 620169689Skan branch on CC, and move (both FP and non-FP) on CC. */ 621169689Skan#define ISA_HAS_8CC (ISA_MIPS4 \ 622169689Skan || ISA_MIPS32 \ 623169689Skan || ISA_MIPS32R2 \ 624208737Sjmallett || ISA_MIPS64 \ 625208737Sjmallett || ISA_MIPS64R2) 626169689Skan 627169689Skan/* This is a catch all for other mips4 instructions: indexed load, the 628169689Skan FP madd and msub instructions, and the FP recip and recip sqrt 629169689Skan instructions. */ 630169689Skan#define ISA_HAS_FP4 ((ISA_MIPS4 \ 631208737Sjmallett || ISA_MIPS64 \ 632208737Sjmallett || ISA_MIPS64R2) \ 633169689Skan && !TARGET_MIPS16) 634169689Skan 635169689Skan/* ISA has conditional trap instructions. */ 636169689Skan#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ 637169689Skan && !TARGET_MIPS16) 638169689Skan 639169689Skan/* ISA has integer multiply-accumulate instructions, madd and msub. */ 640169689Skan#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ 641169689Skan || ISA_MIPS32R2 \ 642169689Skan || ISA_MIPS64 \ 643208737Sjmallett || ISA_MIPS64R2 \ 644169689Skan ) && !TARGET_MIPS16) 645169689Skan 646169689Skan/* ISA has floating-point nmadd and nmsub instructions. */ 647169689Skan#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \ 648208737Sjmallett || ISA_MIPS64 \ 649208737Sjmallett || ISA_MIPS64R2) \ 650169689Skan && (!TARGET_MIPS5400 || TARGET_MAD) \ 651169689Skan && ! TARGET_MIPS16) 652169689Skan 653169689Skan/* ISA has count leading zeroes/ones instruction (not implemented). */ 654169689Skan#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ 655169689Skan || ISA_MIPS32R2 \ 656169689Skan || ISA_MIPS64 \ 657208737Sjmallett || ISA_MIPS64R2 \ 658169689Skan ) && !TARGET_MIPS16) 659169689Skan 660169689Skan/* ISA has double-word count leading zeroes/ones instruction (not 661169689Skan implemented). */ 662169689Skan#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \ 663208737Sjmallett || ISA_MIPS64R2 \ 664169689Skan && !TARGET_MIPS16) 665169689Skan 666169689Skan/* ISA has three operand multiply instructions that put 667169689Skan the high part in an accumulator: mulhi or mulhiu. */ 668169689Skan#define ISA_HAS_MULHI (TARGET_MIPS5400 \ 669169689Skan || TARGET_MIPS5500 \ 670169689Skan || TARGET_SR71K \ 671169689Skan ) 672169689Skan 673169689Skan/* ISA has three operand multiply instructions that 674169689Skan negates the result and puts the result in an accumulator. */ 675169689Skan#define ISA_HAS_MULS (TARGET_MIPS5400 \ 676169689Skan || TARGET_MIPS5500 \ 677169689Skan || TARGET_SR71K \ 678169689Skan ) 679169689Skan 680169689Skan/* ISA has three operand multiply instructions that subtracts the 681169689Skan result from a 4th operand and puts the result in an accumulator. */ 682169689Skan#define ISA_HAS_MSAC (TARGET_MIPS5400 \ 683169689Skan || TARGET_MIPS5500 \ 684169689Skan || TARGET_SR71K \ 685169689Skan ) 686169689Skan/* ISA has three operand multiply instructions that the result 687169689Skan from a 4th operand and puts the result in an accumulator. */ 688169689Skan#define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \ 689169689Skan || (TARGET_MIPS4130 && !TARGET_MIPS16) \ 690169689Skan || TARGET_MIPS5400 \ 691169689Skan || TARGET_MIPS5500 \ 692169689Skan || TARGET_SR71K \ 693169689Skan ) 694169689Skan 695169689Skan/* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ 696169689Skan#define ISA_HAS_MACCHI (!TARGET_MIPS16 \ 697169689Skan && (TARGET_MIPS4120 \ 698169689Skan || TARGET_MIPS4130)) 699169689Skan 700169689Skan/* ISA has 32-bit rotate right instruction. */ 701169689Skan#define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \ 702169689Skan && (ISA_MIPS32R2 \ 703208737Sjmallett || ISA_MIPS64R2 \ 704169689Skan || TARGET_MIPS5400 \ 705169689Skan || TARGET_MIPS5500 \ 706169689Skan || TARGET_SR71K \ 707169689Skan )) 708169689Skan 709169689Skan/* ISA has 64-bit rotate right instruction. */ 710169689Skan#define ISA_HAS_ROTR_DI (TARGET_64BIT \ 711169689Skan && !TARGET_MIPS16 \ 712169689Skan && (TARGET_MIPS5400 \ 713169689Skan || TARGET_MIPS5500 \ 714169689Skan || TARGET_SR71K \ 715169689Skan )) 716169689Skan 717169689Skan/* ISA has data prefetch instructions. This controls use of 'pref'. */ 718169689Skan#define ISA_HAS_PREFETCH ((ISA_MIPS4 \ 719169689Skan || ISA_MIPS32 \ 720169689Skan || ISA_MIPS32R2 \ 721208737Sjmallett || ISA_MIPS64 \ 722208737Sjmallett || ISA_MIPS64R2) \ 723169689Skan && !TARGET_MIPS16) 724169689Skan 725169689Skan/* ISA has data indexed prefetch instructions. This controls use of 726169689Skan 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. 727169689Skan (prefx is a cop1x instruction, so can only be used if FP is 728169689Skan enabled.) */ 729169689Skan#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ 730208737Sjmallett || ISA_MIPS64 \ 731208737Sjmallett || ISA_MIPS64R2) \ 732169689Skan && !TARGET_MIPS16) 733169689Skan 734169689Skan/* True if trunc.w.s and trunc.w.d are real (not synthetic) 735169689Skan instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d 736169689Skan also requires TARGET_DOUBLE_FLOAT. */ 737169689Skan#define ISA_HAS_TRUNC_W (!ISA_MIPS1) 738169689Skan 739169689Skan/* ISA includes the MIPS32r2 seb and seh instructions. */ 740169689Skan#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \ 741169689Skan && (ISA_MIPS32R2 \ 742208737Sjmallett || ISA_MIPS64R2 \ 743169689Skan )) 744169689Skan 745169689Skan/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ 746169689Skan#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \ 747169689Skan && (ISA_MIPS32R2 \ 748208737Sjmallett || ISA_MIPS64R2 \ 749169689Skan )) 750169689Skan 751169689Skan/* True if the result of a load is not available to the next instruction. 752169689Skan A nop will then be needed between instructions like "lw $4,..." 753169689Skan and "addiu $4,$4,1". */ 754169689Skan#define ISA_HAS_LOAD_DELAY (mips_isa == 1 \ 755169689Skan && !TARGET_MIPS3900 \ 756169689Skan && !TARGET_MIPS16) 757169689Skan 758169689Skan/* Likewise mtc1 and mfc1. */ 759169689Skan#define ISA_HAS_XFER_DELAY (mips_isa <= 3) 760169689Skan 761169689Skan/* Likewise floating-point comparisons. */ 762169689Skan#define ISA_HAS_FCMP_DELAY (mips_isa <= 3) 763169689Skan 764169689Skan/* True if mflo and mfhi can be immediately followed by instructions 765169689Skan which write to the HI and LO registers. 766169689Skan 767169689Skan According to MIPS specifications, MIPS ISAs I, II, and III need 768169689Skan (at least) two instructions between the reads of HI/LO and 769169689Skan instructions which write them, and later ISAs do not. Contradicting 770169689Skan the MIPS specifications, some MIPS IV processor user manuals (e.g. 771169689Skan the UM for the NEC Vr5000) document needing the instructions between 772169689Skan HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 773169689Skan MIPS64 and later ISAs to have the interlocks, plus any specific 774169689Skan earlier-ISA CPUs for which CPU documentation declares that the 775169689Skan instructions are really interlocked. */ 776169689Skan#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ 777169689Skan || ISA_MIPS32R2 \ 778169689Skan || ISA_MIPS64 \ 779208737Sjmallett || ISA_MIPS64R2 \ 780169689Skan || TARGET_MIPS5500) 781169689Skan 782169689Skan/* Add -G xx support. */ 783169689Skan 784169689Skan#undef SWITCH_TAKES_ARG 785169689Skan#define SWITCH_TAKES_ARG(CHAR) \ 786169689Skan (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') 787169689Skan 788169689Skan#define OVERRIDE_OPTIONS override_options () 789169689Skan 790169689Skan#define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage () 791169689Skan 792169689Skan/* Show we can debug even without a frame pointer. */ 793169689Skan#define CAN_DEBUG_WITHOUT_FP 794169689Skan 795169689Skan/* Tell collect what flags to pass to nm. */ 796169689Skan#ifndef NM_FLAGS 797169689Skan#define NM_FLAGS "-Bn" 798169689Skan#endif 799169689Skan 800169689Skan 801169689Skan#ifndef MIPS_ABI_DEFAULT 802169689Skan#define MIPS_ABI_DEFAULT ABI_32 803169689Skan#endif 804169689Skan 805169689Skan/* Use the most portable ABI flag for the ASM specs. */ 806169689Skan 807169689Skan#if MIPS_ABI_DEFAULT == ABI_32 808169689Skan#define MULTILIB_ABI_DEFAULT "mabi=32" 809169689Skan#endif 810169689Skan 811169689Skan#if MIPS_ABI_DEFAULT == ABI_O64 812169689Skan#define MULTILIB_ABI_DEFAULT "mabi=o64" 813169689Skan#endif 814169689Skan 815169689Skan#if MIPS_ABI_DEFAULT == ABI_N32 816169689Skan#define MULTILIB_ABI_DEFAULT "mabi=n32" 817169689Skan#endif 818169689Skan 819169689Skan#if MIPS_ABI_DEFAULT == ABI_64 820169689Skan#define MULTILIB_ABI_DEFAULT "mabi=64" 821169689Skan#endif 822169689Skan 823169689Skan#if MIPS_ABI_DEFAULT == ABI_EABI 824169689Skan#define MULTILIB_ABI_DEFAULT "mabi=eabi" 825169689Skan#endif 826169689Skan 827169689Skan/* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options 828169689Skan to the assembler. It may be overridden by subtargets. */ 829169689Skan#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC 830169689Skan#define SUBTARGET_ASM_OPTIMIZING_SPEC "\ 831169689Skan%{noasmopt:-O0} \ 832169689Skan%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}" 833169689Skan#endif 834169689Skan 835169689Skan/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to 836169689Skan the assembler. It may be overridden by subtargets. 837169689Skan 838169689Skan Beginning with gas 2.13, -mdebug must be passed to correctly handle 839169689Skan COFF debugging info. */ 840169689Skan 841169689Skan#ifndef SUBTARGET_ASM_DEBUGGING_SPEC 842169689Skan#define SUBTARGET_ASM_DEBUGGING_SPEC "\ 843169689Skan%{g} %{g0} %{g1} %{g2} %{g3} \ 844169689Skan%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ 845169689Skan%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ 846169689Skan%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ 847169689Skan%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \ 848169689Skan%{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}" 849169689Skan#endif 850169689Skan 851169689Skan/* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be 852169689Skan overridden by subtargets. */ 853169689Skan 854169689Skan#ifndef SUBTARGET_ASM_SPEC 855169689Skan#define SUBTARGET_ASM_SPEC "" 856169689Skan#endif 857169689Skan 858169689Skan#undef ASM_SPEC 859169689Skan#define ASM_SPEC "\ 860169689Skan%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ 861169689Skan%{mips32} %{mips32r2} %{mips64} \ 862169689Skan%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ 863169689Skan%{mips3d:-mips3d} \ 864169689Skan%{mdsp} \ 865169689Skan%{mfix-vr4120} %{mfix-vr4130} \ 866169689Skan%(subtarget_asm_optimizing_spec) \ 867169689Skan%(subtarget_asm_debugging_spec) \ 868169689Skan%{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \ 869169689Skan%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ 870169689Skan%{mshared} %{mno-shared} \ 871169689Skan%{msym32} %{mno-sym32} \ 872169689Skan%{mtune=*} %{v} \ 873169689Skan%(subtarget_asm_spec)" 874169689Skan 875169689Skan/* Extra switches sometimes passed to the linker. */ 876169689Skan/* ??? The bestGnum will never be passed to the linker, because the gcc driver 877169689Skan will interpret it as a -b option. */ 878169689Skan 879169689Skan#ifndef LINK_SPEC 880169689Skan#define LINK_SPEC "\ 881169689Skan%(endian_spec) \ 882169689Skan%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \ 883169689Skan%{bestGnum} %{shared} %{non_shared}" 884169689Skan#endif /* LINK_SPEC defined */ 885169689Skan 886169689Skan 887169689Skan/* Specs for the compiler proper */ 888169689Skan 889169689Skan/* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be 890169689Skan overridden by subtargets. */ 891169689Skan#ifndef SUBTARGET_CC1_SPEC 892169689Skan#define SUBTARGET_CC1_SPEC "" 893169689Skan#endif 894169689Skan 895169689Skan/* CC1_SPEC is the set of arguments to pass to the compiler proper. */ 896169689Skan 897169689Skan#undef CC1_SPEC 898169689Skan#define CC1_SPEC "\ 899169689Skan%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ 900169689Skan%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ 901169689Skan%{save-temps: } \ 902169689Skan%(subtarget_cc1_spec)" 903169689Skan 904169689Skan/* Preprocessor specs. */ 905169689Skan 906169689Skan/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be 907169689Skan overridden by subtargets. */ 908169689Skan#ifndef SUBTARGET_CPP_SPEC 909169689Skan#define SUBTARGET_CPP_SPEC "" 910169689Skan#endif 911169689Skan 912169689Skan#define CPP_SPEC "%(subtarget_cpp_spec)" 913169689Skan 914169689Skan/* This macro defines names of additional specifications to put in the specs 915169689Skan that can be used in various specifications like CC1_SPEC. Its definition 916169689Skan is an initializer with a subgrouping for each command option. 917169689Skan 918169689Skan Each subgrouping contains a string constant, that defines the 919169689Skan specification name, and a string constant that used by the GCC driver 920169689Skan program. 921169689Skan 922169689Skan Do not define this macro if it does not need to do anything. */ 923169689Skan 924169689Skan#define EXTRA_SPECS \ 925169689Skan { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ 926169689Skan { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 927169689Skan { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \ 928169689Skan { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ 929169689Skan { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 930169689Skan { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ 931169689Skan { "endian_spec", ENDIAN_SPEC }, \ 932169689Skan SUBTARGET_EXTRA_SPECS 933169689Skan 934169689Skan#ifndef SUBTARGET_EXTRA_SPECS 935169689Skan#define SUBTARGET_EXTRA_SPECS 936169689Skan#endif 937169689Skan 938169689Skan#define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ 939169689Skan#define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */ 940169689Skan#define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ 941169689Skan 942169689Skan#ifndef PREFERRED_DEBUGGING_TYPE 943169689Skan#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 944169689Skan#endif 945169689Skan 946169689Skan#define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4) 947169689Skan 948169689Skan/* By default, turn on GDB extensions. */ 949169689Skan#define DEFAULT_GDB_EXTENSIONS 1 950169689Skan 951169689Skan/* Local compiler-generated symbols must have a prefix that the assembler 952169689Skan understands. By default, this is $, although some targets (e.g., 953169689Skan NetBSD-ELF) need to override this. */ 954169689Skan 955169689Skan#ifndef LOCAL_LABEL_PREFIX 956169689Skan#define LOCAL_LABEL_PREFIX "$" 957169689Skan#endif 958169689Skan 959169689Skan/* By default on the mips, external symbols do not have an underscore 960169689Skan prepended, but some targets (e.g., NetBSD) require this. */ 961169689Skan 962169689Skan#ifndef USER_LABEL_PREFIX 963169689Skan#define USER_LABEL_PREFIX "" 964169689Skan#endif 965169689Skan 966169689Skan/* On Sun 4, this limit is 2048. We use 1500 to be safe, 967169689Skan since the length can run past this up to a continuation point. */ 968169689Skan#undef DBX_CONTIN_LENGTH 969169689Skan#define DBX_CONTIN_LENGTH 1500 970169689Skan 971169689Skan/* How to renumber registers for dbx and gdb. */ 972169689Skan#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ] 973169689Skan 974169689Skan/* The mapping from gcc register number to DWARF 2 CFA column number. */ 975169689Skan#define DWARF_FRAME_REGNUM(REG) (REG) 976169689Skan 977169689Skan/* The DWARF 2 CFA column which tracks the return address. */ 978169689Skan#define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31) 979169689Skan 980169689Skan/* The DWARF 2 CFA column which tracks the return address from a 981169689Skan signal handler context. */ 982169689Skan#define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1) 983169689Skan 984169689Skan/* Before the prologue, RA lives in r31. */ 985169689Skan#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31) 986169689Skan 987169689Skan/* Describe how we implement __builtin_eh_return. */ 988169689Skan#define EH_RETURN_DATA_REGNO(N) \ 989169689Skan ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 990169689Skan 991169689Skan#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) 992169689Skan 993169689Skan/* Offsets recorded in opcodes are a multiple of this alignment factor. 994169689Skan The default for this in 64-bit mode is 8, which causes problems with 995169689Skan SFmode register saves. */ 996169689Skan#define DWARF_CIE_DATA_ALIGNMENT -4 997169689Skan 998169689Skan/* Correct the offset of automatic variables and arguments. Note that 999169689Skan the MIPS debug format wants all automatic variables and arguments 1000169689Skan to be in terms of the virtual frame pointer (stack pointer before 1001169689Skan any adjustment in the function), while the MIPS 3.0 linker wants 1002169689Skan the frame pointer to be the stack pointer after the initial 1003169689Skan adjustment. */ 1004169689Skan 1005169689Skan#define DEBUGGER_AUTO_OFFSET(X) \ 1006169689Skan mips_debugger_offset (X, (HOST_WIDE_INT) 0) 1007169689Skan#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ 1008169689Skan mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) 1009169689Skan 1010169689Skan/* Target machine storage layout */ 1011169689Skan 1012169689Skan#define BITS_BIG_ENDIAN 0 1013169689Skan#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 1014169689Skan#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 1015169689Skan 1016169689Skan/* Define this to set the endianness to use in libgcc2.c, which can 1017169689Skan not depend on target_flags. */ 1018169689Skan#if !defined(MIPSEL) && !defined(__MIPSEL__) 1019169689Skan#define LIBGCC2_WORDS_BIG_ENDIAN 1 1020169689Skan#else 1021169689Skan#define LIBGCC2_WORDS_BIG_ENDIAN 0 1022169689Skan#endif 1023169689Skan 1024169689Skan#define MAX_BITS_PER_WORD 64 1025169689Skan 1026169689Skan/* Width of a word, in units (bytes). */ 1027169689Skan#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 1028169689Skan#ifndef IN_LIBGCC2 1029169689Skan#define MIN_UNITS_PER_WORD 4 1030169689Skan#endif 1031169689Skan 1032169689Skan/* For MIPS, width of a floating point register. */ 1033169689Skan#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) 1034169689Skan 1035169689Skan/* If register $f0 holds a floating-point value, $f(0 + FP_INC) is 1036169689Skan the next available register. */ 1037169689Skan#define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) 1038169689Skan 1039169689Skan/* The largest size of value that can be held in floating-point 1040169689Skan registers and moved with a single instruction. */ 1041169689Skan#define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG) 1042169689Skan 1043169689Skan/* The largest size of value that can be held in floating-point 1044169689Skan registers. */ 1045169689Skan#define UNITS_PER_FPVALUE \ 1046169689Skan (TARGET_SOFT_FLOAT ? 0 \ 1047169689Skan : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ 1048169689Skan : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) 1049169689Skan 1050169689Skan/* The number of bytes in a double. */ 1051169689Skan#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) 1052169689Skan 1053169689Skan#define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD) 1054169689Skan 1055169689Skan/* Set the sizes of the core types. */ 1056169689Skan#define SHORT_TYPE_SIZE 16 1057169689Skan#define INT_TYPE_SIZE 32 1058169689Skan#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) 1059169689Skan#define LONG_LONG_TYPE_SIZE 64 1060169689Skan 1061169689Skan#define FLOAT_TYPE_SIZE 32 1062169689Skan#define DOUBLE_TYPE_SIZE 64 1063169689Skan#define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) 1064169689Skan 1065169689Skan/* long double is not a fixed mode, but the idea is that, if we 1066169689Skan support long double, we also want a 128-bit integer type. */ 1067169689Skan#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE 1068169689Skan 1069169689Skan#ifdef IN_LIBGCC2 1070169689Skan#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 1071169689Skan || (defined _ABI64 && _MIPS_SIM == _ABI64) 1072169689Skan# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 1073169689Skan# else 1074169689Skan# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 1075169689Skan# endif 1076169689Skan#endif 1077169689Skan 1078169689Skan/* Width in bits of a pointer. */ 1079169689Skan#ifndef POINTER_SIZE 1080169689Skan#define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) 1081169689Skan#endif 1082169689Skan 1083169689Skan/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1084169689Skan#define PARM_BOUNDARY BITS_PER_WORD 1085169689Skan 1086169689Skan/* Allocation boundary (in *bits*) for the code of a function. */ 1087169689Skan#define FUNCTION_BOUNDARY 32 1088169689Skan 1089169689Skan/* Alignment of field after `int : 0' in a structure. */ 1090169689Skan#define EMPTY_FIELD_BOUNDARY 32 1091169689Skan 1092169689Skan/* Every structure's size must be a multiple of this. */ 1093169689Skan/* 8 is observed right on a DECstation and on riscos 4.02. */ 1094169689Skan#define STRUCTURE_SIZE_BOUNDARY 8 1095169689Skan 1096169689Skan/* There is no point aligning anything to a rounder boundary than this. */ 1097169689Skan#define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE 1098169689Skan 1099169689Skan/* All accesses must be aligned. */ 1100169689Skan#define STRICT_ALIGNMENT 1 1101169689Skan 1102169689Skan/* Define this if you wish to imitate the way many other C compilers 1103169689Skan handle alignment of bitfields and the structures that contain 1104169689Skan them. 1105169689Skan 1106169689Skan The behavior is that the type written for a bit-field (`int', 1107169689Skan `short', or other integer type) imposes an alignment for the 1108169689Skan entire structure, as if the structure really did contain an 1109169689Skan ordinary field of that type. In addition, the bit-field is placed 1110169689Skan within the structure so that it would fit within such a field, 1111169689Skan not crossing a boundary for it. 1112169689Skan 1113169689Skan Thus, on most machines, a bit-field whose type is written as `int' 1114169689Skan would not cross a four-byte boundary, and would force four-byte 1115169689Skan alignment for the whole structure. (The alignment used may not 1116169689Skan be four bytes; it is controlled by the other alignment 1117169689Skan parameters.) 1118169689Skan 1119169689Skan If the macro is defined, its definition should be a C expression; 1120169689Skan a nonzero value for the expression enables this behavior. */ 1121169689Skan 1122169689Skan#define PCC_BITFIELD_TYPE_MATTERS 1 1123169689Skan 1124169689Skan/* If defined, a C expression to compute the alignment given to a 1125169689Skan constant that is being placed in memory. CONSTANT is the constant 1126169689Skan and ALIGN is the alignment that the object would ordinarily have. 1127169689Skan The value of this macro is used instead of that alignment to align 1128169689Skan the object. 1129169689Skan 1130169689Skan If this macro is not defined, then ALIGN is used. 1131169689Skan 1132169689Skan The typical use of this macro is to increase alignment for string 1133169689Skan constants to be word aligned so that `strcpy' calls that copy 1134169689Skan constants can be done inline. */ 1135169689Skan 1136169689Skan#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 1137169689Skan ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 1138169689Skan && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 1139169689Skan 1140169689Skan/* If defined, a C expression to compute the alignment for a static 1141169689Skan variable. TYPE is the data type, and ALIGN is the alignment that 1142169689Skan the object would ordinarily have. The value of this macro is used 1143169689Skan instead of that alignment to align the object. 1144169689Skan 1145169689Skan If this macro is not defined, then ALIGN is used. 1146169689Skan 1147169689Skan One use of this macro is to increase alignment of medium-size 1148169689Skan data to make it all fit in fewer cache lines. Another is to 1149169689Skan cause character arrays to be word-aligned so that `strcpy' calls 1150169689Skan that copy constants to character arrays can be done inline. */ 1151169689Skan 1152169689Skan#undef DATA_ALIGNMENT 1153169689Skan#define DATA_ALIGNMENT(TYPE, ALIGN) \ 1154169689Skan ((((ALIGN) < BITS_PER_WORD) \ 1155169689Skan && (TREE_CODE (TYPE) == ARRAY_TYPE \ 1156169689Skan || TREE_CODE (TYPE) == UNION_TYPE \ 1157169689Skan || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 1158169689Skan 1159169689Skan 1160169689Skan#define PAD_VARARGS_DOWN \ 1161169689Skan (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1162169689Skan 1163169689Skan/* Define if operations between registers always perform the operation 1164169689Skan on the full register even if a narrower mode is specified. */ 1165169689Skan#define WORD_REGISTER_OPERATIONS 1166169689Skan 1167169689Skan/* When in 64 bit mode, move insns will sign extend SImode and CCmode 1168169689Skan moves. All other references are zero extended. */ 1169169689Skan#define LOAD_EXTEND_OP(MODE) \ 1170169689Skan (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ 1171169689Skan ? SIGN_EXTEND : ZERO_EXTEND) 1172169689Skan 1173169689Skan/* Define this macro if it is advisable to hold scalars in registers 1174169689Skan in a wider mode than that declared by the program. In such cases, 1175169689Skan the value is constrained to be within the bounds of the declared 1176169689Skan type, but kept valid in the wider mode. The signedness of the 1177169689Skan extension may differ from that of the type. */ 1178169689Skan 1179169689Skan#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1180169689Skan if (GET_MODE_CLASS (MODE) == MODE_INT \ 1181169689Skan && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 1182169689Skan { \ 1183169689Skan if ((MODE) == SImode) \ 1184169689Skan (UNSIGNEDP) = 0; \ 1185169689Skan (MODE) = Pmode; \ 1186169689Skan } 1187169689Skan 1188169689Skan/* Define if loading short immediate values into registers sign extends. */ 1189169689Skan#define SHORT_IMMEDIATES_SIGN_EXTEND 1190169689Skan 1191169689Skan/* The [d]clz instructions have the natural values at 0. */ 1192169689Skan 1193169689Skan#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1194169689Skan ((VALUE) = GET_MODE_BITSIZE (MODE), true) 1195169689Skan 1196169689Skan/* Standard register usage. */ 1197169689Skan 1198169689Skan/* Number of hardware registers. We have: 1199169689Skan 1200169689Skan - 32 integer registers 1201169689Skan - 32 floating point registers 1202169689Skan - 8 condition code registers 1203169689Skan - 2 accumulator registers (hi and lo) 1204169689Skan - 32 registers each for coprocessors 0, 2 and 3 1205169689Skan - 3 fake registers: 1206169689Skan - ARG_POINTER_REGNUM 1207169689Skan - FRAME_POINTER_REGNUM 1208169689Skan - FAKE_CALL_REGNO (see the comment above load_callsi for details) 1209169689Skan - 3 dummy entries that were used at various times in the past. 1210169689Skan - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE 1211169689Skan - 6 DSP control registers */ 1212169689Skan 1213169689Skan#define FIRST_PSEUDO_REGISTER 188 1214169689Skan 1215169689Skan/* By default, fix the kernel registers ($26 and $27), the global 1216169689Skan pointer ($28) and the stack pointer ($29). This can change 1217169689Skan depending on the command-line options. 1218169689Skan 1219169689Skan Regarding coprocessor registers: without evidence to the contrary, 1220169689Skan it's best to assume that each coprocessor register has a unique 1221169689Skan use. This can be overridden, in, e.g., override_options() or 1222169689Skan CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate 1223169689Skan for a particular target. */ 1224169689Skan 1225169689Skan#define FIXED_REGISTERS \ 1226169689Skan{ \ 1227169689Skan 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1228169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ 1229169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1230169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1231169689Skan 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ 1232169689Skan /* COP0 registers */ \ 1233169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1234169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1235169689Skan /* COP2 registers */ \ 1236169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1237169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1238169689Skan /* COP3 registers */ \ 1239169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1240169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1241169689Skan /* 6 DSP accumulator registers & 6 control registers */ \ 1242169689Skan 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ 1243169689Skan} 1244169689Skan 1245169689Skan 1246169689Skan/* Set up this array for o32 by default. 1247169689Skan 1248169689Skan Note that we don't mark $31 as a call-clobbered register. The idea is 1249169689Skan that it's really the call instructions themselves which clobber $31. 1250169689Skan We don't care what the called function does with it afterwards. 1251169689Skan 1252169689Skan This approach makes it easier to implement sibcalls. Unlike normal 1253169689Skan calls, sibcalls don't clobber $31, so the register reaches the 1254169689Skan called function in tact. EPILOGUE_USES says that $31 is useful 1255169689Skan to the called function. */ 1256169689Skan 1257169689Skan#define CALL_USED_REGISTERS \ 1258169689Skan{ \ 1259169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1260169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ 1261169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1262169689Skan 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1263169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1264169689Skan /* COP0 registers */ \ 1265169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1266169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1267169689Skan /* COP2 registers */ \ 1268169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1269169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1270169689Skan /* COP3 registers */ \ 1271169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1272169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1273169689Skan /* 6 DSP accumulator registers & 6 control registers */ \ 1274169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 1275169689Skan} 1276169689Skan 1277169689Skan 1278169689Skan/* Define this since $28, though fixed, is call-saved in many ABIs. */ 1279169689Skan 1280169689Skan#define CALL_REALLY_USED_REGISTERS \ 1281169689Skan{ /* General registers. */ \ 1282169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1283169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ 1284169689Skan /* Floating-point registers. */ \ 1285169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1286169689Skan 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1287169689Skan /* Others. */ \ 1288169689Skan 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1289169689Skan /* COP0 registers */ \ 1290169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1291169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1292169689Skan /* COP2 registers */ \ 1293169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1294169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1295169689Skan /* COP3 registers */ \ 1296169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1297169689Skan 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1298169689Skan /* 6 DSP accumulator registers & 6 control registers */ \ 1299169689Skan 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ 1300169689Skan} 1301169689Skan 1302169689Skan/* Internal macros to classify a register number as to whether it's a 1303169689Skan general purpose register, a floating point register, a 1304169689Skan multiply/divide register, or a status register. */ 1305169689Skan 1306169689Skan#define GP_REG_FIRST 0 1307169689Skan#define GP_REG_LAST 31 1308169689Skan#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 1309169689Skan#define GP_DBX_FIRST 0 1310169689Skan 1311169689Skan#define FP_REG_FIRST 32 1312169689Skan#define FP_REG_LAST 63 1313169689Skan#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 1314169689Skan#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) 1315169689Skan 1316169689Skan#define MD_REG_FIRST 64 1317169689Skan#define MD_REG_LAST 65 1318169689Skan#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) 1319169689Skan#define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) 1320169689Skan 1321169689Skan#define ST_REG_FIRST 67 1322169689Skan#define ST_REG_LAST 74 1323169689Skan#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) 1324169689Skan 1325169689Skan 1326169689Skan/* FIXME: renumber. */ 1327169689Skan#define COP0_REG_FIRST 80 1328169689Skan#define COP0_REG_LAST 111 1329169689Skan#define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) 1330169689Skan 1331169689Skan#define COP2_REG_FIRST 112 1332169689Skan#define COP2_REG_LAST 143 1333169689Skan#define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) 1334169689Skan 1335169689Skan#define COP3_REG_FIRST 144 1336169689Skan#define COP3_REG_LAST 175 1337169689Skan#define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) 1338169689Skan/* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */ 1339169689Skan#define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1) 1340169689Skan 1341169689Skan#define DSP_ACC_REG_FIRST 176 1342169689Skan#define DSP_ACC_REG_LAST 181 1343169689Skan#define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) 1344169689Skan 1345169689Skan#define AT_REGNUM (GP_REG_FIRST + 1) 1346169689Skan#define HI_REGNUM (MD_REG_FIRST + 0) 1347169689Skan#define LO_REGNUM (MD_REG_FIRST + 1) 1348169689Skan#define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0) 1349169689Skan#define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1) 1350169689Skan#define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2) 1351169689Skan#define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3) 1352169689Skan#define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4) 1353169689Skan#define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5) 1354169689Skan 1355169689Skan/* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. 1356169689Skan If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG 1357169689Skan should be used instead. */ 1358169689Skan#define FPSW_REGNUM ST_REG_FIRST 1359169689Skan 1360169689Skan#define GP_REG_P(REGNO) \ 1361169689Skan ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 1362169689Skan#define M16_REG_P(REGNO) \ 1363169689Skan (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) 1364169689Skan#define FP_REG_P(REGNO) \ 1365169689Skan ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 1366169689Skan#define MD_REG_P(REGNO) \ 1367169689Skan ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) 1368169689Skan#define ST_REG_P(REGNO) \ 1369169689Skan ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) 1370169689Skan#define COP0_REG_P(REGNO) \ 1371169689Skan ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) 1372169689Skan#define COP2_REG_P(REGNO) \ 1373169689Skan ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) 1374169689Skan#define COP3_REG_P(REGNO) \ 1375169689Skan ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) 1376169689Skan#define ALL_COP_REG_P(REGNO) \ 1377169689Skan ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) 1378169689Skan/* Test if REGNO is one of the 6 new DSP accumulators. */ 1379169689Skan#define DSP_ACC_REG_P(REGNO) \ 1380169689Skan ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) 1381169689Skan/* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ 1382169689Skan#define ACC_REG_P(REGNO) \ 1383169689Skan (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) 1384169689Skan/* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */ 1385169689Skan#define ACC_HI_REG_P(REGNO) \ 1386169689Skan ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \ 1387169689Skan || (REGNO) == AC3HI_REGNUM) 1388169689Skan 1389169689Skan#define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 1390169689Skan 1391169689Skan/* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used 1392169689Skan to initialize the mips16 gp pseudo register. */ 1393169689Skan#define CONST_GP_P(X) \ 1394169689Skan (GET_CODE (X) == CONST \ 1395169689Skan && GET_CODE (XEXP (X, 0)) == UNSPEC \ 1396169689Skan && XINT (XEXP (X, 0), 1) == UNSPEC_GP) 1397169689Skan 1398169689Skan/* Return coprocessor number from register number. */ 1399169689Skan 1400169689Skan#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ 1401169689Skan (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ 1402169689Skan : COP3_REG_P (REGNO) ? '3' : '?') 1403169689Skan 1404169689Skan 1405169689Skan#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE) 1406169689Skan 1407169689Skan/* To make the code simpler, HARD_REGNO_MODE_OK just references an 1408169689Skan array built in override_options. Because machmodes.h is not yet 1409169689Skan included before this file is processed, the MODE bound can't be 1410169689Skan expressed here. */ 1411169689Skan 1412169689Skanextern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; 1413169689Skan 1414169689Skan#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1415169689Skan mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ] 1416169689Skan 1417169689Skan/* Value is 1 if it is a good idea to tie two pseudo registers 1418169689Skan when one has mode MODE1 and one has mode MODE2. 1419169689Skan If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1420169689Skan for any hard reg, then this must be 0 for correct output. */ 1421169689Skan#define MODES_TIEABLE_P(MODE1, MODE2) \ 1422169689Skan ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ 1423169689Skan GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 1424169689Skan == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ 1425169689Skan GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 1426169689Skan 1427169689Skan/* Register to use for pushing function arguments. */ 1428169689Skan#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) 1429169689Skan 1430169689Skan/* These two registers don't really exist: they get eliminated to either 1431169689Skan the stack or hard frame pointer. */ 1432169689Skan#define ARG_POINTER_REGNUM 77 1433169689Skan#define FRAME_POINTER_REGNUM 78 1434169689Skan 1435169689Skan/* $30 is not available on the mips16, so we use $17 as the frame 1436169689Skan pointer. */ 1437169689Skan#define HARD_FRAME_POINTER_REGNUM \ 1438169689Skan (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) 1439169689Skan 1440169689Skan/* Value should be nonzero if functions must have frame pointers. 1441169689Skan Zero means the frame pointer need not be set up (and parms 1442169689Skan may be accessed via the stack pointer) in functions that seem suitable. 1443169689Skan This is computed in `reload', in reload1.c. */ 1444169689Skan#define FRAME_POINTER_REQUIRED (current_function_calls_alloca) 1445169689Skan 1446169689Skan/* Register in which static-chain is passed to a function. */ 1447169689Skan#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2) 1448169689Skan 1449169689Skan/* Registers used as temporaries in prologue/epilogue code. If we're 1450169689Skan generating mips16 code, these registers must come from the core set 1451169689Skan of 8. The prologue register mustn't conflict with any incoming 1452169689Skan arguments, the static chain pointer, or the frame pointer. The 1453169689Skan epilogue temporary mustn't conflict with the return registers, the 1454169689Skan frame pointer, the EH stack adjustment, or the EH data registers. */ 1455169689Skan 1456169689Skan#define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3) 1457169689Skan#define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) 1458169689Skan 1459169689Skan#define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) 1460169689Skan#define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) 1461169689Skan 1462169689Skan/* Define this macro if it is as good or better to call a constant 1463169689Skan function address than to call an address kept in a register. */ 1464169689Skan#define NO_FUNCTION_CSE 1 1465169689Skan 1466169689Skan/* The ABI-defined global pointer. Sometimes we use a different 1467169689Skan register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ 1468169689Skan#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) 1469169689Skan 1470169689Skan/* We normally use $28 as the global pointer. However, when generating 1471169689Skan n32/64 PIC, it is better for leaf functions to use a call-clobbered 1472169689Skan register instead. They can then avoid saving and restoring $28 1473169689Skan and perhaps avoid using a frame at all. 1474169689Skan 1475169689Skan When a leaf function uses something other than $28, mips_expand_prologue 1476169689Skan will modify pic_offset_table_rtx in place. Take the register number 1477169689Skan from there after reload. */ 1478169689Skan#define PIC_OFFSET_TABLE_REGNUM \ 1479169689Skan (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) 1480169689Skan 1481169689Skan#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25) 1482169689Skan 1483169689Skan/* Define the classes of registers for register constraints in the 1484169689Skan machine description. Also define ranges of constants. 1485169689Skan 1486169689Skan One of the classes must always be named ALL_REGS and include all hard regs. 1487169689Skan If there is more than one class, another class must be named NO_REGS 1488169689Skan and contain no registers. 1489169689Skan 1490169689Skan The name GENERAL_REGS must be the name of a class (or an alias for 1491169689Skan another name such as ALL_REGS). This is the class of registers 1492169689Skan that is allowed by "g" or "r" in a register constraint. 1493169689Skan Also, registers outside this class are allocated only when 1494169689Skan instructions express preferences for them. 1495169689Skan 1496169689Skan The classes must be numbered in nondecreasing order; that is, 1497169689Skan a larger-numbered class must never be contained completely 1498169689Skan in a smaller-numbered class. 1499169689Skan 1500169689Skan For any two classes, it is very desirable that there be another 1501169689Skan class that represents their union. */ 1502169689Skan 1503169689Skanenum reg_class 1504169689Skan{ 1505169689Skan NO_REGS, /* no registers in set */ 1506169689Skan M16_NA_REGS, /* mips16 regs not used to pass args */ 1507169689Skan M16_REGS, /* mips16 directly accessible registers */ 1508169689Skan T_REG, /* mips16 T register ($24) */ 1509169689Skan M16_T_REGS, /* mips16 registers plus T register */ 1510169689Skan PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ 1511169689Skan V1_REG, /* Register $v1 ($3) used for TLS access. */ 1512169689Skan LEA_REGS, /* Every GPR except $25 */ 1513169689Skan GR_REGS, /* integer registers */ 1514169689Skan FP_REGS, /* floating point registers */ 1515169689Skan HI_REG, /* hi register */ 1516169689Skan LO_REG, /* lo register */ 1517169689Skan MD_REGS, /* multiply/divide registers (hi/lo) */ 1518169689Skan COP0_REGS, /* generic coprocessor classes */ 1519169689Skan COP2_REGS, 1520169689Skan COP3_REGS, 1521169689Skan HI_AND_GR_REGS, /* union classes */ 1522169689Skan LO_AND_GR_REGS, 1523169689Skan HI_AND_FP_REGS, 1524169689Skan COP0_AND_GR_REGS, 1525169689Skan COP2_AND_GR_REGS, 1526169689Skan COP3_AND_GR_REGS, 1527169689Skan ALL_COP_REGS, 1528169689Skan ALL_COP_AND_GR_REGS, 1529169689Skan ST_REGS, /* status registers (fp status) */ 1530169689Skan DSP_ACC_REGS, /* DSP accumulator registers */ 1531169689Skan ACC_REGS, /* Hi/Lo and DSP accumulator registers */ 1532169689Skan ALL_REGS, /* all registers */ 1533169689Skan LIM_REG_CLASSES /* max value + 1 */ 1534169689Skan}; 1535169689Skan 1536169689Skan#define N_REG_CLASSES (int) LIM_REG_CLASSES 1537169689Skan 1538169689Skan#define GENERAL_REGS GR_REGS 1539169689Skan 1540169689Skan/* An initializer containing the names of the register classes as C 1541169689Skan string constants. These names are used in writing some of the 1542169689Skan debugging dumps. */ 1543169689Skan 1544169689Skan#define REG_CLASS_NAMES \ 1545169689Skan{ \ 1546169689Skan "NO_REGS", \ 1547169689Skan "M16_NA_REGS", \ 1548169689Skan "M16_REGS", \ 1549169689Skan "T_REG", \ 1550169689Skan "M16_T_REGS", \ 1551169689Skan "PIC_FN_ADDR_REG", \ 1552169689Skan "V1_REG", \ 1553169689Skan "LEA_REGS", \ 1554169689Skan "GR_REGS", \ 1555169689Skan "FP_REGS", \ 1556169689Skan "HI_REG", \ 1557169689Skan "LO_REG", \ 1558169689Skan "MD_REGS", \ 1559169689Skan /* coprocessor registers */ \ 1560169689Skan "COP0_REGS", \ 1561169689Skan "COP2_REGS", \ 1562169689Skan "COP3_REGS", \ 1563169689Skan "HI_AND_GR_REGS", \ 1564169689Skan "LO_AND_GR_REGS", \ 1565169689Skan "HI_AND_FP_REGS", \ 1566169689Skan "COP0_AND_GR_REGS", \ 1567169689Skan "COP2_AND_GR_REGS", \ 1568169689Skan "COP3_AND_GR_REGS", \ 1569169689Skan "ALL_COP_REGS", \ 1570169689Skan "ALL_COP_AND_GR_REGS", \ 1571169689Skan "ST_REGS", \ 1572169689Skan "DSP_ACC_REGS", \ 1573169689Skan "ACC_REGS", \ 1574169689Skan "ALL_REGS" \ 1575169689Skan} 1576169689Skan 1577169689Skan/* An initializer containing the contents of the register classes, 1578169689Skan as integers which are bit masks. The Nth integer specifies the 1579169689Skan contents of class N. The way the integer MASK is interpreted is 1580169689Skan that register R is in the class if `MASK & (1 << R)' is 1. 1581169689Skan 1582169689Skan When the machine has more than 32 registers, an integer does not 1583169689Skan suffice. Then the integers are replaced by sub-initializers, 1584169689Skan braced groupings containing several integers. Each 1585169689Skan sub-initializer must be suitable as an initializer for the type 1586169689Skan `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 1587169689Skan 1588169689Skan#define REG_CLASS_CONTENTS \ 1589169689Skan{ \ 1590169689Skan { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \ 1591169689Skan { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\ 1592169689Skan { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \ 1593169689Skan { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \ 1594169689Skan { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \ 1595169689Skan { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \ 1596169689Skan { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \ 1597169689Skan { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \ 1598169689Skan { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \ 1599169689Skan { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \ 1600169689Skan { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \ 1601169689Skan { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \ 1602169689Skan { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \ 1603169689Skan { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \ 1604169689Skan { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \ 1605169689Skan { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \ 1606169689Skan { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \ 1607169689Skan { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \ 1608169689Skan { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \ 1609169689Skan { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \ 1610169689Skan { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \ 1611169689Skan { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \ 1612169689Skan { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ 1613169689Skan { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ 1614169689Skan { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \ 1615169689Skan { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \ 1616169689Skan { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \ 1617169689Skan { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \ 1618169689Skan} 1619169689Skan 1620169689Skan 1621169689Skan/* A C expression whose value is a register class containing hard 1622169689Skan register REGNO. In general there is more that one such class; 1623169689Skan choose a class which is "minimal", meaning that no smaller class 1624169689Skan also contains the register. */ 1625169689Skan 1626169689Skanextern const enum reg_class mips_regno_to_class[]; 1627169689Skan 1628169689Skan#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] 1629169689Skan 1630169689Skan/* A macro whose definition is the name of the class to which a 1631169689Skan valid base register must belong. A base register is one used in 1632169689Skan an address which is the register value plus a displacement. */ 1633169689Skan 1634169689Skan#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS) 1635169689Skan 1636169689Skan/* A macro whose definition is the name of the class to which a 1637169689Skan valid index register must belong. An index register is one used 1638169689Skan in an address where its value is either multiplied by a scale 1639169689Skan factor or added to another register (as well as added to a 1640169689Skan displacement). */ 1641169689Skan 1642169689Skan#define INDEX_REG_CLASS NO_REGS 1643169689Skan 1644169689Skan/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1645169689Skan registers explicitly used in the rtl to be used as spill registers 1646169689Skan but prevents the compiler from extending the lifetime of these 1647169689Skan registers. */ 1648169689Skan 1649169689Skan#define SMALL_REGISTER_CLASSES (TARGET_MIPS16) 1650169689Skan 1651169689Skan/* This macro is used later on in the file. */ 1652169689Skan#define GR_REG_CLASS_P(CLASS) \ 1653169689Skan ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \ 1654169689Skan || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \ 1655169689Skan || (CLASS) == V1_REG \ 1656169689Skan || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS) 1657169689Skan 1658169689Skan/* This macro is also used later on in the file. */ 1659169689Skan#define COP_REG_CLASS_P(CLASS) \ 1660169689Skan ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS) 1661169689Skan 1662169689Skan/* REG_ALLOC_ORDER is to order in which to allocate registers. This 1663169689Skan is the default value (allocate the registers in numeric order). We 1664169689Skan define it just so that we can override it for the mips16 target in 1665169689Skan ORDER_REGS_FOR_LOCAL_ALLOC. */ 1666169689Skan 1667169689Skan#define REG_ALLOC_ORDER \ 1668169689Skan{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 1669169689Skan 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 1670169689Skan 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1671169689Skan 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 1672169689Skan 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 1673169689Skan 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 1674169689Skan 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ 1675169689Skan 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ 1676169689Skan 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ 1677169689Skan 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ 1678169689Skan 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ 1679169689Skan 176,177,178,179,180,181,182,183,184,185,186,187 \ 1680169689Skan} 1681169689Skan 1682169689Skan/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 1683169689Skan to be rearranged based on a particular function. On the mips16, we 1684169689Skan want to allocate $24 (T_REG) before other registers for 1685169689Skan instructions for which it is possible. */ 1686169689Skan 1687169689Skan#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () 1688169689Skan 1689169689Skan/* True if VALUE is an unsigned 6-bit number. */ 1690169689Skan 1691169689Skan#define UIMM6_OPERAND(VALUE) \ 1692169689Skan (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) 1693169689Skan 1694169689Skan/* True if VALUE is a signed 10-bit number. */ 1695169689Skan 1696169689Skan#define IMM10_OPERAND(VALUE) \ 1697169689Skan ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) 1698169689Skan 1699169689Skan/* True if VALUE is a signed 16-bit number. */ 1700169689Skan 1701169689Skan#define SMALL_OPERAND(VALUE) \ 1702169689Skan ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) 1703169689Skan 1704169689Skan/* True if VALUE is an unsigned 16-bit number. */ 1705169689Skan 1706169689Skan#define SMALL_OPERAND_UNSIGNED(VALUE) \ 1707169689Skan (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) 1708169689Skan 1709169689Skan/* True if VALUE can be loaded into a register using LUI. */ 1710169689Skan 1711169689Skan#define LUI_OPERAND(VALUE) \ 1712169689Skan (((VALUE) | 0x7fff0000) == 0x7fff0000 \ 1713169689Skan || ((VALUE) | 0x7fff0000) + 0x10000 == 0) 1714169689Skan 1715169689Skan/* Return a value X with the low 16 bits clear, and such that 1716169689Skan VALUE - X is a signed 16-bit value. */ 1717169689Skan 1718169689Skan#define CONST_HIGH_PART(VALUE) \ 1719169689Skan (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) 1720169689Skan 1721169689Skan#define CONST_LOW_PART(VALUE) \ 1722169689Skan ((VALUE) - CONST_HIGH_PART (VALUE)) 1723169689Skan 1724169689Skan#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) 1725169689Skan#define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) 1726169689Skan#define LUI_INT(X) LUI_OPERAND (INTVAL (X)) 1727169689Skan 1728169689Skan#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1729169689Skan mips_preferred_reload_class (X, CLASS) 1730169689Skan 1731169689Skan/* Certain machines have the property that some registers cannot be 1732169689Skan copied to some other registers without using memory. Define this 1733169689Skan macro on those machines to be a C expression that is nonzero if 1734169689Skan objects of mode MODE in registers of CLASS1 can only be copied to 1735169689Skan registers of class CLASS2 by storing a register of CLASS1 into 1736169689Skan memory and loading that memory location into a register of CLASS2. 1737169689Skan 1738169689Skan Do not define this macro if its value would always be zero. */ 1739169689Skan#if 0 1740169689Skan#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1741169689Skan ((!TARGET_DEBUG_H_MODE \ 1742169689Skan && GET_MODE_CLASS (MODE) == MODE_INT \ 1743169689Skan && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \ 1744169689Skan || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \ 1745169689Skan || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \ 1746169689Skan && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \ 1747169689Skan || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS)))) 1748169689Skan#endif 1749169689Skan/* The HI and LO registers can only be reloaded via the general 1750169689Skan registers. Condition code registers can only be loaded to the 1751169689Skan general registers, and from the floating point registers. */ 1752169689Skan 1753169689Skan#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1754169689Skan mips_secondary_reload_class (CLASS, MODE, X, 1) 1755169689Skan#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1756169689Skan mips_secondary_reload_class (CLASS, MODE, X, 0) 1757169689Skan 1758169689Skan/* Return the maximum number of consecutive registers 1759169689Skan needed to represent mode MODE in a register of class CLASS. */ 1760169689Skan 1761169689Skan#define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) 1762169689Skan 1763169689Skan#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1764169689Skan mips_cannot_change_mode_class (FROM, TO, CLASS) 1765169689Skan 1766169689Skan/* Stack layout; function entry, exit and calling. */ 1767169689Skan 1768169689Skan#define STACK_GROWS_DOWNWARD 1769169689Skan 1770169689Skan/* The offset of the first local variable from the beginning of the frame. 1771169689Skan See compute_frame_size for details about the frame layout. 1772169689Skan 1773169689Skan ??? If flag_profile_values is true, and we are generating 32-bit code, then 1774169689Skan we assume that we will need 16 bytes of argument space. This is because 1775169689Skan the value profiling code may emit calls to cmpdi2 in leaf functions. 1776169689Skan Without this hack, the local variables will start at sp+8 and the gp save 1777169689Skan area will be at sp+16, and thus they will overlap. compute_frame_size is 1778169689Skan OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which 1779169689Skan will end up as 24 instead of 8. This won't be needed if profiling code is 1780169689Skan inserted before virtual register instantiation. */ 1781169689Skan 1782169689Skan#define STARTING_FRAME_OFFSET \ 1783169689Skan ((flag_profile_values && ! TARGET_64BIT \ 1784169689Skan ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \ 1785169689Skan : current_function_outgoing_args_size) \ 1786169689Skan + (TARGET_ABICALLS && !TARGET_NEWABI \ 1787169689Skan ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)) 1788169689Skan 1789169689Skan#define RETURN_ADDR_RTX mips_return_addr 1790169689Skan 1791169689Skan/* Since the mips16 ISA mode is encoded in the least-significant bit 1792169689Skan of the address, mask it off return addresses for purposes of 1793169689Skan finding exception handling regions. */ 1794169689Skan 1795169689Skan#define MASK_RETURN_ADDR GEN_INT (-2) 1796169689Skan 1797169689Skan 1798169689Skan/* Similarly, don't use the least-significant bit to tell pointers to 1799169689Skan code from vtable index. */ 1800169689Skan 1801169689Skan#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 1802169689Skan 1803169689Skan/* The eliminations to $17 are only used for mips16 code. See the 1804169689Skan definition of HARD_FRAME_POINTER_REGNUM. */ 1805169689Skan 1806169689Skan#define ELIMINABLE_REGS \ 1807169689Skan{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1808169689Skan { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 1809169689Skan { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ 1810169689Skan { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1811169689Skan { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 1812169689Skan { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} 1813169689Skan 1814169689Skan/* We can always eliminate to the hard frame pointer. We can eliminate 1815169689Skan to the stack pointer unless a frame pointer is needed. 1816169689Skan 1817169689Skan In mips16 mode, we need a frame pointer for a large frame; otherwise, 1818169689Skan reload may be unable to compute the address of a local variable, 1819169689Skan since there is no way to add a large constant to the stack pointer 1820169689Skan without using a temporary register. */ 1821169689Skan#define CAN_ELIMINATE(FROM, TO) \ 1822169689Skan ((TO) == HARD_FRAME_POINTER_REGNUM \ 1823169689Skan || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \ 1824169689Skan && (!TARGET_MIPS16 \ 1825169689Skan || compute_frame_size (get_frame_size ()) < 32768))) 1826169689Skan 1827169689Skan#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1828169689Skan (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) 1829169689Skan 1830169689Skan/* Allocate stack space for arguments at the beginning of each function. */ 1831169689Skan#define ACCUMULATE_OUTGOING_ARGS 1 1832169689Skan 1833169689Skan/* The argument pointer always points to the first argument. */ 1834169689Skan#define FIRST_PARM_OFFSET(FNDECL) 0 1835169689Skan 1836169689Skan/* o32 and o64 reserve stack space for all argument registers. */ 1837169689Skan#define REG_PARM_STACK_SPACE(FNDECL) \ 1838169689Skan (TARGET_OLDABI \ 1839169689Skan ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ 1840169689Skan : 0) 1841169689Skan 1842169689Skan/* Define this if it is the responsibility of the caller to 1843169689Skan allocate the area reserved for arguments passed in registers. 1844169689Skan If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 1845169689Skan of this macro is to determine whether the space is included in 1846169689Skan `current_function_outgoing_args_size'. */ 1847169689Skan#define OUTGOING_REG_PARM_STACK_SPACE 1848169689Skan 1849169689Skan#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) 1850169689Skan 1851169689Skan#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1852169689Skan 1853169689Skan/* Symbolic macros for the registers used to return integer and floating 1854169689Skan point values. */ 1855169689Skan 1856169689Skan#define GP_RETURN (GP_REG_FIRST + 2) 1857169689Skan#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) 1858169689Skan 1859169689Skan#define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) 1860169689Skan 1861169689Skan/* Symbolic macros for the first/last argument registers. */ 1862169689Skan 1863169689Skan#define GP_ARG_FIRST (GP_REG_FIRST + 4) 1864169689Skan#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 1865169689Skan#define FP_ARG_FIRST (FP_REG_FIRST + 12) 1866169689Skan#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 1867169689Skan 1868169689Skan#define LIBCALL_VALUE(MODE) \ 1869169689Skan mips_function_value (NULL_TREE, NULL, (MODE)) 1870169689Skan 1871169689Skan#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1872169689Skan mips_function_value ((VALTYPE), (FUNC), VOIDmode) 1873169689Skan 1874169689Skan/* 1 if N is a possible register number for a function value. 1875169689Skan On the MIPS, R2 R3 and F0 F2 are the only register thus used. 1876169689Skan Currently, R2 and F0 are only implemented here (C has no complex type) */ 1877169689Skan 1878169689Skan#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \ 1879169689Skan || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \ 1880169689Skan && (N) == FP_RETURN + 2)) 1881169689Skan 1882169689Skan/* 1 if N is a possible register number for function argument passing. 1883169689Skan We have no FP argument registers when soft-float. When FP registers 1884169689Skan are 32 bits, we can't directly reference the odd numbered ones. */ 1885169689Skan 1886169689Skan#define FUNCTION_ARG_REGNO_P(N) \ 1887169689Skan ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ 1888169689Skan || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \ 1889169689Skan && !fixed_regs[N]) 1890169689Skan 1891169689Skan/* This structure has to cope with two different argument allocation 1892169689Skan schemes. Most MIPS ABIs view the arguments as a structure, of which 1893169689Skan the first N words go in registers and the rest go on the stack. If I 1894169689Skan < N, the Ith word might go in Ith integer argument register or in a 1895169689Skan floating-point register. For these ABIs, we only need to remember 1896169689Skan the offset of the current argument into the structure. 1897169689Skan 1898169689Skan The EABI instead allocates the integer and floating-point arguments 1899169689Skan separately. The first N words of FP arguments go in FP registers, 1900169689Skan the rest go on the stack. Likewise, the first N words of the other 1901169689Skan arguments go in integer registers, and the rest go on the stack. We 1902169689Skan need to maintain three counts: the number of integer registers used, 1903169689Skan the number of floating-point registers used, and the number of words 1904169689Skan passed on the stack. 1905169689Skan 1906169689Skan We could keep separate information for the two ABIs (a word count for 1907169689Skan the standard ABIs, and three separate counts for the EABI). But it 1908169689Skan seems simpler to view the standard ABIs as forms of EABI that do not 1909169689Skan allocate floating-point registers. 1910169689Skan 1911169689Skan So for the standard ABIs, the first N words are allocated to integer 1912169689Skan registers, and function_arg decides on an argument-by-argument basis 1913169689Skan whether that argument should really go in an integer register, or in 1914169689Skan a floating-point one. */ 1915169689Skan 1916169689Skantypedef struct mips_args { 1917169689Skan /* Always true for varargs functions. Otherwise true if at least 1918169689Skan one argument has been passed in an integer register. */ 1919169689Skan int gp_reg_found; 1920169689Skan 1921169689Skan /* The number of arguments seen so far. */ 1922169689Skan unsigned int arg_number; 1923169689Skan 1924169689Skan /* The number of integer registers used so far. For all ABIs except 1925169689Skan EABI, this is the number of words that have been added to the 1926169689Skan argument structure, limited to MAX_ARGS_IN_REGISTERS. */ 1927169689Skan unsigned int num_gprs; 1928169689Skan 1929169689Skan /* For EABI, the number of floating-point registers used so far. */ 1930169689Skan unsigned int num_fprs; 1931169689Skan 1932169689Skan /* The number of words passed on the stack. */ 1933169689Skan unsigned int stack_words; 1934169689Skan 1935169689Skan /* On the mips16, we need to keep track of which floating point 1936169689Skan arguments were passed in general registers, but would have been 1937169689Skan passed in the FP regs if this were a 32 bit function, so that we 1938169689Skan can move them to the FP regs if we wind up calling a 32 bit 1939169689Skan function. We record this information in fp_code, encoded in base 1940169689Skan four. A zero digit means no floating point argument, a one digit 1941169689Skan means an SFmode argument, and a two digit means a DFmode argument, 1942169689Skan and a three digit is not used. The low order digit is the first 1943169689Skan argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by 1944169689Skan an SFmode argument. ??? A more sophisticated approach will be 1945169689Skan needed if MIPS_ABI != ABI_32. */ 1946169689Skan int fp_code; 1947169689Skan 1948169689Skan /* True if the function has a prototype. */ 1949169689Skan int prototype; 1950169689Skan} CUMULATIVE_ARGS; 1951169689Skan 1952169689Skan/* Initialize a variable CUM of type CUMULATIVE_ARGS 1953169689Skan for a call to a function whose data type is FNTYPE. 1954169689Skan For a library call, FNTYPE is 0. */ 1955169689Skan 1956169689Skan#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1957169689Skan init_cumulative_args (&CUM, FNTYPE, LIBNAME) \ 1958169689Skan 1959169689Skan/* Update the data in CUM to advance over an argument 1960169689Skan of mode MODE and data type TYPE. 1961169689Skan (TYPE is null for libcalls where that information may not be available.) */ 1962169689Skan 1963169689Skan#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1964169689Skan function_arg_advance (&CUM, MODE, TYPE, NAMED) 1965169689Skan 1966169689Skan/* Determine where to put an argument to a function. 1967169689Skan Value is zero to push the argument on the stack, 1968169689Skan or a hard register in which to store the argument. 1969169689Skan 1970169689Skan MODE is the argument's machine mode. 1971169689Skan TYPE is the data type of the argument (as a tree). 1972169689Skan This is null for libcalls where that information may 1973169689Skan not be available. 1974169689Skan CUM is a variable of type CUMULATIVE_ARGS which gives info about 1975169689Skan the preceding args and about the function being called. 1976169689Skan NAMED is nonzero if this argument is a named parameter 1977169689Skan (otherwise it is an extra parameter matching an ellipsis). */ 1978169689Skan 1979169689Skan#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1980169689Skan function_arg( &CUM, MODE, TYPE, NAMED) 1981169689Skan 1982169689Skan#define FUNCTION_ARG_BOUNDARY function_arg_boundary 1983169689Skan 1984169689Skan#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1985169689Skan (mips_pad_arg_upward (MODE, TYPE) ? upward : downward) 1986169689Skan 1987169689Skan#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1988169689Skan (mips_pad_reg_upward (MODE, TYPE) ? upward : downward) 1989169689Skan 1990169689Skan/* True if using EABI and varargs can be passed in floating-point 1991169689Skan registers. Under these conditions, we need a more complex form 1992169689Skan of va_list, which tracks GPR, FPR and stack arguments separately. */ 1993169689Skan#define EABI_FLOAT_VARARGS_P \ 1994169689Skan (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) 1995169689Skan 1996169689Skan 1997169689Skan/* Say that the epilogue uses the return address register. Note that 1998169689Skan in the case of sibcalls, the values "used by the epilogue" are 1999169689Skan considered live at the start of the called function. */ 2000169689Skan#define EPILOGUE_USES(REGNO) ((REGNO) == 31) 2001169689Skan 2002169689Skan/* Treat LOC as a byte offset from the stack pointer and round it up 2003169689Skan to the next fully-aligned offset. */ 2004169689Skan#define MIPS_STACK_ALIGN(LOC) \ 2005169689Skan (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8) 2006169689Skan 2007169689Skan 2008169689Skan/* Implement `va_start' for varargs and stdarg. */ 2009169689Skan#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 2010169689Skan mips_va_start (valist, nextarg) 2011169689Skan 2012169689Skan/* Output assembler code to FILE to increment profiler label # LABELNO 2013169689Skan for profiling a function entry. */ 2014169689Skan 2015169689Skan#define FUNCTION_PROFILER(FILE, LABELNO) \ 2016169689Skan{ \ 2017169689Skan if (TARGET_MIPS16) \ 2018169689Skan sorry ("mips16 function profiling"); \ 2019169689Skan fprintf (FILE, "\t.set\tnoat\n"); \ 2020169689Skan fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \ 2021169689Skan reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \ 2022169689Skan if (!TARGET_NEWABI) \ 2023169689Skan { \ 2024169689Skan fprintf (FILE, \ 2025169689Skan "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \ 2026169689Skan TARGET_64BIT ? "dsubu" : "subu", \ 2027169689Skan reg_names[STACK_POINTER_REGNUM], \ 2028169689Skan reg_names[STACK_POINTER_REGNUM], \ 2029169689Skan Pmode == DImode ? 16 : 8); \ 2030169689Skan } \ 2031169689Skan fprintf (FILE, "\tjal\t_mcount\n"); \ 2032169689Skan fprintf (FILE, "\t.set\tat\n"); \ 2033169689Skan} 2034169689Skan 2035169689Skan/* No mips port has ever used the profiler counter word, so don't emit it 2036169689Skan or the label for it. */ 2037169689Skan 2038169689Skan#define NO_PROFILE_COUNTERS 1 2039169689Skan 2040169689Skan/* Define this macro if the code for function profiling should come 2041169689Skan before the function prologue. Normally, the profiling code comes 2042169689Skan after. */ 2043169689Skan 2044169689Skan/* #define PROFILE_BEFORE_PROLOGUE */ 2045169689Skan 2046169689Skan/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 2047169689Skan the stack pointer does not matter. The value is tested only in 2048169689Skan functions that have frame pointers. 2049169689Skan No definition is equivalent to always zero. */ 2050169689Skan 2051169689Skan#define EXIT_IGNORE_STACK 1 2052169689Skan 2053169689Skan 2054169689Skan/* A C statement to output, on the stream FILE, assembler code for a 2055169689Skan block of data that contains the constant parts of a trampoline. 2056169689Skan This code should not include a label--the label is taken care of 2057169689Skan automatically. */ 2058169689Skan 2059169689Skan#define TRAMPOLINE_TEMPLATE(STREAM) \ 2060169689Skan{ \ 2061169689Skan if (ptr_mode == DImode) \ 2062169689Skan fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \ 2063169689Skan else \ 2064169689Skan fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \ 2065169689Skan fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \ 2066169689Skan fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \ 2067169689Skan if (ptr_mode == DImode) \ 2068169689Skan { \ 2069169689Skan fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \ 2070169689Skan fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \ 2071169689Skan fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \ 2072169689Skan } \ 2073169689Skan else \ 2074169689Skan { \ 2075169689Skan fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \ 2076169689Skan fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \ 2077169689Skan fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \ 2078169689Skan } \ 2079169689Skan fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \ 2080169689Skan if (ptr_mode == DImode) \ 2081169689Skan { \ 2082169689Skan fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \ 2083169689Skan fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \ 2084169689Skan fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \ 2085169689Skan } \ 2086169689Skan else \ 2087169689Skan { \ 2088169689Skan fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \ 2089169689Skan fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \ 2090169689Skan fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \ 2091169689Skan } \ 2092169689Skan} 2093169689Skan 2094169689Skan/* A C expression for the size in bytes of the trampoline, as an 2095169689Skan integer. */ 2096169689Skan 2097169689Skan#define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2) 2098169689Skan 2099169689Skan/* Alignment required for trampolines, in bits. */ 2100169689Skan 2101169689Skan#define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode) 2102169689Skan 2103169689Skan/* INITIALIZE_TRAMPOLINE calls this library function to flush 2104169689Skan program and data caches. */ 2105169689Skan 2106169689Skan#ifndef CACHE_FLUSH_FUNC 2107169689Skan#define CACHE_FLUSH_FUNC "_flush_cache" 2108169689Skan#endif 2109169689Skan 2110169689Skan/* A C statement to initialize the variable parts of a trampoline. 2111169689Skan ADDR is an RTX for the address of the trampoline; FNADDR is an 2112169689Skan RTX for the address of the nested function; STATIC_CHAIN is an 2113169689Skan RTX for the static chain value that should be passed to the 2114169689Skan function when it is called. */ 2115169689Skan 2116169689Skan#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \ 2117169689Skan{ \ 2118169689Skan rtx func_addr, chain_addr; \ 2119169689Skan \ 2120169689Skan func_addr = plus_constant (ADDR, 32); \ 2121169689Skan chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \ 2122169689Skan emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \ 2123169689Skan emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \ 2124169689Skan \ 2125169689Skan /* Flush both caches. We need to flush the data cache in case \ 2126169689Skan the system has a write-back cache. */ \ 2127169689Skan /* ??? Should check the return value for errors. */ \ 2128169689Skan if (mips_cache_flush_func && mips_cache_flush_func[0]) \ 2129169689Skan emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ 2130169689Skan 0, VOIDmode, 3, ADDR, Pmode, \ 2131169689Skan GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\ 2132169689Skan GEN_INT (3), TYPE_MODE (integer_type_node)); \ 2133169689Skan} 2134169689Skan 2135169689Skan/* Addressing modes, and classification of registers for them. */ 2136169689Skan 2137169689Skan#define REGNO_OK_FOR_INDEX_P(REGNO) 0 2138169689Skan#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 2139169689Skan mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) 2140169689Skan 2141169689Skan/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2142169689Skan and check its validity for a certain class. 2143169689Skan We have two alternate definitions for each of them. 2144169689Skan The usual definition accepts all pseudo regs; the other rejects them all. 2145169689Skan The symbol REG_OK_STRICT causes the latter definition to be used. 2146169689Skan 2147169689Skan Most source files want to accept pseudo regs in the hope that 2148169689Skan they will get allocated to the class that the insn wants them to be in. 2149169689Skan Some source files that are used after register allocation 2150169689Skan need to be strict. */ 2151169689Skan 2152169689Skan#ifndef REG_OK_STRICT 2153169689Skan#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2154169689Skan mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) 2155169689Skan#else 2156169689Skan#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2157169689Skan mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) 2158169689Skan#endif 2159169689Skan 2160169689Skan#define REG_OK_FOR_INDEX_P(X) 0 2161169689Skan 2162169689Skan 2163169689Skan/* Maximum number of registers that can appear in a valid memory address. */ 2164169689Skan 2165169689Skan#define MAX_REGS_PER_ADDRESS 1 2166169689Skan 2167169689Skan#ifdef REG_OK_STRICT 2168169689Skan#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2169169689Skan{ \ 2170169689Skan if (mips_legitimate_address_p (MODE, X, 1)) \ 2171169689Skan goto ADDR; \ 2172169689Skan} 2173169689Skan#else 2174169689Skan#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2175169689Skan{ \ 2176169689Skan if (mips_legitimate_address_p (MODE, X, 0)) \ 2177169689Skan goto ADDR; \ 2178169689Skan} 2179169689Skan#endif 2180169689Skan 2181169689Skan/* Check for constness inline but use mips_legitimate_address_p 2182169689Skan to check whether a constant really is an address. */ 2183169689Skan 2184169689Skan#define CONSTANT_ADDRESS_P(X) \ 2185169689Skan (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0)) 2186169689Skan 2187169689Skan#define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0) 2188169689Skan 2189169689Skan#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2190169689Skan do { \ 2191169689Skan if (mips_legitimize_address (&(X), MODE)) \ 2192169689Skan goto WIN; \ 2193169689Skan } while (0) 2194169689Skan 2195169689Skan 2196169689Skan/* A C statement or compound statement with a conditional `goto 2197169689Skan LABEL;' executed if memory address X (an RTX) can have different 2198169689Skan meanings depending on the machine mode of the memory reference it 2199169689Skan is used for. 2200169689Skan 2201169689Skan Autoincrement and autodecrement addresses typically have 2202169689Skan mode-dependent effects because the amount of the increment or 2203169689Skan decrement is the size of the operand being addressed. Some 2204169689Skan machines have other mode-dependent addresses. Many RISC machines 2205169689Skan have no mode-dependent addresses. 2206169689Skan 2207169689Skan You may assume that ADDR is a valid address for the machine. */ 2208169689Skan 2209169689Skan#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} 2210169689Skan 2211169689Skan/* This handles the magic '..CURRENT_FUNCTION' symbol, which means 2212169689Skan 'the start of the function that this code is output in'. */ 2213169689Skan 2214169689Skan#define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2215169689Skan if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 2216169689Skan asm_fprintf ((FILE), "%U%s", \ 2217169689Skan XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ 2218169689Skan else \ 2219169689Skan asm_fprintf ((FILE), "%U%s", (NAME)) 2220169689Skan 2221169689Skan/* Flag to mark a function decl symbol that requires a long call. */ 2222169689Skan#define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) 2223169689Skan#define SYMBOL_REF_LONG_CALL_P(X) \ 2224169689Skan ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) 2225169689Skan 2226169689Skan/* Specify the machine mode that this machine uses 2227169689Skan for the index in the tablejump instruction. 2228169689Skan ??? Using HImode in mips16 mode can cause overflow. */ 2229169689Skan#define CASE_VECTOR_MODE \ 2230169689Skan (TARGET_MIPS16 ? HImode : ptr_mode) 2231169689Skan 2232169689Skan/* Define as C expression which evaluates to nonzero if the tablejump 2233169689Skan instruction expects the table to contain offsets from the address of the 2234169689Skan table. 2235169689Skan Do not define this if the table should contain absolute addresses. */ 2236169689Skan#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16) 2237169689Skan 2238169689Skan/* Define this as 1 if `char' should by default be signed; else as 0. */ 2239169689Skan#ifndef DEFAULT_SIGNED_CHAR 2240169689Skan#define DEFAULT_SIGNED_CHAR 1 2241169689Skan#endif 2242169689Skan 2243169689Skan/* Max number of bytes we can move from memory to memory 2244169689Skan in one reasonably fast instruction. */ 2245169689Skan#define MOVE_MAX (TARGET_64BIT ? 8 : 4) 2246169689Skan#define MAX_MOVE_MAX 8 2247169689Skan 2248169689Skan/* Define this macro as a C expression which is nonzero if 2249169689Skan accessing less than a word of memory (i.e. a `char' or a 2250169689Skan `short') is no faster than accessing a word of memory, i.e., if 2251169689Skan such access require more than one instruction or if there is no 2252169689Skan difference in cost between byte and (aligned) word loads. 2253169689Skan 2254169689Skan On RISC machines, it tends to generate better code to define 2255169689Skan this as 1, since it avoids making a QI or HI mode register. */ 2256169689Skan#define SLOW_BYTE_ACCESS 1 2257169689Skan 2258169689Skan/* Define this to be nonzero if shift instructions ignore all but the low-order 2259169689Skan few bits. */ 2260169689Skan#define SHIFT_COUNT_TRUNCATED 1 2261169689Skan 2262169689Skan/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2263169689Skan is done just by pretending it is already truncated. */ 2264169689Skan#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ 2265169689Skan (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1) 2266169689Skan 2267169689Skan 2268169689Skan/* Specify the machine mode that pointers have. 2269169689Skan After generation of rtl, the compiler makes no further distinction 2270169689Skan between pointers and any other objects of this machine mode. */ 2271169689Skan 2272169689Skan#ifndef Pmode 2273169689Skan#define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) 2274169689Skan#endif 2275169689Skan 2276169689Skan/* Give call MEMs SImode since it is the "most permissive" mode 2277169689Skan for both 32-bit and 64-bit targets. */ 2278169689Skan 2279169689Skan#define FUNCTION_MODE SImode 2280169689Skan 2281169689Skan 2282169689Skan/* The cost of loading values from the constant pool. It should be 2283169689Skan larger than the cost of any constant we want to synthesize in-line. */ 2284169689Skan 2285169689Skan#define CONSTANT_POOL_COST COSTS_N_INSNS (8) 2286169689Skan 2287169689Skan/* A C expression for the cost of moving data from a register in 2288169689Skan class FROM to one in class TO. The classes are expressed using 2289169689Skan the enumeration values such as `GENERAL_REGS'. A value of 2 is 2290169689Skan the default; other values are interpreted relative to that. 2291169689Skan 2292169689Skan It is not required that the cost always equal 2 when FROM is the 2293169689Skan same as TO; on some machines it is expensive to move between 2294169689Skan registers if they are not general registers. 2295169689Skan 2296169689Skan If reload sees an insn consisting of a single `set' between two 2297169689Skan hard registers, and if `REGISTER_MOVE_COST' applied to their 2298169689Skan classes returns a value of 2, reload does not check to ensure 2299169689Skan that the constraints of the insn are met. Setting a cost of 2300169689Skan other than 2 will allow reload to verify that the constraints are 2301169689Skan met. You should do this if the `movM' pattern's constraints do 2302169689Skan not allow such copying. */ 2303169689Skan 2304169689Skan#define REGISTER_MOVE_COST(MODE, FROM, TO) \ 2305169689Skan mips_register_move_cost (MODE, FROM, TO) 2306169689Skan 2307169689Skan#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ 2308169689Skan (mips_cost->memory_latency \ 2309169689Skan + memory_move_secondary_cost ((MODE), (CLASS), (TO_P))) 2310169689Skan 2311169689Skan/* Define if copies to/from condition code registers should be avoided. 2312169689Skan 2313169689Skan This is needed for the MIPS because reload_outcc is not complete; 2314169689Skan it needs to handle cases where the source is a general or another 2315169689Skan condition code register. */ 2316169689Skan#define AVOID_CCMODE_COPIES 2317169689Skan 2318169689Skan/* A C expression for the cost of a branch instruction. A value of 2319169689Skan 1 is the default; other values are interpreted relative to that. */ 2320169689Skan 2321169689Skan#define BRANCH_COST mips_cost->branch_cost 2322169689Skan#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 2323169689Skan 2324169689Skan/* If defined, modifies the length assigned to instruction INSN as a 2325169689Skan function of the context in which it is used. LENGTH is an lvalue 2326169689Skan that contains the initially computed length of the insn and should 2327169689Skan be updated with the correct length of the insn. */ 2328169689Skan#define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2329169689Skan ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) 2330169689Skan 2331169689Skan/* Return the asm template for a non-MIPS16 conditional branch instruction. 2332169689Skan OPCODE is the opcode's mnemonic and OPERANDS is the asm template for 2333169689Skan its operands. */ 2334169689Skan#define MIPS_BRANCH(OPCODE, OPERANDS) \ 2335169689Skan "%*" OPCODE "%?\t" OPERANDS "%/" 2336169689Skan 2337169689Skan/* Return the asm template for a call. INSN is the instruction's mnemonic 2338169689Skan ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number 2339169689Skan of the target. 2340169689Skan 2341169689Skan When generating -mabicalls without explicit relocation operators, 2342169689Skan all calls should use assembly macros. Otherwise, all indirect 2343169689Skan calls should use "jr" or "jalr"; we will arrange to restore $gp 2344169689Skan afterwards if necessary. Finally, we can only generate direct 2345169689Skan calls for -mabicalls by temporarily switching to non-PIC mode. */ 2346169689Skan#define MIPS_CALL(INSN, OPERANDS, OPNO) \ 2347169689Skan (TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS \ 2348169689Skan ? "%*" INSN "\t%" #OPNO "%/" \ 2349169689Skan : REG_P (OPERANDS[OPNO]) \ 2350169689Skan ? "%*" INSN "r\t%" #OPNO "%/" \ 2351169689Skan : TARGET_ABICALLS \ 2352169689Skan ? (".option\tpic0\n\t" \ 2353169689Skan "%*" INSN "\t%" #OPNO "%/\n\t" \ 2354169689Skan ".option\tpic2") \ 2355169689Skan : "%*" INSN "\t%" #OPNO "%/") 2356169689Skan 2357169689Skan/* Control the assembler format that we output. */ 2358169689Skan 2359169689Skan/* Output to assembler file text saying following lines 2360169689Skan may contain character constants, extra white space, comments, etc. */ 2361169689Skan 2362169689Skan#ifndef ASM_APP_ON 2363169689Skan#define ASM_APP_ON " #APP\n" 2364169689Skan#endif 2365169689Skan 2366169689Skan/* Output to assembler file text saying following lines 2367169689Skan no longer contain unusual constructs. */ 2368169689Skan 2369169689Skan#ifndef ASM_APP_OFF 2370169689Skan#define ASM_APP_OFF " #NO_APP\n" 2371169689Skan#endif 2372169689Skan 2373169689Skan#define REGISTER_NAMES \ 2374169689Skan{ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ 2375169689Skan "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 2376169689Skan "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 2377169689Skan "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ 2378169689Skan "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ 2379169689Skan "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 2380169689Skan "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ 2381169689Skan "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ 2382169689Skan "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ 2383169689Skan "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \ 2384169689Skan "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ 2385169689Skan "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ 2386169689Skan "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ 2387169689Skan "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ 2388169689Skan "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ 2389169689Skan "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ 2390169689Skan "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ 2391169689Skan "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ 2392169689Skan "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ 2393169689Skan "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ 2394169689Skan "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ 2395169689Skan "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ 2396169689Skan "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ 2397169689Skan "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } 2398169689Skan 2399169689Skan/* List the "software" names for each register. Also list the numerical 2400169689Skan names for $fp and $sp. */ 2401169689Skan 2402169689Skan#define ADDITIONAL_REGISTER_NAMES \ 2403169689Skan{ \ 2404169689Skan { "$29", 29 + GP_REG_FIRST }, \ 2405169689Skan { "$30", 30 + GP_REG_FIRST }, \ 2406169689Skan { "at", 1 + GP_REG_FIRST }, \ 2407169689Skan { "v0", 2 + GP_REG_FIRST }, \ 2408169689Skan { "v1", 3 + GP_REG_FIRST }, \ 2409169689Skan { "a0", 4 + GP_REG_FIRST }, \ 2410169689Skan { "a1", 5 + GP_REG_FIRST }, \ 2411169689Skan { "a2", 6 + GP_REG_FIRST }, \ 2412169689Skan { "a3", 7 + GP_REG_FIRST }, \ 2413169689Skan { "t0", 8 + GP_REG_FIRST }, \ 2414169689Skan { "t1", 9 + GP_REG_FIRST }, \ 2415169689Skan { "t2", 10 + GP_REG_FIRST }, \ 2416169689Skan { "t3", 11 + GP_REG_FIRST }, \ 2417169689Skan { "t4", 12 + GP_REG_FIRST }, \ 2418169689Skan { "t5", 13 + GP_REG_FIRST }, \ 2419169689Skan { "t6", 14 + GP_REG_FIRST }, \ 2420169689Skan { "t7", 15 + GP_REG_FIRST }, \ 2421169689Skan { "s0", 16 + GP_REG_FIRST }, \ 2422169689Skan { "s1", 17 + GP_REG_FIRST }, \ 2423169689Skan { "s2", 18 + GP_REG_FIRST }, \ 2424169689Skan { "s3", 19 + GP_REG_FIRST }, \ 2425169689Skan { "s4", 20 + GP_REG_FIRST }, \ 2426169689Skan { "s5", 21 + GP_REG_FIRST }, \ 2427169689Skan { "s6", 22 + GP_REG_FIRST }, \ 2428169689Skan { "s7", 23 + GP_REG_FIRST }, \ 2429169689Skan { "t8", 24 + GP_REG_FIRST }, \ 2430169689Skan { "t9", 25 + GP_REG_FIRST }, \ 2431169689Skan { "k0", 26 + GP_REG_FIRST }, \ 2432169689Skan { "k1", 27 + GP_REG_FIRST }, \ 2433169689Skan { "gp", 28 + GP_REG_FIRST }, \ 2434169689Skan { "sp", 29 + GP_REG_FIRST }, \ 2435169689Skan { "fp", 30 + GP_REG_FIRST }, \ 2436169689Skan { "ra", 31 + GP_REG_FIRST }, \ 2437169689Skan ALL_COP_ADDITIONAL_REGISTER_NAMES \ 2438169689Skan} 2439169689Skan 2440169689Skan/* This is meant to be redefined in the host dependent files. It is a 2441169689Skan set of alternative names and regnums for mips coprocessors. */ 2442169689Skan 2443169689Skan#define ALL_COP_ADDITIONAL_REGISTER_NAMES 2444169689Skan 2445169689Skan/* A C compound statement to output to stdio stream STREAM the 2446169689Skan assembler syntax for an instruction operand X. X is an RTL 2447169689Skan expression. 2448169689Skan 2449169689Skan CODE is a value that can be used to specify one of several ways 2450169689Skan of printing the operand. It is used when identical operands 2451169689Skan must be printed differently depending on the context. CODE 2452169689Skan comes from the `%' specification that was used to request 2453169689Skan printing of the operand. If the specification was just `%DIGIT' 2454169689Skan then CODE is 0; if the specification was `%LTR DIGIT' then CODE 2455169689Skan is the ASCII code for LTR. 2456169689Skan 2457169689Skan If X is a register, this macro should print the register's name. 2458169689Skan The names can be found in an array `reg_names' whose type is 2459169689Skan `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. 2460169689Skan 2461169689Skan When the machine description has a specification `%PUNCT' (a `%' 2462169689Skan followed by a punctuation character), this macro is called with 2463169689Skan a null pointer for X and the punctuation character for CODE. 2464169689Skan 2465169689Skan See mips.c for the MIPS specific codes. */ 2466169689Skan 2467169689Skan#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2468169689Skan 2469169689Skan/* A C expression which evaluates to true if CODE is a valid 2470169689Skan punctuation character for use in the `PRINT_OPERAND' macro. If 2471169689Skan `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no 2472169689Skan punctuation characters (except for the standard one, `%') are 2473169689Skan used in this way. */ 2474169689Skan 2475169689Skan#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE] 2476169689Skan 2477169689Skan/* A C compound statement to output to stdio stream STREAM the 2478169689Skan assembler syntax for an instruction operand that is a memory 2479169689Skan reference whose address is ADDR. ADDR is an RTL expression. */ 2480169689Skan 2481169689Skan#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2482169689Skan 2483169689Skan 2484169689Skan/* A C statement, to be executed after all slot-filler instructions 2485169689Skan have been output. If necessary, call `dbr_sequence_length' to 2486169689Skan determine the number of slots filled in a sequence (zero if not 2487169689Skan currently outputting a sequence), to decide how many no-ops to 2488169689Skan output, or whatever. 2489169689Skan 2490169689Skan Don't define this macro if it has nothing to do, but it is 2491169689Skan helpful in reading assembly output if the extent of the delay 2492169689Skan sequence is made explicit (e.g. with white space). 2493169689Skan 2494169689Skan Note that output routines for instructions with delay slots must 2495169689Skan be prepared to deal with not being output as part of a sequence 2496169689Skan (i.e. when the scheduling pass is not run, or when no slot 2497169689Skan fillers could be found.) The variable `final_sequence' is null 2498169689Skan when not processing a sequence, otherwise it contains the 2499169689Skan `sequence' rtx being output. */ 2500169689Skan 2501169689Skan#define DBR_OUTPUT_SEQEND(STREAM) \ 2502169689Skando \ 2503169689Skan { \ 2504169689Skan if (set_nomacro > 0 && --set_nomacro == 0) \ 2505169689Skan fputs ("\t.set\tmacro\n", STREAM); \ 2506169689Skan \ 2507169689Skan if (set_noreorder > 0 && --set_noreorder == 0) \ 2508169689Skan fputs ("\t.set\treorder\n", STREAM); \ 2509169689Skan \ 2510169689Skan fputs ("\n", STREAM); \ 2511169689Skan } \ 2512169689Skanwhile (0) 2513169689Skan 2514169689Skan 2515169689Skan/* How to tell the debugger about changes of source files. */ 2516169689Skan#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ 2517169689Skan mips_output_filename (STREAM, NAME) 2518169689Skan 2519169689Skan/* mips-tfile does not understand .stabd directives. */ 2520169689Skan#define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \ 2521169689Skan dbxout_begin_stabn_sline (LINE); \ 2522169689Skan dbxout_stab_value_internal_label ("LM", &COUNTER); \ 2523169689Skan} while (0) 2524169689Skan 2525169689Skan/* Use .loc directives for SDB line numbers. */ 2526169689Skan#define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \ 2527169689Skan fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE) 2528169689Skan 2529169689Skan/* The MIPS implementation uses some labels for its own purpose. The 2530169689Skan following lists what labels are created, and are all formed by the 2531169689Skan pattern $L[a-z].*. The machine independent portion of GCC creates 2532169689Skan labels matching: $L[A-Z][0-9]+ and $L[0-9]+. 2533169689Skan 2534169689Skan LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. 2535169689Skan $Lb[0-9]+ Begin blocks for MIPS debug support 2536169689Skan $Lc[0-9]+ Label for use in s<xx> operation. 2537169689Skan $Le[0-9]+ End blocks for MIPS debug support */ 2538169689Skan 2539169689Skan#undef ASM_DECLARE_OBJECT_NAME 2540169689Skan#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ 2541169689Skan mips_declare_object (STREAM, NAME, "", ":\n", 0) 2542169689Skan 2543169689Skan/* Globalizing directive for a label. */ 2544169689Skan#define GLOBAL_ASM_OP "\t.globl\t" 2545169689Skan 2546169689Skan/* This says how to define a global common symbol. */ 2547169689Skan 2548169689Skan#define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common 2549169689Skan 2550169689Skan/* This says how to define a local common symbol (i.e., not visible to 2551169689Skan linker). */ 2552169689Skan 2553169689Skan#ifndef ASM_OUTPUT_ALIGNED_LOCAL 2554169689Skan#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ 2555169689Skan mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) 2556169689Skan#endif 2557169689Skan 2558169689Skan/* This says how to output an external. It would be possible not to 2559169689Skan output anything and let undefined symbol become external. However 2560169689Skan the assembler uses length information on externals to allocate in 2561169689Skan data/sdata bss/sbss, thereby saving exec time. */ 2562169689Skan 2563169689Skan#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ 2564169689Skan mips_output_external(STREAM,DECL,NAME) 2565169689Skan 2566169689Skan/* This is how to declare a function name. The actual work of 2567169689Skan emitting the label is moved to function_prologue, so that we can 2568169689Skan get the line number correctly emitted before the .ent directive, 2569169689Skan and after any .file directives. Define as empty so that the function 2570169689Skan is not declared before the .ent directive elsewhere. */ 2571169689Skan 2572169689Skan#undef ASM_DECLARE_FUNCTION_NAME 2573169689Skan#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) 2574169689Skan 2575169689Skan#ifndef FUNCTION_NAME_ALREADY_DECLARED 2576169689Skan#define FUNCTION_NAME_ALREADY_DECLARED 0 2577169689Skan#endif 2578169689Skan 2579169689Skan/* This is how to store into the string LABEL 2580169689Skan the symbol_ref name of an internal numbered label where 2581169689Skan PREFIX is the class of label and NUM is the number within the class. 2582169689Skan This is suitable for output with `assemble_name'. */ 2583169689Skan 2584169689Skan#undef ASM_GENERATE_INTERNAL_LABEL 2585169689Skan#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2586169689Skan sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 2587169689Skan 2588169689Skan/* This is how to output an element of a case-vector that is absolute. */ 2589169689Skan 2590169689Skan#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 2591169689Skan fprintf (STREAM, "\t%s\t%sL%d\n", \ 2592169689Skan ptr_mode == DImode ? ".dword" : ".word", \ 2593169689Skan LOCAL_LABEL_PREFIX, \ 2594169689Skan VALUE) 2595169689Skan 2596169689Skan/* This is how to output an element of a case-vector. We can make the 2597169689Skan entries PC-relative in MIPS16 code and GP-relative when .gp(d)word 2598169689Skan is supported. */ 2599169689Skan 2600169689Skan#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 2601169689Skando { \ 2602169689Skan if (TARGET_MIPS16) \ 2603169689Skan fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ 2604169689Skan LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 2605169689Skan else if (TARGET_GPWORD) \ 2606169689Skan fprintf (STREAM, "\t%s\t%sL%d\n", \ 2607169689Skan ptr_mode == DImode ? ".gpdword" : ".gpword", \ 2608169689Skan LOCAL_LABEL_PREFIX, VALUE); \ 2609169689Skan else \ 2610169689Skan fprintf (STREAM, "\t%s\t%sL%d\n", \ 2611169689Skan ptr_mode == DImode ? ".dword" : ".word", \ 2612169689Skan LOCAL_LABEL_PREFIX, VALUE); \ 2613169689Skan} while (0) 2614169689Skan 2615169689Skan/* When generating MIPS16 code, we want the jump table to be in the text 2616169689Skan section so that we can load its address using a PC-relative addition. */ 2617169689Skan#define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16 2618169689Skan 2619169689Skan/* This is how to output an assembler line 2620169689Skan that says to advance the location counter 2621169689Skan to a multiple of 2**LOG bytes. */ 2622169689Skan 2623169689Skan#define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 2624169689Skan fprintf (STREAM, "\t.align\t%d\n", (LOG)) 2625169689Skan 2626169689Skan/* This is how to output an assembler line to advance the location 2627169689Skan counter by SIZE bytes. */ 2628169689Skan 2629169689Skan#undef ASM_OUTPUT_SKIP 2630169689Skan#define ASM_OUTPUT_SKIP(STREAM,SIZE) \ 2631169689Skan fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 2632169689Skan 2633169689Skan/* This is how to output a string. */ 2634169689Skan#undef ASM_OUTPUT_ASCII 2635169689Skan#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \ 2636169689Skan mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t") 2637169689Skan 2638169689Skan/* Output #ident as a in the read-only data section. */ 2639169689Skan#undef ASM_OUTPUT_IDENT 2640169689Skan#define ASM_OUTPUT_IDENT(FILE, STRING) \ 2641169689Skan{ \ 2642169689Skan const char *p = STRING; \ 2643169689Skan int size = strlen (p) + 1; \ 2644169689Skan switch_to_section (readonly_data_section); \ 2645169689Skan assemble_string (p, size); \ 2646169689Skan} 2647169689Skan 2648169689Skan/* Default to -G 8 */ 2649169689Skan#ifndef MIPS_DEFAULT_GVALUE 2650169689Skan#define MIPS_DEFAULT_GVALUE 8 2651169689Skan#endif 2652169689Skan 2653169689Skan/* Define the strings to put out for each section in the object file. */ 2654169689Skan#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 2655169689Skan#define DATA_SECTION_ASM_OP "\t.data" /* large data */ 2656169689Skan 2657169689Skan#undef READONLY_DATA_SECTION_ASM_OP 2658169689Skan#define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ 2659169689Skan 2660169689Skan#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 2661169689Skando \ 2662169689Skan { \ 2663169689Skan fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \ 2664169689Skan TARGET_64BIT ? "dsubu" : "subu", \ 2665169689Skan reg_names[STACK_POINTER_REGNUM], \ 2666169689Skan reg_names[STACK_POINTER_REGNUM], \ 2667169689Skan TARGET_64BIT ? "sd" : "sw", \ 2668169689Skan reg_names[REGNO], \ 2669169689Skan reg_names[STACK_POINTER_REGNUM]); \ 2670169689Skan } \ 2671169689Skanwhile (0) 2672169689Skan 2673169689Skan#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 2674169689Skando \ 2675169689Skan { \ 2676169689Skan if (! set_noreorder) \ 2677169689Skan fprintf (STREAM, "\t.set\tnoreorder\n"); \ 2678169689Skan \ 2679169689Skan fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ 2680169689Skan TARGET_64BIT ? "ld" : "lw", \ 2681169689Skan reg_names[REGNO], \ 2682169689Skan reg_names[STACK_POINTER_REGNUM], \ 2683169689Skan TARGET_64BIT ? "daddu" : "addu", \ 2684169689Skan reg_names[STACK_POINTER_REGNUM], \ 2685169689Skan reg_names[STACK_POINTER_REGNUM]); \ 2686169689Skan \ 2687169689Skan if (! set_noreorder) \ 2688169689Skan fprintf (STREAM, "\t.set\treorder\n"); \ 2689169689Skan } \ 2690169689Skanwhile (0) 2691169689Skan 2692169689Skan/* How to start an assembler comment. 2693169689Skan The leading space is important (the mips native assembler requires it). */ 2694169689Skan#ifndef ASM_COMMENT_START 2695169689Skan#define ASM_COMMENT_START " #" 2696169689Skan#endif 2697169689Skan 2698169689Skan/* Default definitions for size_t and ptrdiff_t. We must override the 2699169689Skan definitions from ../svr4.h on mips-*-linux-gnu. */ 2700169689Skan 2701169689Skan#undef SIZE_TYPE 2702169689Skan#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 2703169689Skan 2704169689Skan#undef PTRDIFF_TYPE 2705169689Skan#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 2706169689Skan 2707169689Skan#ifndef __mips16 2708169689Skan/* Since the bits of the _init and _fini function is spread across 2709169689Skan many object files, each potentially with its own GP, we must assume 2710169689Skan we need to load our GP. We don't preserve $gp or $ra, since each 2711169689Skan init/fini chunk is supposed to initialize $gp, and crti/crtn 2712169689Skan already take care of preserving $ra and, when appropriate, $gp. */ 2713169689Skan#if (defined _ABIO32 && _MIPS_SIM == _ABIO32) 2714169689Skan#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2715169689Skan asm (SECTION_OP "\n\ 2716169689Skan .set noreorder\n\ 2717169689Skan bal 1f\n\ 2718169689Skan nop\n\ 2719169689Skan1: .cpload $31\n\ 2720169689Skan .set reorder\n\ 2721169689Skan jal " USER_LABEL_PREFIX #FUNC "\n\ 2722169689Skan " TEXT_SECTION_ASM_OP); 2723169689Skan#endif /* Switch to #elif when we're no longer limited by K&R C. */ 2724169689Skan#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 2725169689Skan || (defined _ABI64 && _MIPS_SIM == _ABI64) 2726169689Skan#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2727169689Skan asm (SECTION_OP "\n\ 2728169689Skan .set noreorder\n\ 2729169689Skan bal 1f\n\ 2730169689Skan nop\n\ 2731169689Skan1: .set reorder\n\ 2732169689Skan .cpsetup $31, $2, 1b\n\ 2733169689Skan jal " USER_LABEL_PREFIX #FUNC "\n\ 2734169689Skan " TEXT_SECTION_ASM_OP); 2735169689Skan#endif 2736169689Skan#endif 2737169689Skan 2738169689Skan#ifndef HAVE_AS_TLS 2739169689Skan#define HAVE_AS_TLS 0 2740169689Skan#endif 2741