1/* Definitions of target machine for GNU compiler. MIPS version. 2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4 Contributed by A. Lichnewsky (lich@inria.inria.fr). 5 Changed by Michael Meissner (meissner@osf.org). 6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and 7 Brendan Eich (brendan@microunity.com). 8 9This file is part of GCC. 10 11GCC is free software; you can redistribute it and/or modify 12it under the terms of the GNU General Public License as published by 13the Free Software Foundation; either version 2, or (at your option) 14any later version. 15 16GCC is distributed in the hope that it will be useful, 17but WITHOUT ANY WARRANTY; without even the implied warranty of 18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19GNU General Public License for more details. 20 21You should have received a copy of the GNU General Public License 22along with GCC; see the file COPYING. If not, write to 23the Free Software Foundation, 51 Franklin Street, Fifth Floor, 24Boston, MA 02110-1301, USA. */ 25 26 27/* MIPS external variables defined in mips.c. */ 28 29/* Which processor to schedule for. Since there is no difference between 30 a R2000 and R3000 in terms of the scheduler, we collapse them into 31 just an R3000. The elements of the enumeration must match exactly 32 the cpu attribute in the mips.md machine description. */ 33 34enum processor_type { 35 PROCESSOR_R3000, 36 PROCESSOR_4KC, 37 PROCESSOR_4KP, 38 PROCESSOR_5KC, 39 PROCESSOR_5KF, 40 PROCESSOR_20KC, 41 PROCESSOR_24K, 42 PROCESSOR_24KX, 43 PROCESSOR_M4K, 44 PROCESSOR_OCTEON, 45 PROCESSOR_R3900, 46 PROCESSOR_R6000, 47 PROCESSOR_R4000, 48 PROCESSOR_R4100, 49 PROCESSOR_R4111, 50 PROCESSOR_R4120, 51 PROCESSOR_R4130, 52 PROCESSOR_R4300, 53 PROCESSOR_R4600, 54 PROCESSOR_R4650, 55 PROCESSOR_R5000, 56 PROCESSOR_R5400, 57 PROCESSOR_R5500, 58 PROCESSOR_R7000, 59 PROCESSOR_R8000, 60 PROCESSOR_R9000, 61 PROCESSOR_SB1, 62 PROCESSOR_SB1A, 63 PROCESSOR_SR71000, 64 PROCESSOR_MAX 65}; 66 67/* Costs of various operations on the different architectures. */ 68 69struct mips_rtx_cost_data 70{ 71 unsigned short fp_add; 72 unsigned short fp_mult_sf; 73 unsigned short fp_mult_df; 74 unsigned short fp_div_sf; 75 unsigned short fp_div_df; 76 unsigned short int_mult_si; 77 unsigned short int_mult_di; 78 unsigned short int_div_si; 79 unsigned short int_div_di; 80 unsigned short branch_cost; 81 unsigned short memory_latency; 82}; 83 84/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), 85 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended 86 to work on a 64 bit machine. */ 87 88#define ABI_32 0 89#define ABI_N32 1 90#define ABI_64 2 91#define ABI_EABI 3 92#define ABI_O64 4 93 94/* Information about one recognized processor. Defined here for the 95 benefit of TARGET_CPU_CPP_BUILTINS. */ 96struct mips_cpu_info { 97 /* The 'canonical' name of the processor as far as GCC is concerned. 98 It's typically a manufacturer's prefix followed by a numerical 99 designation. It should be lower case. */ 100 const char *name; 101 102 /* The internal processor number that most closely matches this 103 entry. Several processors can have the same value, if there's no 104 difference between them from GCC's point of view. */ 105 enum processor_type cpu; 106 107 /* The ISA level that the processor implements. */ 108 int isa; 109}; 110 111#ifndef USED_FOR_TARGET 112extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */ 113extern const char *current_function_file; /* filename current function is in */ 114extern int num_source_filenames; /* current .file # */ 115extern int mips_section_threshold; /* # bytes of data/sdata cutoff */ 116extern int sym_lineno; /* sgi next label # for each stmt */ 117extern int set_noreorder; /* # of nested .set noreorder's */ 118extern int set_nomacro; /* # of nested .set nomacro's */ 119extern int set_noat; /* # of nested .set noat's */ 120extern int set_volatile; /* # of nested .set volatile's */ 121extern int mips_branch_likely; /* emit 'l' after br (branch likely) */ 122extern int mips_dbx_regno[]; /* Map register # to debug register # */ 123extern bool mips_split_p[]; 124extern GTY(()) rtx cmp_operands[2]; 125extern enum processor_type mips_arch; /* which cpu to codegen for */ 126extern enum processor_type mips_tune; /* which cpu to schedule for */ 127extern int mips_isa; /* architectural level */ 128extern int mips_abi; /* which ABI to use */ 129extern int mips16_hard_float; /* mips16 without -msoft-float */ 130extern const struct mips_cpu_info mips_cpu_info_table[]; 131extern const struct mips_cpu_info *mips_arch_info; 132extern const struct mips_cpu_info *mips_tune_info; 133extern const struct mips_rtx_cost_data *mips_cost; 134#endif 135 136/* Macros to silence warnings about numbers being signed in traditional 137 C and unsigned in ISO C when compiled on 32-bit hosts. */ 138 139#define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ 140#define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ 141#define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ 142 143 144/* Run-time compilation parameters selecting different hardware subsets. */ 145 146/* True if the call patterns should be split into a jalr followed by 147 an instruction to restore $gp. This is only ever true for SVR4 PIC, 148 in which $gp is call-clobbered. It is only safe to split the load 149 from the call when every use of $gp is explicit. */ 150 151#define TARGET_SPLIT_CALLS \ 152 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI) 153 154/* True if we're generating a form of -mabicalls in which we can use 155 operators like %hi and %lo to refer to locally-binding symbols. 156 We can only do this for -mno-shared, and only then if we can use 157 relocation operations instead of assembly macros. It isn't really 158 worth using absolute sequences for 64-bit symbols because GOT 159 accesses are so much shorter. */ 160 161#define TARGET_ABSOLUTE_ABICALLS \ 162 (TARGET_ABICALLS \ 163 && !TARGET_SHARED \ 164 && TARGET_EXPLICIT_RELOCS \ 165 && !ABI_HAS_64BIT_SYMBOLS) 166 167/* True if we can optimize sibling calls. For simplicity, we only 168 handle cases in which call_insn_operand will reject invalid 169 sibcall addresses. There are two cases in which this isn't true: 170 171 - TARGET_MIPS16. call_insn_operand accepts constant addresses 172 but there is no direct jump instruction. It isn't worth 173 using sibling calls in this case anyway; they would usually 174 be longer than normal calls. 175 176 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand 177 accepts global constants, but "jr $25" is the only allowed 178 sibcall. */ 179 180#define TARGET_SIBCALLS \ 181 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS)) 182 183/* True if .gpword or .gpdword should be used for switch tables. 184 185 Although GAS does understand .gpdword, the SGI linker mishandles 186 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64). 187 We therefore disable GP-relative switch tables for n64 on IRIX targets. */ 188#define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX)) 189 190/* Generate mips16 code */ 191#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) 192/* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */ 193#define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) 194 195/* Generic ISA defines. */ 196#define ISA_MIPS1 (mips_isa == 1) 197#define ISA_MIPS2 (mips_isa == 2) 198#define ISA_MIPS3 (mips_isa == 3) 199#define ISA_MIPS4 (mips_isa == 4) 200#define ISA_MIPS32 (mips_isa == 32) 201#define ISA_MIPS32R2 (mips_isa == 33) 202#define ISA_MIPS64 (mips_isa == 64) 203#define ISA_MIPS64R2 (mips_isa == 65) 204 205/* Architecture target defines. */ 206#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) 207#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) 208#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) 209#define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) 210#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) 211#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) 212#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) 213#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) 214#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ 215 || mips_arch == PROCESSOR_SB1A) 216#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) 217#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON) 218 219/* Scheduling target defines. */ 220#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) 221#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) 222#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) 223#define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) 224#define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) 225#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) 226#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) 227#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) 228#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) 229#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) 230#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) 231#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ 232 || mips_tune == PROCESSOR_SB1A) 233#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON) 234 235/* True if the pre-reload scheduler should try to create chains of 236 multiply-add or multiply-subtract instructions. For example, 237 suppose we have: 238 239 t1 = a * b 240 t2 = t1 + c * d 241 t3 = e * f 242 t4 = t3 - g * h 243 244 t1 will have a higher priority than t2 and t3 will have a higher 245 priority than t4. However, before reload, there is no dependence 246 between t1 and t3, and they can often have similar priorities. 247 The scheduler will then tend to prefer: 248 249 t1 = a * b 250 t3 = e * f 251 t2 = t1 + c * d 252 t4 = t3 - g * h 253 254 which stops us from making full use of macc/madd-style instructions. 255 This sort of situation occurs frequently in Fourier transforms and 256 in unrolled loops. 257 258 To counter this, the TUNE_MACC_CHAINS code will reorder the ready 259 queue so that chained multiply-add and multiply-subtract instructions 260 appear ahead of any other instruction that is likely to clobber lo. 261 In the example above, if t2 and t3 become ready at the same time, 262 the code ensures that t2 is scheduled first. 263 264 Multiply-accumulate instructions are a bigger win for some targets 265 than others, so this macro is defined on an opt-in basis. */ 266#define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ 267 || TUNE_MIPS4120 \ 268 || TUNE_MIPS4130) 269 270#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) 271#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) 272 273/* IRIX specific stuff. */ 274#define TARGET_IRIX 0 275#define TARGET_IRIX6 0 276 277/* Define preprocessor macros for the -march and -mtune options. 278 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected 279 processor. If INFO's canonical name is "foo", define PREFIX to 280 be "foo", and define an additional macro PREFIX_FOO. */ 281#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ 282 do \ 283 { \ 284 char *macro, *p; \ 285 \ 286 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ 287 for (p = macro; *p != 0; p++) \ 288 if (*p == '+') \ 289 *p = 'P'; \ 290 else \ 291 *p = TOUPPER (*p); \ 292 \ 293 builtin_define (macro); \ 294 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ 295 free (macro); \ 296 } \ 297 while (0) 298 299/* Target CPU builtins. */ 300#define TARGET_CPU_CPP_BUILTINS() \ 301 do \ 302 { \ 303 /* Everyone but IRIX defines this to mips. */ \ 304 if (!TARGET_IRIX) \ 305 builtin_assert ("machine=mips"); \ 306 \ 307 builtin_assert ("cpu=mips"); \ 308 builtin_define ("__mips__"); \ 309 builtin_define ("_mips"); \ 310 \ 311 /* We do this here because __mips is defined below \ 312 and so we can't use builtin_define_std. */ \ 313 if (!flag_iso) \ 314 builtin_define ("mips"); \ 315 \ 316 if (TARGET_64BIT) \ 317 builtin_define ("__mips64"); \ 318 \ 319 if (!TARGET_IRIX) \ 320 { \ 321 /* Treat _R3000 and _R4000 like register-size \ 322 defines, which is how they've historically \ 323 been used. */ \ 324 if (TARGET_64BIT) \ 325 { \ 326 builtin_define_std ("R4000"); \ 327 builtin_define ("_R4000"); \ 328 } \ 329 else \ 330 { \ 331 builtin_define_std ("R3000"); \ 332 builtin_define ("_R3000"); \ 333 } \ 334 } \ 335 if (TARGET_FLOAT64) \ 336 builtin_define ("__mips_fpr=64"); \ 337 else \ 338 builtin_define ("__mips_fpr=32"); \ 339 \ 340 if (TARGET_MIPS16) \ 341 builtin_define ("__mips16"); \ 342 \ 343 if (TARGET_MIPS3D) \ 344 builtin_define ("__mips3d"); \ 345 \ 346 if (TARGET_DSP) \ 347 builtin_define ("__mips_dsp"); \ 348 \ 349 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ 350 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ 351 \ 352 if (ISA_MIPS1) \ 353 { \ 354 builtin_define ("__mips=1"); \ 355 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ 356 } \ 357 else if (ISA_MIPS2) \ 358 { \ 359 builtin_define ("__mips=2"); \ 360 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ 361 } \ 362 else if (ISA_MIPS3) \ 363 { \ 364 builtin_define ("__mips=3"); \ 365 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ 366 } \ 367 else if (ISA_MIPS4) \ 368 { \ 369 builtin_define ("__mips=4"); \ 370 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ 371 } \ 372 else if (ISA_MIPS32) \ 373 { \ 374 builtin_define ("__mips=32"); \ 375 builtin_define ("__mips_isa_rev=1"); \ 376 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 377 } \ 378 else if (ISA_MIPS32R2) \ 379 { \ 380 builtin_define ("__mips=32"); \ 381 builtin_define ("__mips_isa_rev=2"); \ 382 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 383 } \ 384 else if (ISA_MIPS64) \ 385 { \ 386 builtin_define ("__mips=64"); \ 387 builtin_define ("__mips_isa_rev=1"); \ 388 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 389 } \ 390 else if (ISA_MIPS64R2) \ 391 { \ 392 builtin_define ("__mips=64"); \ 393 builtin_define ("__mips_isa_rev=2"); \ 394 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 395 } \ 396 \ 397 if (TARGET_HARD_FLOAT) \ 398 builtin_define ("__mips_hard_float"); \ 399 else if (TARGET_SOFT_FLOAT) \ 400 builtin_define ("__mips_soft_float"); \ 401 \ 402 if (TARGET_SINGLE_FLOAT) \ 403 builtin_define ("__mips_single_float"); \ 404 \ 405 if (TARGET_PAIRED_SINGLE_FLOAT) \ 406 builtin_define ("__mips_paired_single_float"); \ 407 \ 408 if (TARGET_BIG_ENDIAN) \ 409 { \ 410 builtin_define_std ("MIPSEB"); \ 411 builtin_define ("_MIPSEB"); \ 412 } \ 413 else \ 414 { \ 415 builtin_define_std ("MIPSEL"); \ 416 builtin_define ("_MIPSEL"); \ 417 } \ 418 \ 419 /* Macros dependent on the C dialect. */ \ 420 if (preprocessing_asm_p ()) \ 421 { \ 422 builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 423 builtin_define ("_LANGUAGE_ASSEMBLY"); \ 424 } \ 425 else if (c_dialect_cxx ()) \ 426 { \ 427 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ 428 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 429 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 430 } \ 431 else \ 432 { \ 433 builtin_define_std ("LANGUAGE_C"); \ 434 builtin_define ("_LANGUAGE_C"); \ 435 } \ 436 if (c_dialect_objc ()) \ 437 { \ 438 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ 439 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 440 /* Bizarre, but needed at least for Irix. */ \ 441 builtin_define_std ("LANGUAGE_C"); \ 442 builtin_define ("_LANGUAGE_C"); \ 443 } \ 444 \ 445 if (mips_abi == ABI_EABI) \ 446 builtin_define ("__mips_eabi"); \ 447 \ 448} while (0) 449 450/* Default target_flags if no switches are specified */ 451 452#ifndef TARGET_DEFAULT 453#define TARGET_DEFAULT 0 454#endif 455 456#ifndef TARGET_CPU_DEFAULT 457#define TARGET_CPU_DEFAULT 0 458#endif 459 460#ifndef TARGET_ENDIAN_DEFAULT 461#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN 462#endif 463 464#ifndef TARGET_FP_EXCEPTIONS_DEFAULT 465#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS 466#endif 467 468/* 'from-abi' makes a good default: you get whatever the ABI requires. */ 469#ifndef MIPS_ISA_DEFAULT 470#ifndef MIPS_CPU_STRING_DEFAULT 471#define MIPS_CPU_STRING_DEFAULT "from-abi" 472#endif 473#endif 474 475#ifdef IN_LIBGCC2 476#undef TARGET_64BIT 477/* Make this compile time constant for libgcc2 */ 478#ifdef __mips64 479#define TARGET_64BIT 1 480#else 481#define TARGET_64BIT 0 482#endif 483#endif /* IN_LIBGCC2 */ 484 485#define TARGET_LIBGCC_SDATA_SECTION ".sdata" 486 487#ifndef MULTILIB_ENDIAN_DEFAULT 488#if TARGET_ENDIAN_DEFAULT == 0 489#define MULTILIB_ENDIAN_DEFAULT "EL" 490#else 491#define MULTILIB_ENDIAN_DEFAULT "EB" 492#endif 493#endif 494 495#ifndef MULTILIB_ISA_DEFAULT 496# if MIPS_ISA_DEFAULT == 1 497# define MULTILIB_ISA_DEFAULT "mips1" 498# else 499# if MIPS_ISA_DEFAULT == 2 500# define MULTILIB_ISA_DEFAULT "mips2" 501# else 502# if MIPS_ISA_DEFAULT == 3 503# define MULTILIB_ISA_DEFAULT "mips3" 504# else 505# if MIPS_ISA_DEFAULT == 4 506# define MULTILIB_ISA_DEFAULT "mips4" 507# else 508# if MIPS_ISA_DEFAULT == 32 509# define MULTILIB_ISA_DEFAULT "mips32" 510# else 511# if MIPS_ISA_DEFAULT == 33 512# define MULTILIB_ISA_DEFAULT "mips32r2" 513# else 514# if MIPS_ISA_DEFAULT == 64 515# define MULTILIB_ISA_DEFAULT "mips64" 516# else 517# if MIPS_ISA_DEFAULT == 65 518# define MULTILIB_ISA_DEFAULT "mips64r2" 519# else 520# define MULTILIB_ISA_DEFAULT "mips1" 521# endif 522# endif 523# endif 524# endif 525# endif 526# endif 527# endif 528# endif 529#endif 530 531#ifndef MULTILIB_DEFAULTS 532#define MULTILIB_DEFAULTS \ 533 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } 534#endif 535 536/* We must pass -EL to the linker by default for little endian embedded 537 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the 538 linker will default to using big-endian output files. The OUTPUT_FORMAT 539 line must be in the linker script, otherwise -EB/-EL will not work. */ 540 541#ifndef ENDIAN_SPEC 542#if TARGET_ENDIAN_DEFAULT == 0 543#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" 544#else 545#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" 546#endif 547#endif 548 549/* Support for a compile-time default CPU, et cetera. The rules are: 550 --with-arch is ignored if -march is specified or a -mips is specified 551 (other than -mips16). 552 --with-tune is ignored if -mtune is specified. 553 --with-abi is ignored if -mabi is specified. 554 --with-float is ignored if -mhard-float or -msoft-float are 555 specified. 556 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are 557 specified. */ 558#define OPTION_DEFAULT_SPECS \ 559 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \ 560 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 561 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 562 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ 563 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" } 564 565 566#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ 567 && ISA_HAS_COND_TRAP) 568 569#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \ 570 && !TARGET_SR71K \ 571 && !TARGET_MIPS16) 572 573/* Generate three-operand multiply instructions for SImode. */ 574#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \ 575 || TARGET_MIPS5400 \ 576 || TARGET_MIPS5500 \ 577 || TARGET_MIPS7000 \ 578 || TARGET_MIPS9000 \ 579 || TARGET_MAD \ 580 || ISA_MIPS32 \ 581 || ISA_MIPS32R2 \ 582 || ISA_MIPS64 \ 583 || ISA_MIPS64R2) \ 584 && !TARGET_MIPS16) 585 586/* Generate three-operand multiply instructions for DImode. */ 587#define GENERATE_MULT3_DI ((TARGET_MIPS3900) \ 588 && !TARGET_MIPS16) 589 590/* True if the ABI can only work with 64-bit integer registers. We 591 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but 592 otherwise floating-point registers must also be 64-bit. */ 593#define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) 594 595/* Likewise for 32-bit regs. */ 596#define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) 597 598/* True if symbols are 64 bits wide. At present, n64 is the only 599 ABI for which this is true. */ 600#define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32) 601 602/* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */ 603#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ 604 || ISA_MIPS4 \ 605 || ISA_MIPS64 \ 606 || ISA_MIPS64R2) 607 608/* ISA has branch likely instructions (e.g. mips2). */ 609/* Disable branchlikely for tx39 until compare rewrite. They haven't 610 been generated up to this point. */ 611#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1) 612 613/* ISA has the conditional move instructions introduced in mips4. */ 614#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \ 615 || ISA_MIPS32 \ 616 || ISA_MIPS32R2 \ 617 || ISA_MIPS64 \ 618 || ISA_MIPS64R2) \ 619 && !TARGET_MIPS5500 \ 620 && !TARGET_MIPS16) 621 622/* ISA has the mips4 FP condition code instructions: FP-compare to CC, 623 branch on CC, and move (both FP and non-FP) on CC. */ 624#define ISA_HAS_8CC (ISA_MIPS4 \ 625 || ISA_MIPS32 \ 626 || ISA_MIPS32R2 \ 627 || ISA_MIPS64 \ 628 || ISA_MIPS64R2) 629 630/* This is a catch all for other mips4 instructions: indexed load, the 631 FP madd and msub instructions, and the FP recip and recip sqrt 632 instructions. */ 633#define ISA_HAS_FP4 ((ISA_MIPS4 \ 634 || ISA_MIPS64 \ 635 || ISA_MIPS64R2) \ 636 && !TARGET_MIPS16) 637 638/* ISA has conditional trap instructions. */ 639#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ 640 && !TARGET_MIPS16) 641 642/* ISA has integer multiply-accumulate instructions, madd and msub. */ 643#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ 644 || ISA_MIPS32R2 \ 645 || ISA_MIPS64 \ 646 || ISA_MIPS64R2 \ 647 ) && !TARGET_MIPS16) 648 649/* ISA has floating-point nmadd and nmsub instructions. */ 650#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \ 651 || ISA_MIPS64 \ 652 || ISA_MIPS64R2) \ 653 && (!TARGET_MIPS5400 || TARGET_MAD) \ 654 && ! TARGET_MIPS16) 655 656/* ISA has count leading zeroes/ones instruction (not implemented). */ 657#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ 658 || ISA_MIPS32R2 \ 659 || ISA_MIPS64 \ 660 || ISA_MIPS64R2 \ 661 ) && !TARGET_MIPS16) 662 663/* ISA has double-word count leading zeroes/ones instruction (not 664 implemented). */ 665#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \ 666 || ISA_MIPS64R2 \ 667 && !TARGET_MIPS16) 668 669/* ISA has three operand multiply instructions that put 670 the high part in an accumulator: mulhi or mulhiu. */ 671#define ISA_HAS_MULHI (TARGET_MIPS5400 \ 672 || TARGET_MIPS5500 \ 673 || TARGET_SR71K \ 674 ) 675 676/* ISA has three operand multiply instructions that 677 negates the result and puts the result in an accumulator. */ 678#define ISA_HAS_MULS (TARGET_MIPS5400 \ 679 || TARGET_MIPS5500 \ 680 || TARGET_SR71K \ 681 ) 682 683/* ISA has three operand multiply instructions that subtracts the 684 result from a 4th operand and puts the result in an accumulator. */ 685#define ISA_HAS_MSAC (TARGET_MIPS5400 \ 686 || TARGET_MIPS5500 \ 687 || TARGET_SR71K \ 688 ) 689/* ISA has three operand multiply instructions that the result 690 from a 4th operand and puts the result in an accumulator. */ 691#define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \ 692 || (TARGET_MIPS4130 && !TARGET_MIPS16) \ 693 || TARGET_MIPS5400 \ 694 || TARGET_MIPS5500 \ 695 || TARGET_SR71K \ 696 ) 697 698/* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ 699#define ISA_HAS_MACCHI (!TARGET_MIPS16 \ 700 && (TARGET_MIPS4120 \ 701 || TARGET_MIPS4130)) 702 703/* ISA has 32-bit rotate right instruction. */ 704#define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \ 705 && (ISA_MIPS32R2 \ 706 || ISA_MIPS64R2 \ 707 || TARGET_MIPS5400 \ 708 || TARGET_MIPS5500 \ 709 || TARGET_SR71K \ 710 )) 711 712/* ISA has 64-bit rotate right instruction. */ 713#define ISA_HAS_ROTR_DI (TARGET_64BIT \ 714 && !TARGET_MIPS16 \ 715 && (TARGET_MIPS5400 \ 716 || TARGET_MIPS5500 \ 717 || TARGET_SR71K \ 718 )) 719 720/* ISA has data prefetch instructions. This controls use of 'pref'. */ 721#define ISA_HAS_PREFETCH ((ISA_MIPS4 \ 722 || ISA_MIPS32 \ 723 || ISA_MIPS32R2 \ 724 || ISA_MIPS64 \ 725 || ISA_MIPS64R2) \ 726 && !TARGET_MIPS16) 727 728/* ISA has data indexed prefetch instructions. This controls use of 729 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. 730 (prefx is a cop1x instruction, so can only be used if FP is 731 enabled.) */ 732#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ 733 || ISA_MIPS64 \ 734 || ISA_MIPS64R2) \ 735 && !TARGET_MIPS16) 736 737/* True if trunc.w.s and trunc.w.d are real (not synthetic) 738 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d 739 also requires TARGET_DOUBLE_FLOAT. */ 740#define ISA_HAS_TRUNC_W (!ISA_MIPS1) 741 742/* ISA includes the MIPS32r2 seb and seh instructions. */ 743#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \ 744 && (ISA_MIPS32R2 \ 745 || ISA_MIPS64R2 \ 746 )) 747 748/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ 749#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \ 750 && (ISA_MIPS32R2 \ 751 || ISA_MIPS64R2 \ 752 )) 753 754/* True if the result of a load is not available to the next instruction. 755 A nop will then be needed between instructions like "lw $4,..." 756 and "addiu $4,$4,1". */ 757#define ISA_HAS_LOAD_DELAY (mips_isa == 1 \ 758 && !TARGET_MIPS3900 \ 759 && !TARGET_MIPS16) 760 761/* Likewise mtc1 and mfc1. */ 762#define ISA_HAS_XFER_DELAY (mips_isa <= 3) 763 764/* Likewise floating-point comparisons. */ 765#define ISA_HAS_FCMP_DELAY (mips_isa <= 3) 766 767/* True if mflo and mfhi can be immediately followed by instructions 768 which write to the HI and LO registers. 769 770 According to MIPS specifications, MIPS ISAs I, II, and III need 771 (at least) two instructions between the reads of HI/LO and 772 instructions which write them, and later ISAs do not. Contradicting 773 the MIPS specifications, some MIPS IV processor user manuals (e.g. 774 the UM for the NEC Vr5000) document needing the instructions between 775 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 776 MIPS64 and later ISAs to have the interlocks, plus any specific 777 earlier-ISA CPUs for which CPU documentation declares that the 778 instructions are really interlocked. */ 779#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ 780 || ISA_MIPS32R2 \ 781 || ISA_MIPS64 \ 782 || ISA_MIPS64R2 \ 783 || TARGET_MIPS5500) 784 785/* Add -G xx support. */ 786 787#undef SWITCH_TAKES_ARG 788#define SWITCH_TAKES_ARG(CHAR) \ 789 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') 790 791#define OVERRIDE_OPTIONS override_options () 792 793#define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage () 794 795/* Show we can debug even without a frame pointer. */ 796#define CAN_DEBUG_WITHOUT_FP 797 798/* Tell collect what flags to pass to nm. */ 799#ifndef NM_FLAGS 800#define NM_FLAGS "-Bn" 801#endif 802 803 804#ifndef MIPS_ABI_DEFAULT 805#define MIPS_ABI_DEFAULT ABI_32 806#endif 807 808/* Use the most portable ABI flag for the ASM specs. */ 809 810#if MIPS_ABI_DEFAULT == ABI_32 811#define MULTILIB_ABI_DEFAULT "mabi=32" 812#endif 813 814#if MIPS_ABI_DEFAULT == ABI_O64 815#define MULTILIB_ABI_DEFAULT "mabi=o64" 816#endif 817 818#if MIPS_ABI_DEFAULT == ABI_N32 819#define MULTILIB_ABI_DEFAULT "mabi=n32" 820#endif 821 822#if MIPS_ABI_DEFAULT == ABI_64 823#define MULTILIB_ABI_DEFAULT "mabi=64" 824#endif 825 826#if MIPS_ABI_DEFAULT == ABI_EABI 827#define MULTILIB_ABI_DEFAULT "mabi=eabi" 828#endif 829 830/* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options 831 to the assembler. It may be overridden by subtargets. */ 832#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC 833#define SUBTARGET_ASM_OPTIMIZING_SPEC "\ 834%{noasmopt:-O0} \ 835%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}" 836#endif 837 838/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to 839 the assembler. It may be overridden by subtargets. 840 841 Beginning with gas 2.13, -mdebug must be passed to correctly handle 842 COFF debugging info. */ 843 844#ifndef SUBTARGET_ASM_DEBUGGING_SPEC 845#define SUBTARGET_ASM_DEBUGGING_SPEC "\ 846%{g} %{g0} %{g1} %{g2} %{g3} \ 847%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ 848%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ 849%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ 850%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \ 851%{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}" 852#endif 853 854/* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be 855 overridden by subtargets. */ 856 857#ifndef SUBTARGET_ASM_SPEC 858#define SUBTARGET_ASM_SPEC "" 859#endif 860 861#undef ASM_SPEC 862#define ASM_SPEC "\ 863%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ 864%{mips32} %{mips32r2} %{mips64} \ 865%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ 866%{mips3d:-mips3d} \ 867%{mdsp} \ 868%{mfix-vr4120} %{mfix-vr4130} \ 869%(subtarget_asm_optimizing_spec) \ 870%(subtarget_asm_debugging_spec) \ 871%{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \ 872%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ 873%{mshared} %{mno-shared} \ 874%{msym32} %{mno-sym32} \ 875%{mtune=*} %{v} \ 876%(subtarget_asm_spec)" 877 878/* Extra switches sometimes passed to the linker. */ 879/* ??? The bestGnum will never be passed to the linker, because the gcc driver 880 will interpret it as a -b option. */ 881 882#ifndef LINK_SPEC 883#define LINK_SPEC "\ 884%(endian_spec) \ 885%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \ 886%{bestGnum} %{shared} %{non_shared}" 887#endif /* LINK_SPEC defined */ 888 889 890/* Specs for the compiler proper */ 891 892/* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be 893 overridden by subtargets. */ 894#ifndef SUBTARGET_CC1_SPEC 895#define SUBTARGET_CC1_SPEC "" 896#endif 897 898/* CC1_SPEC is the set of arguments to pass to the compiler proper. */ 899 900#undef CC1_SPEC 901#define CC1_SPEC "\ 902%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ 903%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ 904%{save-temps: } \ 905%(subtarget_cc1_spec)" 906 907/* Preprocessor specs. */ 908 909/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be 910 overridden by subtargets. */ 911#ifndef SUBTARGET_CPP_SPEC 912#define SUBTARGET_CPP_SPEC "" 913#endif 914 915#define CPP_SPEC "%(subtarget_cpp_spec)" 916 917/* This macro defines names of additional specifications to put in the specs 918 that can be used in various specifications like CC1_SPEC. Its definition 919 is an initializer with a subgrouping for each command option. 920 921 Each subgrouping contains a string constant, that defines the 922 specification name, and a string constant that used by the GCC driver 923 program. 924 925 Do not define this macro if it does not need to do anything. */ 926 927#define EXTRA_SPECS \ 928 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ 929 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 930 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \ 931 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ 932 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 933 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ 934 { "endian_spec", ENDIAN_SPEC }, \ 935 SUBTARGET_EXTRA_SPECS 936 937#ifndef SUBTARGET_EXTRA_SPECS 938#define SUBTARGET_EXTRA_SPECS 939#endif 940 941#define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ 942#define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */ 943#define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ 944 945#ifndef PREFERRED_DEBUGGING_TYPE 946#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 947#endif 948 949#define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4) 950 951/* By default, turn on GDB extensions. */ 952#define DEFAULT_GDB_EXTENSIONS 1 953 954/* Local compiler-generated symbols must have a prefix that the assembler 955 understands. By default, this is $, although some targets (e.g., 956 NetBSD-ELF) need to override this. */ 957 958#ifndef LOCAL_LABEL_PREFIX 959#define LOCAL_LABEL_PREFIX "$" 960#endif 961 962/* By default on the mips, external symbols do not have an underscore 963 prepended, but some targets (e.g., NetBSD) require this. */ 964 965#ifndef USER_LABEL_PREFIX 966#define USER_LABEL_PREFIX "" 967#endif 968 969/* On Sun 4, this limit is 2048. We use 1500 to be safe, 970 since the length can run past this up to a continuation point. */ 971#undef DBX_CONTIN_LENGTH 972#define DBX_CONTIN_LENGTH 1500 973 974/* How to renumber registers for dbx and gdb. */ 975#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ] 976 977/* The mapping from gcc register number to DWARF 2 CFA column number. */ 978#define DWARF_FRAME_REGNUM(REG) (REG) 979 980/* The DWARF 2 CFA column which tracks the return address. */ 981#define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31) 982 983/* The DWARF 2 CFA column which tracks the return address from a 984 signal handler context. */ 985#define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1) 986 987/* Before the prologue, RA lives in r31. */ 988#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31) 989 990/* Describe how we implement __builtin_eh_return. */ 991#define EH_RETURN_DATA_REGNO(N) \ 992 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 993 994#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) 995 996/* Offsets recorded in opcodes are a multiple of this alignment factor. 997 The default for this in 64-bit mode is 8, which causes problems with 998 SFmode register saves. */ 999#define DWARF_CIE_DATA_ALIGNMENT -4 1000 1001/* Correct the offset of automatic variables and arguments. Note that 1002 the MIPS debug format wants all automatic variables and arguments 1003 to be in terms of the virtual frame pointer (stack pointer before 1004 any adjustment in the function), while the MIPS 3.0 linker wants 1005 the frame pointer to be the stack pointer after the initial 1006 adjustment. */ 1007 1008#define DEBUGGER_AUTO_OFFSET(X) \ 1009 mips_debugger_offset (X, (HOST_WIDE_INT) 0) 1010#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ 1011 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) 1012 1013/* Target machine storage layout */ 1014 1015#define BITS_BIG_ENDIAN 0 1016#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 1017#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 1018 1019/* Define this to set the endianness to use in libgcc2.c, which can 1020 not depend on target_flags. */ 1021#if !defined(MIPSEL) && !defined(__MIPSEL__) 1022#define LIBGCC2_WORDS_BIG_ENDIAN 1 1023#else 1024#define LIBGCC2_WORDS_BIG_ENDIAN 0 1025#endif 1026 1027#define MAX_BITS_PER_WORD 64 1028 1029/* Width of a word, in units (bytes). */ 1030#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 1031#ifndef IN_LIBGCC2 1032#define MIN_UNITS_PER_WORD 4 1033#endif 1034 1035/* For MIPS, width of a floating point register. */ 1036#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) 1037 1038/* If register $f0 holds a floating-point value, $f(0 + FP_INC) is 1039 the next available register. */ 1040#define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) 1041 1042/* The largest size of value that can be held in floating-point 1043 registers and moved with a single instruction. */ 1044#define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG) 1045 1046/* The largest size of value that can be held in floating-point 1047 registers. */ 1048#define UNITS_PER_FPVALUE \ 1049 (TARGET_SOFT_FLOAT ? 0 \ 1050 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ 1051 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) 1052 1053/* The number of bytes in a double. */ 1054#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) 1055 1056#define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD) 1057 1058/* Set the sizes of the core types. */ 1059#define SHORT_TYPE_SIZE 16 1060#define INT_TYPE_SIZE 32 1061#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) 1062#define LONG_LONG_TYPE_SIZE 64 1063 1064#define FLOAT_TYPE_SIZE 32 1065#define DOUBLE_TYPE_SIZE 64 1066#define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) 1067 1068/* long double is not a fixed mode, but the idea is that, if we 1069 support long double, we also want a 128-bit integer type. */ 1070#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE 1071 1072#ifdef IN_LIBGCC2 1073#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 1074 || (defined _ABI64 && _MIPS_SIM == _ABI64) 1075# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 1076# else 1077# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 1078# endif 1079#endif 1080 1081/* Width in bits of a pointer. */ 1082#ifndef POINTER_SIZE 1083#define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) 1084#endif 1085 1086/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1087#define PARM_BOUNDARY BITS_PER_WORD 1088 1089/* Allocation boundary (in *bits*) for the code of a function. */ 1090#define FUNCTION_BOUNDARY 32 1091 1092/* Alignment of field after `int : 0' in a structure. */ 1093#define EMPTY_FIELD_BOUNDARY 32 1094 1095/* Every structure's size must be a multiple of this. */ 1096/* 8 is observed right on a DECstation and on riscos 4.02. */ 1097#define STRUCTURE_SIZE_BOUNDARY 8 1098 1099/* There is no point aligning anything to a rounder boundary than this. */ 1100#define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE 1101 1102/* All accesses must be aligned. */ 1103#define STRICT_ALIGNMENT 1 1104 1105/* Define this if you wish to imitate the way many other C compilers 1106 handle alignment of bitfields and the structures that contain 1107 them. 1108 1109 The behavior is that the type written for a bit-field (`int', 1110 `short', or other integer type) imposes an alignment for the 1111 entire structure, as if the structure really did contain an 1112 ordinary field of that type. In addition, the bit-field is placed 1113 within the structure so that it would fit within such a field, 1114 not crossing a boundary for it. 1115 1116 Thus, on most machines, a bit-field whose type is written as `int' 1117 would not cross a four-byte boundary, and would force four-byte 1118 alignment for the whole structure. (The alignment used may not 1119 be four bytes; it is controlled by the other alignment 1120 parameters.) 1121 1122 If the macro is defined, its definition should be a C expression; 1123 a nonzero value for the expression enables this behavior. */ 1124 1125#define PCC_BITFIELD_TYPE_MATTERS 1 1126 1127/* If defined, a C expression to compute the alignment given to a 1128 constant that is being placed in memory. CONSTANT is the constant 1129 and ALIGN is the alignment that the object would ordinarily have. 1130 The value of this macro is used instead of that alignment to align 1131 the object. 1132 1133 If this macro is not defined, then ALIGN is used. 1134 1135 The typical use of this macro is to increase alignment for string 1136 constants to be word aligned so that `strcpy' calls that copy 1137 constants can be done inline. */ 1138 1139#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 1140 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 1141 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 1142 1143/* If defined, a C expression to compute the alignment for a static 1144 variable. TYPE is the data type, and ALIGN is the alignment that 1145 the object would ordinarily have. The value of this macro is used 1146 instead of that alignment to align the object. 1147 1148 If this macro is not defined, then ALIGN is used. 1149 1150 One use of this macro is to increase alignment of medium-size 1151 data to make it all fit in fewer cache lines. Another is to 1152 cause character arrays to be word-aligned so that `strcpy' calls 1153 that copy constants to character arrays can be done inline. */ 1154 1155#undef DATA_ALIGNMENT 1156#define DATA_ALIGNMENT(TYPE, ALIGN) \ 1157 ((((ALIGN) < BITS_PER_WORD) \ 1158 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 1159 || TREE_CODE (TYPE) == UNION_TYPE \ 1160 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 1161 1162 1163#define PAD_VARARGS_DOWN \ 1164 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1165 1166/* Define if operations between registers always perform the operation 1167 on the full register even if a narrower mode is specified. */ 1168#define WORD_REGISTER_OPERATIONS 1169 1170/* When in 64 bit mode, move insns will sign extend SImode and CCmode 1171 moves. All other references are zero extended. */ 1172#define LOAD_EXTEND_OP(MODE) \ 1173 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ 1174 ? SIGN_EXTEND : ZERO_EXTEND) 1175 1176/* Define this macro if it is advisable to hold scalars in registers 1177 in a wider mode than that declared by the program. In such cases, 1178 the value is constrained to be within the bounds of the declared 1179 type, but kept valid in the wider mode. The signedness of the 1180 extension may differ from that of the type. */ 1181 1182#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1183 if (GET_MODE_CLASS (MODE) == MODE_INT \ 1184 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 1185 { \ 1186 if ((MODE) == SImode) \ 1187 (UNSIGNEDP) = 0; \ 1188 (MODE) = Pmode; \ 1189 } 1190 1191/* Define if loading short immediate values into registers sign extends. */ 1192#define SHORT_IMMEDIATES_SIGN_EXTEND 1193 1194/* The [d]clz instructions have the natural values at 0. */ 1195 1196#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1197 ((VALUE) = GET_MODE_BITSIZE (MODE), true) 1198 1199/* Standard register usage. */ 1200 1201/* Number of hardware registers. We have: 1202 1203 - 32 integer registers 1204 - 32 floating point registers 1205 - 8 condition code registers 1206 - 2 accumulator registers (hi and lo) 1207 - 32 registers each for coprocessors 0, 2 and 3 1208 - 3 fake registers: 1209 - ARG_POINTER_REGNUM 1210 - FRAME_POINTER_REGNUM 1211 - FAKE_CALL_REGNO (see the comment above load_callsi for details) 1212 - 3 dummy entries that were used at various times in the past. 1213 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE 1214 - 6 DSP control registers */ 1215 1216#define FIRST_PSEUDO_REGISTER 188 1217 1218/* By default, fix the kernel registers ($26 and $27), the global 1219 pointer ($28) and the stack pointer ($29). This can change 1220 depending on the command-line options. 1221 1222 Regarding coprocessor registers: without evidence to the contrary, 1223 it's best to assume that each coprocessor register has a unique 1224 use. This can be overridden, in, e.g., override_options() or 1225 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate 1226 for a particular target. */ 1227 1228#define FIXED_REGISTERS \ 1229{ \ 1230 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ 1232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1234 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ 1235 /* COP0 registers */ \ 1236 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1237 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1238 /* COP2 registers */ \ 1239 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1240 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1241 /* COP3 registers */ \ 1242 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1243 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1244 /* 6 DSP accumulator registers & 6 control registers */ \ 1245 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ 1246} 1247 1248 1249/* Set up this array for o32 by default. 1250 1251 Note that we don't mark $31 as a call-clobbered register. The idea is 1252 that it's really the call instructions themselves which clobber $31. 1253 We don't care what the called function does with it afterwards. 1254 1255 This approach makes it easier to implement sibcalls. Unlike normal 1256 calls, sibcalls don't clobber $31, so the register reaches the 1257 called function in tact. EPILOGUE_USES says that $31 is useful 1258 to the called function. */ 1259 1260#define CALL_USED_REGISTERS \ 1261{ \ 1262 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1263 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ 1264 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1265 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1266 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1267 /* COP0 registers */ \ 1268 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1269 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1270 /* COP2 registers */ \ 1271 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1272 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1273 /* COP3 registers */ \ 1274 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1275 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1276 /* 6 DSP accumulator registers & 6 control registers */ \ 1277 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 1278} 1279 1280 1281/* Define this since $28, though fixed, is call-saved in many ABIs. */ 1282 1283#define CALL_REALLY_USED_REGISTERS \ 1284{ /* General registers. */ \ 1285 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1286 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ 1287 /* Floating-point registers. */ \ 1288 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1289 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1290 /* Others. */ \ 1291 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1292 /* COP0 registers */ \ 1293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1294 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1295 /* COP2 registers */ \ 1296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1298 /* COP3 registers */ \ 1299 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1300 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1301 /* 6 DSP accumulator registers & 6 control registers */ \ 1302 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ 1303} 1304 1305/* Internal macros to classify a register number as to whether it's a 1306 general purpose register, a floating point register, a 1307 multiply/divide register, or a status register. */ 1308 1309#define GP_REG_FIRST 0 1310#define GP_REG_LAST 31 1311#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 1312#define GP_DBX_FIRST 0 1313 1314#define FP_REG_FIRST 32 1315#define FP_REG_LAST 63 1316#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 1317#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) 1318 1319#define MD_REG_FIRST 64 1320#define MD_REG_LAST 65 1321#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) 1322#define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) 1323 1324#define ST_REG_FIRST 67 1325#define ST_REG_LAST 74 1326#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) 1327 1328 1329/* FIXME: renumber. */ 1330#define COP0_REG_FIRST 80 1331#define COP0_REG_LAST 111 1332#define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) 1333 1334#define COP2_REG_FIRST 112 1335#define COP2_REG_LAST 143 1336#define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) 1337 1338#define COP3_REG_FIRST 144 1339#define COP3_REG_LAST 175 1340#define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) 1341/* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */ 1342#define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1) 1343 1344#define DSP_ACC_REG_FIRST 176 1345#define DSP_ACC_REG_LAST 181 1346#define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) 1347 1348#define AT_REGNUM (GP_REG_FIRST + 1) 1349#define HI_REGNUM (MD_REG_FIRST + 0) 1350#define LO_REGNUM (MD_REG_FIRST + 1) 1351#define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0) 1352#define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1) 1353#define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2) 1354#define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3) 1355#define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4) 1356#define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5) 1357 1358/* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. 1359 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG 1360 should be used instead. */ 1361#define FPSW_REGNUM ST_REG_FIRST 1362 1363#define GP_REG_P(REGNO) \ 1364 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 1365#define M16_REG_P(REGNO) \ 1366 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) 1367#define FP_REG_P(REGNO) \ 1368 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 1369#define MD_REG_P(REGNO) \ 1370 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) 1371#define ST_REG_P(REGNO) \ 1372 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) 1373#define COP0_REG_P(REGNO) \ 1374 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) 1375#define COP2_REG_P(REGNO) \ 1376 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) 1377#define COP3_REG_P(REGNO) \ 1378 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) 1379#define ALL_COP_REG_P(REGNO) \ 1380 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) 1381/* Test if REGNO is one of the 6 new DSP accumulators. */ 1382#define DSP_ACC_REG_P(REGNO) \ 1383 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) 1384/* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ 1385#define ACC_REG_P(REGNO) \ 1386 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) 1387/* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */ 1388#define ACC_HI_REG_P(REGNO) \ 1389 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \ 1390 || (REGNO) == AC3HI_REGNUM) 1391 1392#define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 1393 1394/* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used 1395 to initialize the mips16 gp pseudo register. */ 1396#define CONST_GP_P(X) \ 1397 (GET_CODE (X) == CONST \ 1398 && GET_CODE (XEXP (X, 0)) == UNSPEC \ 1399 && XINT (XEXP (X, 0), 1) == UNSPEC_GP) 1400 1401/* Return coprocessor number from register number. */ 1402 1403#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ 1404 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ 1405 : COP3_REG_P (REGNO) ? '3' : '?') 1406 1407 1408#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE) 1409 1410/* To make the code simpler, HARD_REGNO_MODE_OK just references an 1411 array built in override_options. Because machmodes.h is not yet 1412 included before this file is processed, the MODE bound can't be 1413 expressed here. */ 1414 1415extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; 1416 1417#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1418 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ] 1419 1420/* Value is 1 if it is a good idea to tie two pseudo registers 1421 when one has mode MODE1 and one has mode MODE2. 1422 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1423 for any hard reg, then this must be 0 for correct output. */ 1424#define MODES_TIEABLE_P(MODE1, MODE2) \ 1425 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ 1426 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 1427 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ 1428 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 1429 1430/* Register to use for pushing function arguments. */ 1431#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) 1432 1433/* These two registers don't really exist: they get eliminated to either 1434 the stack or hard frame pointer. */ 1435#define ARG_POINTER_REGNUM 77 1436#define FRAME_POINTER_REGNUM 78 1437 1438/* $30 is not available on the mips16, so we use $17 as the frame 1439 pointer. */ 1440#define HARD_FRAME_POINTER_REGNUM \ 1441 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) 1442 1443/* Value should be nonzero if functions must have frame pointers. 1444 Zero means the frame pointer need not be set up (and parms 1445 may be accessed via the stack pointer) in functions that seem suitable. 1446 This is computed in `reload', in reload1.c. */ 1447#define FRAME_POINTER_REQUIRED (current_function_calls_alloca) 1448 1449/* Register in which static-chain is passed to a function. */ 1450#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2) 1451 1452/* Registers used as temporaries in prologue/epilogue code. If we're 1453 generating mips16 code, these registers must come from the core set 1454 of 8. The prologue register mustn't conflict with any incoming 1455 arguments, the static chain pointer, or the frame pointer. The 1456 epilogue temporary mustn't conflict with the return registers, the 1457 frame pointer, the EH stack adjustment, or the EH data registers. */ 1458 1459#define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3) 1460#define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) 1461 1462#define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) 1463#define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) 1464 1465/* Define this macro if it is as good or better to call a constant 1466 function address than to call an address kept in a register. */ 1467#define NO_FUNCTION_CSE 1 1468 1469/* The ABI-defined global pointer. Sometimes we use a different 1470 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ 1471#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) 1472 1473/* We normally use $28 as the global pointer. However, when generating 1474 n32/64 PIC, it is better for leaf functions to use a call-clobbered 1475 register instead. They can then avoid saving and restoring $28 1476 and perhaps avoid using a frame at all. 1477 1478 When a leaf function uses something other than $28, mips_expand_prologue 1479 will modify pic_offset_table_rtx in place. Take the register number 1480 from there after reload. */ 1481#define PIC_OFFSET_TABLE_REGNUM \ 1482 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) 1483 1484#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25) 1485 1486/* Define the classes of registers for register constraints in the 1487 machine description. Also define ranges of constants. 1488 1489 One of the classes must always be named ALL_REGS and include all hard regs. 1490 If there is more than one class, another class must be named NO_REGS 1491 and contain no registers. 1492 1493 The name GENERAL_REGS must be the name of a class (or an alias for 1494 another name such as ALL_REGS). This is the class of registers 1495 that is allowed by "g" or "r" in a register constraint. 1496 Also, registers outside this class are allocated only when 1497 instructions express preferences for them. 1498 1499 The classes must be numbered in nondecreasing order; that is, 1500 a larger-numbered class must never be contained completely 1501 in a smaller-numbered class. 1502 1503 For any two classes, it is very desirable that there be another 1504 class that represents their union. */ 1505 1506enum reg_class 1507{ 1508 NO_REGS, /* no registers in set */ 1509 M16_NA_REGS, /* mips16 regs not used to pass args */ 1510 M16_REGS, /* mips16 directly accessible registers */ 1511 T_REG, /* mips16 T register ($24) */ 1512 M16_T_REGS, /* mips16 registers plus T register */ 1513 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ 1514 V1_REG, /* Register $v1 ($3) used for TLS access. */ 1515 LEA_REGS, /* Every GPR except $25 */ 1516 GR_REGS, /* integer registers */ 1517 FP_REGS, /* floating point registers */ 1518 HI_REG, /* hi register */ 1519 LO_REG, /* lo register */ 1520 MD_REGS, /* multiply/divide registers (hi/lo) */ 1521 COP0_REGS, /* generic coprocessor classes */ 1522 COP2_REGS, 1523 COP3_REGS, 1524 HI_AND_GR_REGS, /* union classes */ 1525 LO_AND_GR_REGS, 1526 HI_AND_FP_REGS, 1527 COP0_AND_GR_REGS, 1528 COP2_AND_GR_REGS, 1529 COP3_AND_GR_REGS, 1530 ALL_COP_REGS, 1531 ALL_COP_AND_GR_REGS, 1532 ST_REGS, /* status registers (fp status) */ 1533 DSP_ACC_REGS, /* DSP accumulator registers */ 1534 ACC_REGS, /* Hi/Lo and DSP accumulator registers */ 1535 ALL_REGS, /* all registers */ 1536 LIM_REG_CLASSES /* max value + 1 */ 1537}; 1538 1539#define N_REG_CLASSES (int) LIM_REG_CLASSES 1540 1541#define GENERAL_REGS GR_REGS 1542 1543/* An initializer containing the names of the register classes as C 1544 string constants. These names are used in writing some of the 1545 debugging dumps. */ 1546 1547#define REG_CLASS_NAMES \ 1548{ \ 1549 "NO_REGS", \ 1550 "M16_NA_REGS", \ 1551 "M16_REGS", \ 1552 "T_REG", \ 1553 "M16_T_REGS", \ 1554 "PIC_FN_ADDR_REG", \ 1555 "V1_REG", \ 1556 "LEA_REGS", \ 1557 "GR_REGS", \ 1558 "FP_REGS", \ 1559 "HI_REG", \ 1560 "LO_REG", \ 1561 "MD_REGS", \ 1562 /* coprocessor registers */ \ 1563 "COP0_REGS", \ 1564 "COP2_REGS", \ 1565 "COP3_REGS", \ 1566 "HI_AND_GR_REGS", \ 1567 "LO_AND_GR_REGS", \ 1568 "HI_AND_FP_REGS", \ 1569 "COP0_AND_GR_REGS", \ 1570 "COP2_AND_GR_REGS", \ 1571 "COP3_AND_GR_REGS", \ 1572 "ALL_COP_REGS", \ 1573 "ALL_COP_AND_GR_REGS", \ 1574 "ST_REGS", \ 1575 "DSP_ACC_REGS", \ 1576 "ACC_REGS", \ 1577 "ALL_REGS" \ 1578} 1579 1580/* An initializer containing the contents of the register classes, 1581 as integers which are bit masks. The Nth integer specifies the 1582 contents of class N. The way the integer MASK is interpreted is 1583 that register R is in the class if `MASK & (1 << R)' is 1. 1584 1585 When the machine has more than 32 registers, an integer does not 1586 suffice. Then the integers are replaced by sub-initializers, 1587 braced groupings containing several integers. Each 1588 sub-initializer must be suitable as an initializer for the type 1589 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 1590 1591#define REG_CLASS_CONTENTS \ 1592{ \ 1593 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \ 1594 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\ 1595 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \ 1596 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \ 1597 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \ 1598 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \ 1599 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \ 1600 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \ 1601 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \ 1602 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \ 1603 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \ 1604 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \ 1605 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \ 1606 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \ 1607 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \ 1608 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \ 1609 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \ 1610 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \ 1611 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \ 1612 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \ 1613 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \ 1614 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \ 1615 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ 1616 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ 1617 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \ 1618 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \ 1619 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \ 1620 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \ 1621} 1622 1623 1624/* A C expression whose value is a register class containing hard 1625 register REGNO. In general there is more that one such class; 1626 choose a class which is "minimal", meaning that no smaller class 1627 also contains the register. */ 1628 1629extern const enum reg_class mips_regno_to_class[]; 1630 1631#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] 1632 1633/* A macro whose definition is the name of the class to which a 1634 valid base register must belong. A base register is one used in 1635 an address which is the register value plus a displacement. */ 1636 1637#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS) 1638 1639/* A macro whose definition is the name of the class to which a 1640 valid index register must belong. An index register is one used 1641 in an address where its value is either multiplied by a scale 1642 factor or added to another register (as well as added to a 1643 displacement). */ 1644 1645#define INDEX_REG_CLASS NO_REGS 1646 1647/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1648 registers explicitly used in the rtl to be used as spill registers 1649 but prevents the compiler from extending the lifetime of these 1650 registers. */ 1651 1652#define SMALL_REGISTER_CLASSES (TARGET_MIPS16) 1653 1654/* This macro is used later on in the file. */ 1655#define GR_REG_CLASS_P(CLASS) \ 1656 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \ 1657 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \ 1658 || (CLASS) == V1_REG \ 1659 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS) 1660 1661/* This macro is also used later on in the file. */ 1662#define COP_REG_CLASS_P(CLASS) \ 1663 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS) 1664 1665/* REG_ALLOC_ORDER is to order in which to allocate registers. This 1666 is the default value (allocate the registers in numeric order). We 1667 define it just so that we can override it for the mips16 target in 1668 ORDER_REGS_FOR_LOCAL_ALLOC. */ 1669 1670#define REG_ALLOC_ORDER \ 1671{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 1672 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 1673 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1674 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 1675 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 1676 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 1677 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ 1678 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ 1679 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ 1680 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ 1681 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ 1682 176,177,178,179,180,181,182,183,184,185,186,187 \ 1683} 1684 1685/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 1686 to be rearranged based on a particular function. On the mips16, we 1687 want to allocate $24 (T_REG) before other registers for 1688 instructions for which it is possible. */ 1689 1690#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () 1691 1692/* True if VALUE is an unsigned 6-bit number. */ 1693 1694#define UIMM6_OPERAND(VALUE) \ 1695 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) 1696 1697/* True if VALUE is a signed 10-bit number. */ 1698 1699#define IMM10_OPERAND(VALUE) \ 1700 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) 1701 1702/* True if VALUE is a signed 16-bit number. */ 1703 1704#define SMALL_OPERAND(VALUE) \ 1705 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) 1706 1707/* True if VALUE is an unsigned 16-bit number. */ 1708 1709#define SMALL_OPERAND_UNSIGNED(VALUE) \ 1710 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) 1711 1712/* True if VALUE can be loaded into a register using LUI. */ 1713 1714#define LUI_OPERAND(VALUE) \ 1715 (((VALUE) | 0x7fff0000) == 0x7fff0000 \ 1716 || ((VALUE) | 0x7fff0000) + 0x10000 == 0) 1717 1718/* Return a value X with the low 16 bits clear, and such that 1719 VALUE - X is a signed 16-bit value. */ 1720 1721#define CONST_HIGH_PART(VALUE) \ 1722 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) 1723 1724#define CONST_LOW_PART(VALUE) \ 1725 ((VALUE) - CONST_HIGH_PART (VALUE)) 1726 1727#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) 1728#define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) 1729#define LUI_INT(X) LUI_OPERAND (INTVAL (X)) 1730 1731#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1732 mips_preferred_reload_class (X, CLASS) 1733 1734/* Certain machines have the property that some registers cannot be 1735 copied to some other registers without using memory. Define this 1736 macro on those machines to be a C expression that is nonzero if 1737 objects of mode MODE in registers of CLASS1 can only be copied to 1738 registers of class CLASS2 by storing a register of CLASS1 into 1739 memory and loading that memory location into a register of CLASS2. 1740 1741 Do not define this macro if its value would always be zero. */ 1742#if 0 1743#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1744 ((!TARGET_DEBUG_H_MODE \ 1745 && GET_MODE_CLASS (MODE) == MODE_INT \ 1746 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \ 1747 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \ 1748 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \ 1749 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \ 1750 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS)))) 1751#endif 1752/* The HI and LO registers can only be reloaded via the general 1753 registers. Condition code registers can only be loaded to the 1754 general registers, and from the floating point registers. */ 1755 1756#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1757 mips_secondary_reload_class (CLASS, MODE, X, 1) 1758#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1759 mips_secondary_reload_class (CLASS, MODE, X, 0) 1760 1761/* Return the maximum number of consecutive registers 1762 needed to represent mode MODE in a register of class CLASS. */ 1763 1764#define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) 1765 1766#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1767 mips_cannot_change_mode_class (FROM, TO, CLASS) 1768 1769/* Stack layout; function entry, exit and calling. */ 1770 1771#define STACK_GROWS_DOWNWARD 1772 1773/* The offset of the first local variable from the beginning of the frame. 1774 See compute_frame_size for details about the frame layout. 1775 1776 ??? If flag_profile_values is true, and we are generating 32-bit code, then 1777 we assume that we will need 16 bytes of argument space. This is because 1778 the value profiling code may emit calls to cmpdi2 in leaf functions. 1779 Without this hack, the local variables will start at sp+8 and the gp save 1780 area will be at sp+16, and thus they will overlap. compute_frame_size is 1781 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which 1782 will end up as 24 instead of 8. This won't be needed if profiling code is 1783 inserted before virtual register instantiation. */ 1784 1785#define STARTING_FRAME_OFFSET \ 1786 ((flag_profile_values && ! TARGET_64BIT \ 1787 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \ 1788 : current_function_outgoing_args_size) \ 1789 + (TARGET_ABICALLS && !TARGET_NEWABI \ 1790 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)) 1791 1792#define RETURN_ADDR_RTX mips_return_addr 1793 1794/* Since the mips16 ISA mode is encoded in the least-significant bit 1795 of the address, mask it off return addresses for purposes of 1796 finding exception handling regions. */ 1797 1798#define MASK_RETURN_ADDR GEN_INT (-2) 1799 1800 1801/* Similarly, don't use the least-significant bit to tell pointers to 1802 code from vtable index. */ 1803 1804#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 1805 1806/* The eliminations to $17 are only used for mips16 code. See the 1807 definition of HARD_FRAME_POINTER_REGNUM. */ 1808 1809#define ELIMINABLE_REGS \ 1810{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1811 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 1812 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ 1813 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1814 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 1815 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} 1816 1817/* We can always eliminate to the hard frame pointer. We can eliminate 1818 to the stack pointer unless a frame pointer is needed. 1819 1820 In mips16 mode, we need a frame pointer for a large frame; otherwise, 1821 reload may be unable to compute the address of a local variable, 1822 since there is no way to add a large constant to the stack pointer 1823 without using a temporary register. */ 1824#define CAN_ELIMINATE(FROM, TO) \ 1825 ((TO) == HARD_FRAME_POINTER_REGNUM \ 1826 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \ 1827 && (!TARGET_MIPS16 \ 1828 || compute_frame_size (get_frame_size ()) < 32768))) 1829 1830#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1831 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) 1832 1833/* Allocate stack space for arguments at the beginning of each function. */ 1834#define ACCUMULATE_OUTGOING_ARGS 1 1835 1836/* The argument pointer always points to the first argument. */ 1837#define FIRST_PARM_OFFSET(FNDECL) 0 1838 1839/* o32 and o64 reserve stack space for all argument registers. */ 1840#define REG_PARM_STACK_SPACE(FNDECL) \ 1841 (TARGET_OLDABI \ 1842 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ 1843 : 0) 1844 1845/* Define this if it is the responsibility of the caller to 1846 allocate the area reserved for arguments passed in registers. 1847 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 1848 of this macro is to determine whether the space is included in 1849 `current_function_outgoing_args_size'. */ 1850#define OUTGOING_REG_PARM_STACK_SPACE 1851 1852#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) 1853 1854#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1855 1856/* Symbolic macros for the registers used to return integer and floating 1857 point values. */ 1858 1859#define GP_RETURN (GP_REG_FIRST + 2) 1860#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) 1861 1862#define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) 1863 1864/* Symbolic macros for the first/last argument registers. */ 1865 1866#define GP_ARG_FIRST (GP_REG_FIRST + 4) 1867#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 1868#define FP_ARG_FIRST (FP_REG_FIRST + 12) 1869#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 1870 1871#define LIBCALL_VALUE(MODE) \ 1872 mips_function_value (NULL_TREE, NULL, (MODE)) 1873 1874#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1875 mips_function_value ((VALTYPE), (FUNC), VOIDmode) 1876 1877/* 1 if N is a possible register number for a function value. 1878 On the MIPS, R2 R3 and F0 F2 are the only register thus used. 1879 Currently, R2 and F0 are only implemented here (C has no complex type) */ 1880 1881#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \ 1882 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \ 1883 && (N) == FP_RETURN + 2)) 1884 1885/* 1 if N is a possible register number for function argument passing. 1886 We have no FP argument registers when soft-float. When FP registers 1887 are 32 bits, we can't directly reference the odd numbered ones. */ 1888 1889#define FUNCTION_ARG_REGNO_P(N) \ 1890 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ 1891 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \ 1892 && !fixed_regs[N]) 1893 1894/* This structure has to cope with two different argument allocation 1895 schemes. Most MIPS ABIs view the arguments as a structure, of which 1896 the first N words go in registers and the rest go on the stack. If I 1897 < N, the Ith word might go in Ith integer argument register or in a 1898 floating-point register. For these ABIs, we only need to remember 1899 the offset of the current argument into the structure. 1900 1901 The EABI instead allocates the integer and floating-point arguments 1902 separately. The first N words of FP arguments go in FP registers, 1903 the rest go on the stack. Likewise, the first N words of the other 1904 arguments go in integer registers, and the rest go on the stack. We 1905 need to maintain three counts: the number of integer registers used, 1906 the number of floating-point registers used, and the number of words 1907 passed on the stack. 1908 1909 We could keep separate information for the two ABIs (a word count for 1910 the standard ABIs, and three separate counts for the EABI). But it 1911 seems simpler to view the standard ABIs as forms of EABI that do not 1912 allocate floating-point registers. 1913 1914 So for the standard ABIs, the first N words are allocated to integer 1915 registers, and function_arg decides on an argument-by-argument basis 1916 whether that argument should really go in an integer register, or in 1917 a floating-point one. */ 1918 1919typedef struct mips_args { 1920 /* Always true for varargs functions. Otherwise true if at least 1921 one argument has been passed in an integer register. */ 1922 int gp_reg_found; 1923 1924 /* The number of arguments seen so far. */ 1925 unsigned int arg_number; 1926 1927 /* The number of integer registers used so far. For all ABIs except 1928 EABI, this is the number of words that have been added to the 1929 argument structure, limited to MAX_ARGS_IN_REGISTERS. */ 1930 unsigned int num_gprs; 1931 1932 /* For EABI, the number of floating-point registers used so far. */ 1933 unsigned int num_fprs; 1934 1935 /* The number of words passed on the stack. */ 1936 unsigned int stack_words; 1937 1938 /* On the mips16, we need to keep track of which floating point 1939 arguments were passed in general registers, but would have been 1940 passed in the FP regs if this were a 32 bit function, so that we 1941 can move them to the FP regs if we wind up calling a 32 bit 1942 function. We record this information in fp_code, encoded in base 1943 four. A zero digit means no floating point argument, a one digit 1944 means an SFmode argument, and a two digit means a DFmode argument, 1945 and a three digit is not used. The low order digit is the first 1946 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by 1947 an SFmode argument. ??? A more sophisticated approach will be 1948 needed if MIPS_ABI != ABI_32. */ 1949 int fp_code; 1950 1951 /* True if the function has a prototype. */ 1952 int prototype; 1953} CUMULATIVE_ARGS; 1954 1955/* Initialize a variable CUM of type CUMULATIVE_ARGS 1956 for a call to a function whose data type is FNTYPE. 1957 For a library call, FNTYPE is 0. */ 1958 1959#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1960 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \ 1961 1962/* Update the data in CUM to advance over an argument 1963 of mode MODE and data type TYPE. 1964 (TYPE is null for libcalls where that information may not be available.) */ 1965 1966#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1967 function_arg_advance (&CUM, MODE, TYPE, NAMED) 1968 1969/* Determine where to put an argument to a function. 1970 Value is zero to push the argument on the stack, 1971 or a hard register in which to store the argument. 1972 1973 MODE is the argument's machine mode. 1974 TYPE is the data type of the argument (as a tree). 1975 This is null for libcalls where that information may 1976 not be available. 1977 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1978 the preceding args and about the function being called. 1979 NAMED is nonzero if this argument is a named parameter 1980 (otherwise it is an extra parameter matching an ellipsis). */ 1981 1982#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1983 function_arg( &CUM, MODE, TYPE, NAMED) 1984 1985#define FUNCTION_ARG_BOUNDARY function_arg_boundary 1986 1987#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1988 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward) 1989 1990#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1991 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward) 1992 1993/* True if using EABI and varargs can be passed in floating-point 1994 registers. Under these conditions, we need a more complex form 1995 of va_list, which tracks GPR, FPR and stack arguments separately. */ 1996#define EABI_FLOAT_VARARGS_P \ 1997 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) 1998 1999 2000/* Say that the epilogue uses the return address register. Note that 2001 in the case of sibcalls, the values "used by the epilogue" are 2002 considered live at the start of the called function. */ 2003#define EPILOGUE_USES(REGNO) ((REGNO) == 31) 2004 2005/* Treat LOC as a byte offset from the stack pointer and round it up 2006 to the next fully-aligned offset. */ 2007#define MIPS_STACK_ALIGN(LOC) \ 2008 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8) 2009 2010 2011/* Implement `va_start' for varargs and stdarg. */ 2012#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 2013 mips_va_start (valist, nextarg) 2014 2015/* Output assembler code to FILE to increment profiler label # LABELNO 2016 for profiling a function entry. */ 2017 2018#define FUNCTION_PROFILER(FILE, LABELNO) \ 2019{ \ 2020 if (TARGET_MIPS16) \ 2021 sorry ("mips16 function profiling"); \ 2022 fprintf (FILE, "\t.set\tnoat\n"); \ 2023 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \ 2024 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \ 2025 if (!TARGET_NEWABI) \ 2026 { \ 2027 fprintf (FILE, \ 2028 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \ 2029 TARGET_64BIT ? "dsubu" : "subu", \ 2030 reg_names[STACK_POINTER_REGNUM], \ 2031 reg_names[STACK_POINTER_REGNUM], \ 2032 Pmode == DImode ? 16 : 8); \ 2033 } \ 2034 fprintf (FILE, "\tjal\t_mcount\n"); \ 2035 fprintf (FILE, "\t.set\tat\n"); \ 2036} 2037 2038/* No mips port has ever used the profiler counter word, so don't emit it 2039 or the label for it. */ 2040 2041#define NO_PROFILE_COUNTERS 1 2042 2043/* Define this macro if the code for function profiling should come 2044 before the function prologue. Normally, the profiling code comes 2045 after. */ 2046 2047/* #define PROFILE_BEFORE_PROLOGUE */ 2048 2049/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 2050 the stack pointer does not matter. The value is tested only in 2051 functions that have frame pointers. 2052 No definition is equivalent to always zero. */ 2053 2054#define EXIT_IGNORE_STACK 1 2055 2056 2057/* A C statement to output, on the stream FILE, assembler code for a 2058 block of data that contains the constant parts of a trampoline. 2059 This code should not include a label--the label is taken care of 2060 automatically. */ 2061 2062#define TRAMPOLINE_TEMPLATE(STREAM) \ 2063{ \ 2064 if (ptr_mode == DImode) \ 2065 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \ 2066 else \ 2067 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \ 2068 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \ 2069 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \ 2070 if (ptr_mode == DImode) \ 2071 { \ 2072 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \ 2073 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \ 2074 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \ 2075 } \ 2076 else \ 2077 { \ 2078 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \ 2079 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \ 2080 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \ 2081 } \ 2082 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \ 2083 if (ptr_mode == DImode) \ 2084 { \ 2085 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \ 2086 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \ 2087 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \ 2088 } \ 2089 else \ 2090 { \ 2091 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \ 2092 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \ 2093 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \ 2094 } \ 2095} 2096 2097/* A C expression for the size in bytes of the trampoline, as an 2098 integer. */ 2099 2100#define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2) 2101 2102/* Alignment required for trampolines, in bits. */ 2103 2104#define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode) 2105 2106/* INITIALIZE_TRAMPOLINE calls this library function to flush 2107 program and data caches. */ 2108 2109#ifndef CACHE_FLUSH_FUNC 2110#define CACHE_FLUSH_FUNC "_flush_cache" 2111#endif 2112 2113/* A C statement to initialize the variable parts of a trampoline. 2114 ADDR is an RTX for the address of the trampoline; FNADDR is an 2115 RTX for the address of the nested function; STATIC_CHAIN is an 2116 RTX for the static chain value that should be passed to the 2117 function when it is called. */ 2118 2119#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \ 2120{ \ 2121 rtx func_addr, chain_addr; \ 2122 \ 2123 func_addr = plus_constant (ADDR, 32); \ 2124 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \ 2125 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \ 2126 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \ 2127 \ 2128 /* Flush both caches. We need to flush the data cache in case \ 2129 the system has a write-back cache. */ \ 2130 /* ??? Should check the return value for errors. */ \ 2131 if (mips_cache_flush_func && mips_cache_flush_func[0]) \ 2132 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ 2133 0, VOIDmode, 3, ADDR, Pmode, \ 2134 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\ 2135 GEN_INT (3), TYPE_MODE (integer_type_node)); \ 2136} 2137 2138/* Addressing modes, and classification of registers for them. */ 2139 2140#define REGNO_OK_FOR_INDEX_P(REGNO) 0 2141#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 2142 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) 2143 2144/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2145 and check its validity for a certain class. 2146 We have two alternate definitions for each of them. 2147 The usual definition accepts all pseudo regs; the other rejects them all. 2148 The symbol REG_OK_STRICT causes the latter definition to be used. 2149 2150 Most source files want to accept pseudo regs in the hope that 2151 they will get allocated to the class that the insn wants them to be in. 2152 Some source files that are used after register allocation 2153 need to be strict. */ 2154 2155#ifndef REG_OK_STRICT 2156#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2157 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) 2158#else 2159#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2160 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) 2161#endif 2162 2163#define REG_OK_FOR_INDEX_P(X) 0 2164 2165 2166/* Maximum number of registers that can appear in a valid memory address. */ 2167 2168#define MAX_REGS_PER_ADDRESS 1 2169 2170#ifdef REG_OK_STRICT 2171#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2172{ \ 2173 if (mips_legitimate_address_p (MODE, X, 1)) \ 2174 goto ADDR; \ 2175} 2176#else 2177#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2178{ \ 2179 if (mips_legitimate_address_p (MODE, X, 0)) \ 2180 goto ADDR; \ 2181} 2182#endif 2183 2184/* Check for constness inline but use mips_legitimate_address_p 2185 to check whether a constant really is an address. */ 2186 2187#define CONSTANT_ADDRESS_P(X) \ 2188 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0)) 2189 2190#define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0) 2191 2192#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2193 do { \ 2194 if (mips_legitimize_address (&(X), MODE)) \ 2195 goto WIN; \ 2196 } while (0) 2197 2198 2199/* A C statement or compound statement with a conditional `goto 2200 LABEL;' executed if memory address X (an RTX) can have different 2201 meanings depending on the machine mode of the memory reference it 2202 is used for. 2203 2204 Autoincrement and autodecrement addresses typically have 2205 mode-dependent effects because the amount of the increment or 2206 decrement is the size of the operand being addressed. Some 2207 machines have other mode-dependent addresses. Many RISC machines 2208 have no mode-dependent addresses. 2209 2210 You may assume that ADDR is a valid address for the machine. */ 2211 2212#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} 2213 2214/* This handles the magic '..CURRENT_FUNCTION' symbol, which means 2215 'the start of the function that this code is output in'. */ 2216 2217#define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2218 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 2219 asm_fprintf ((FILE), "%U%s", \ 2220 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ 2221 else \ 2222 asm_fprintf ((FILE), "%U%s", (NAME)) 2223 2224/* Flag to mark a function decl symbol that requires a long call. */ 2225#define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) 2226#define SYMBOL_REF_LONG_CALL_P(X) \ 2227 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) 2228 2229/* Specify the machine mode that this machine uses 2230 for the index in the tablejump instruction. 2231 ??? Using HImode in mips16 mode can cause overflow. */ 2232#define CASE_VECTOR_MODE \ 2233 (TARGET_MIPS16 ? HImode : ptr_mode) 2234 2235/* Define as C expression which evaluates to nonzero if the tablejump 2236 instruction expects the table to contain offsets from the address of the 2237 table. 2238 Do not define this if the table should contain absolute addresses. */ 2239#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16) 2240 2241/* Define this as 1 if `char' should by default be signed; else as 0. */ 2242#ifndef DEFAULT_SIGNED_CHAR 2243#define DEFAULT_SIGNED_CHAR 1 2244#endif 2245 2246/* Max number of bytes we can move from memory to memory 2247 in one reasonably fast instruction. */ 2248#define MOVE_MAX (TARGET_64BIT ? 8 : 4) 2249#define MAX_MOVE_MAX 8 2250 2251/* Define this macro as a C expression which is nonzero if 2252 accessing less than a word of memory (i.e. a `char' or a 2253 `short') is no faster than accessing a word of memory, i.e., if 2254 such access require more than one instruction or if there is no 2255 difference in cost between byte and (aligned) word loads. 2256 2257 On RISC machines, it tends to generate better code to define 2258 this as 1, since it avoids making a QI or HI mode register. */ 2259#define SLOW_BYTE_ACCESS 1 2260 2261/* Define this to be nonzero if shift instructions ignore all but the low-order 2262 few bits. */ 2263#define SHIFT_COUNT_TRUNCATED 1 2264 2265/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2266 is done just by pretending it is already truncated. */ 2267#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ 2268 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1) 2269 2270 2271/* Specify the machine mode that pointers have. 2272 After generation of rtl, the compiler makes no further distinction 2273 between pointers and any other objects of this machine mode. */ 2274 2275#ifndef Pmode 2276#define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) 2277#endif 2278 2279/* Give call MEMs SImode since it is the "most permissive" mode 2280 for both 32-bit and 64-bit targets. */ 2281 2282#define FUNCTION_MODE SImode 2283 2284 2285/* The cost of loading values from the constant pool. It should be 2286 larger than the cost of any constant we want to synthesize in-line. */ 2287 2288#define CONSTANT_POOL_COST COSTS_N_INSNS (8) 2289 2290/* A C expression for the cost of moving data from a register in 2291 class FROM to one in class TO. The classes are expressed using 2292 the enumeration values such as `GENERAL_REGS'. A value of 2 is 2293 the default; other values are interpreted relative to that. 2294 2295 It is not required that the cost always equal 2 when FROM is the 2296 same as TO; on some machines it is expensive to move between 2297 registers if they are not general registers. 2298 2299 If reload sees an insn consisting of a single `set' between two 2300 hard registers, and if `REGISTER_MOVE_COST' applied to their 2301 classes returns a value of 2, reload does not check to ensure 2302 that the constraints of the insn are met. Setting a cost of 2303 other than 2 will allow reload to verify that the constraints are 2304 met. You should do this if the `movM' pattern's constraints do 2305 not allow such copying. */ 2306 2307#define REGISTER_MOVE_COST(MODE, FROM, TO) \ 2308 mips_register_move_cost (MODE, FROM, TO) 2309 2310#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ 2311 (mips_cost->memory_latency \ 2312 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P))) 2313 2314/* Define if copies to/from condition code registers should be avoided. 2315 2316 This is needed for the MIPS because reload_outcc is not complete; 2317 it needs to handle cases where the source is a general or another 2318 condition code register. */ 2319#define AVOID_CCMODE_COPIES 2320 2321/* A C expression for the cost of a branch instruction. A value of 2322 1 is the default; other values are interpreted relative to that. */ 2323 2324#define BRANCH_COST mips_cost->branch_cost 2325#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 2326 2327/* If defined, modifies the length assigned to instruction INSN as a 2328 function of the context in which it is used. LENGTH is an lvalue 2329 that contains the initially computed length of the insn and should 2330 be updated with the correct length of the insn. */ 2331#define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2332 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) 2333 2334/* Return the asm template for a non-MIPS16 conditional branch instruction. 2335 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for 2336 its operands. */ 2337#define MIPS_BRANCH(OPCODE, OPERANDS) \ 2338 "%*" OPCODE "%?\t" OPERANDS "%/" 2339 2340/* Return the asm template for a call. INSN is the instruction's mnemonic 2341 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number 2342 of the target. 2343 2344 When generating -mabicalls without explicit relocation operators, 2345 all calls should use assembly macros. Otherwise, all indirect 2346 calls should use "jr" or "jalr"; we will arrange to restore $gp 2347 afterwards if necessary. Finally, we can only generate direct 2348 calls for -mabicalls by temporarily switching to non-PIC mode. */ 2349#define MIPS_CALL(INSN, OPERANDS, OPNO) \ 2350 (TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS \ 2351 ? "%*" INSN "\t%" #OPNO "%/" \ 2352 : REG_P (OPERANDS[OPNO]) \ 2353 ? "%*" INSN "r\t%" #OPNO "%/" \ 2354 : TARGET_ABICALLS \ 2355 ? (".option\tpic0\n\t" \ 2356 "%*" INSN "\t%" #OPNO "%/\n\t" \ 2357 ".option\tpic2") \ 2358 : "%*" INSN "\t%" #OPNO "%/") 2359 2360/* Control the assembler format that we output. */ 2361 2362/* Output to assembler file text saying following lines 2363 may contain character constants, extra white space, comments, etc. */ 2364 2365#ifndef ASM_APP_ON 2366#define ASM_APP_ON " #APP\n" 2367#endif 2368 2369/* Output to assembler file text saying following lines 2370 no longer contain unusual constructs. */ 2371 2372#ifndef ASM_APP_OFF 2373#define ASM_APP_OFF " #NO_APP\n" 2374#endif 2375 2376#define REGISTER_NAMES \ 2377{ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ 2378 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 2379 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 2380 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ 2381 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ 2382 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 2383 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ 2384 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ 2385 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ 2386 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \ 2387 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ 2388 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ 2389 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ 2390 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ 2391 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ 2392 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ 2393 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ 2394 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ 2395 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ 2396 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ 2397 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ 2398 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ 2399 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ 2400 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } 2401 2402/* List the "software" names for each register. Also list the numerical 2403 names for $fp and $sp. */ 2404 2405#define ADDITIONAL_REGISTER_NAMES \ 2406{ \ 2407 { "$29", 29 + GP_REG_FIRST }, \ 2408 { "$30", 30 + GP_REG_FIRST }, \ 2409 { "at", 1 + GP_REG_FIRST }, \ 2410 { "v0", 2 + GP_REG_FIRST }, \ 2411 { "v1", 3 + GP_REG_FIRST }, \ 2412 { "a0", 4 + GP_REG_FIRST }, \ 2413 { "a1", 5 + GP_REG_FIRST }, \ 2414 { "a2", 6 + GP_REG_FIRST }, \ 2415 { "a3", 7 + GP_REG_FIRST }, \ 2416 { "t0", 8 + GP_REG_FIRST }, \ 2417 { "t1", 9 + GP_REG_FIRST }, \ 2418 { "t2", 10 + GP_REG_FIRST }, \ 2419 { "t3", 11 + GP_REG_FIRST }, \ 2420 { "t4", 12 + GP_REG_FIRST }, \ 2421 { "t5", 13 + GP_REG_FIRST }, \ 2422 { "t6", 14 + GP_REG_FIRST }, \ 2423 { "t7", 15 + GP_REG_FIRST }, \ 2424 { "s0", 16 + GP_REG_FIRST }, \ 2425 { "s1", 17 + GP_REG_FIRST }, \ 2426 { "s2", 18 + GP_REG_FIRST }, \ 2427 { "s3", 19 + GP_REG_FIRST }, \ 2428 { "s4", 20 + GP_REG_FIRST }, \ 2429 { "s5", 21 + GP_REG_FIRST }, \ 2430 { "s6", 22 + GP_REG_FIRST }, \ 2431 { "s7", 23 + GP_REG_FIRST }, \ 2432 { "t8", 24 + GP_REG_FIRST }, \ 2433 { "t9", 25 + GP_REG_FIRST }, \ 2434 { "k0", 26 + GP_REG_FIRST }, \ 2435 { "k1", 27 + GP_REG_FIRST }, \ 2436 { "gp", 28 + GP_REG_FIRST }, \ 2437 { "sp", 29 + GP_REG_FIRST }, \ 2438 { "fp", 30 + GP_REG_FIRST }, \ 2439 { "ra", 31 + GP_REG_FIRST }, \ 2440 ALL_COP_ADDITIONAL_REGISTER_NAMES \ 2441} 2442 2443/* This is meant to be redefined in the host dependent files. It is a 2444 set of alternative names and regnums for mips coprocessors. */ 2445 2446#define ALL_COP_ADDITIONAL_REGISTER_NAMES 2447 2448/* A C compound statement to output to stdio stream STREAM the 2449 assembler syntax for an instruction operand X. X is an RTL 2450 expression. 2451 2452 CODE is a value that can be used to specify one of several ways 2453 of printing the operand. It is used when identical operands 2454 must be printed differently depending on the context. CODE 2455 comes from the `%' specification that was used to request 2456 printing of the operand. If the specification was just `%DIGIT' 2457 then CODE is 0; if the specification was `%LTR DIGIT' then CODE 2458 is the ASCII code for LTR. 2459 2460 If X is a register, this macro should print the register's name. 2461 The names can be found in an array `reg_names' whose type is 2462 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. 2463 2464 When the machine description has a specification `%PUNCT' (a `%' 2465 followed by a punctuation character), this macro is called with 2466 a null pointer for X and the punctuation character for CODE. 2467 2468 See mips.c for the MIPS specific codes. */ 2469 2470#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2471 2472/* A C expression which evaluates to true if CODE is a valid 2473 punctuation character for use in the `PRINT_OPERAND' macro. If 2474 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no 2475 punctuation characters (except for the standard one, `%') are 2476 used in this way. */ 2477 2478#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE] 2479 2480/* A C compound statement to output to stdio stream STREAM the 2481 assembler syntax for an instruction operand that is a memory 2482 reference whose address is ADDR. ADDR is an RTL expression. */ 2483 2484#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2485 2486 2487/* A C statement, to be executed after all slot-filler instructions 2488 have been output. If necessary, call `dbr_sequence_length' to 2489 determine the number of slots filled in a sequence (zero if not 2490 currently outputting a sequence), to decide how many no-ops to 2491 output, or whatever. 2492 2493 Don't define this macro if it has nothing to do, but it is 2494 helpful in reading assembly output if the extent of the delay 2495 sequence is made explicit (e.g. with white space). 2496 2497 Note that output routines for instructions with delay slots must 2498 be prepared to deal with not being output as part of a sequence 2499 (i.e. when the scheduling pass is not run, or when no slot 2500 fillers could be found.) The variable `final_sequence' is null 2501 when not processing a sequence, otherwise it contains the 2502 `sequence' rtx being output. */ 2503 2504#define DBR_OUTPUT_SEQEND(STREAM) \ 2505do \ 2506 { \ 2507 if (set_nomacro > 0 && --set_nomacro == 0) \ 2508 fputs ("\t.set\tmacro\n", STREAM); \ 2509 \ 2510 if (set_noreorder > 0 && --set_noreorder == 0) \ 2511 fputs ("\t.set\treorder\n", STREAM); \ 2512 \ 2513 fputs ("\n", STREAM); \ 2514 } \ 2515while (0) 2516 2517 2518/* How to tell the debugger about changes of source files. */ 2519#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ 2520 mips_output_filename (STREAM, NAME) 2521 2522/* mips-tfile does not understand .stabd directives. */ 2523#define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \ 2524 dbxout_begin_stabn_sline (LINE); \ 2525 dbxout_stab_value_internal_label ("LM", &COUNTER); \ 2526} while (0) 2527 2528/* Use .loc directives for SDB line numbers. */ 2529#define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \ 2530 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE) 2531 2532/* The MIPS implementation uses some labels for its own purpose. The 2533 following lists what labels are created, and are all formed by the 2534 pattern $L[a-z].*. The machine independent portion of GCC creates 2535 labels matching: $L[A-Z][0-9]+ and $L[0-9]+. 2536 2537 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. 2538 $Lb[0-9]+ Begin blocks for MIPS debug support 2539 $Lc[0-9]+ Label for use in s<xx> operation. 2540 $Le[0-9]+ End blocks for MIPS debug support */ 2541 2542#undef ASM_DECLARE_OBJECT_NAME 2543#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ 2544 mips_declare_object (STREAM, NAME, "", ":\n", 0) 2545 2546/* Globalizing directive for a label. */ 2547#define GLOBAL_ASM_OP "\t.globl\t" 2548 2549/* This says how to define a global common symbol. */ 2550 2551#define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common 2552 2553/* This says how to define a local common symbol (i.e., not visible to 2554 linker). */ 2555 2556#ifndef ASM_OUTPUT_ALIGNED_LOCAL 2557#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ 2558 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) 2559#endif 2560 2561/* This says how to output an external. It would be possible not to 2562 output anything and let undefined symbol become external. However 2563 the assembler uses length information on externals to allocate in 2564 data/sdata bss/sbss, thereby saving exec time. */ 2565 2566#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ 2567 mips_output_external(STREAM,DECL,NAME) 2568 2569/* This is how to declare a function name. The actual work of 2570 emitting the label is moved to function_prologue, so that we can 2571 get the line number correctly emitted before the .ent directive, 2572 and after any .file directives. Define as empty so that the function 2573 is not declared before the .ent directive elsewhere. */ 2574 2575#undef ASM_DECLARE_FUNCTION_NAME 2576#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) 2577 2578#ifndef FUNCTION_NAME_ALREADY_DECLARED 2579#define FUNCTION_NAME_ALREADY_DECLARED 0 2580#endif 2581 2582/* This is how to store into the string LABEL 2583 the symbol_ref name of an internal numbered label where 2584 PREFIX is the class of label and NUM is the number within the class. 2585 This is suitable for output with `assemble_name'. */ 2586 2587#undef ASM_GENERATE_INTERNAL_LABEL 2588#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2589 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 2590 2591/* This is how to output an element of a case-vector that is absolute. */ 2592 2593#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 2594 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2595 ptr_mode == DImode ? ".dword" : ".word", \ 2596 LOCAL_LABEL_PREFIX, \ 2597 VALUE) 2598 2599/* This is how to output an element of a case-vector. We can make the 2600 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word 2601 is supported. */ 2602 2603#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 2604do { \ 2605 if (TARGET_MIPS16) \ 2606 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ 2607 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 2608 else if (TARGET_GPWORD) \ 2609 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2610 ptr_mode == DImode ? ".gpdword" : ".gpword", \ 2611 LOCAL_LABEL_PREFIX, VALUE); \ 2612 else \ 2613 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2614 ptr_mode == DImode ? ".dword" : ".word", \ 2615 LOCAL_LABEL_PREFIX, VALUE); \ 2616} while (0) 2617 2618/* When generating MIPS16 code, we want the jump table to be in the text 2619 section so that we can load its address using a PC-relative addition. */ 2620#define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16 2621 2622/* This is how to output an assembler line 2623 that says to advance the location counter 2624 to a multiple of 2**LOG bytes. */ 2625 2626#define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 2627 fprintf (STREAM, "\t.align\t%d\n", (LOG)) 2628 2629/* This is how to output an assembler line to advance the location 2630 counter by SIZE bytes. */ 2631 2632#undef ASM_OUTPUT_SKIP 2633#define ASM_OUTPUT_SKIP(STREAM,SIZE) \ 2634 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 2635 2636/* This is how to output a string. */ 2637#undef ASM_OUTPUT_ASCII 2638#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \ 2639 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t") 2640 2641/* Output #ident as a in the read-only data section. */ 2642#undef ASM_OUTPUT_IDENT 2643#define ASM_OUTPUT_IDENT(FILE, STRING) \ 2644{ \ 2645 const char *p = STRING; \ 2646 int size = strlen (p) + 1; \ 2647 switch_to_section (readonly_data_section); \ 2648 assemble_string (p, size); \ 2649} 2650 2651/* Default to -G 8 */ 2652#ifndef MIPS_DEFAULT_GVALUE 2653#define MIPS_DEFAULT_GVALUE 8 2654#endif 2655 2656/* Define the strings to put out for each section in the object file. */ 2657#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 2658#define DATA_SECTION_ASM_OP "\t.data" /* large data */ 2659 2660#undef READONLY_DATA_SECTION_ASM_OP 2661#define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ 2662 2663#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 2664do \ 2665 { \ 2666 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \ 2667 TARGET_64BIT ? "dsubu" : "subu", \ 2668 reg_names[STACK_POINTER_REGNUM], \ 2669 reg_names[STACK_POINTER_REGNUM], \ 2670 TARGET_64BIT ? "sd" : "sw", \ 2671 reg_names[REGNO], \ 2672 reg_names[STACK_POINTER_REGNUM]); \ 2673 } \ 2674while (0) 2675 2676#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 2677do \ 2678 { \ 2679 if (! set_noreorder) \ 2680 fprintf (STREAM, "\t.set\tnoreorder\n"); \ 2681 \ 2682 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ 2683 TARGET_64BIT ? "ld" : "lw", \ 2684 reg_names[REGNO], \ 2685 reg_names[STACK_POINTER_REGNUM], \ 2686 TARGET_64BIT ? "daddu" : "addu", \ 2687 reg_names[STACK_POINTER_REGNUM], \ 2688 reg_names[STACK_POINTER_REGNUM]); \ 2689 \ 2690 if (! set_noreorder) \ 2691 fprintf (STREAM, "\t.set\treorder\n"); \ 2692 } \ 2693while (0) 2694 2695/* How to start an assembler comment. 2696 The leading space is important (the mips native assembler requires it). */ 2697#ifndef ASM_COMMENT_START 2698#define ASM_COMMENT_START " #" 2699#endif 2700 2701/* Default definitions for size_t and ptrdiff_t. We must override the 2702 definitions from ../svr4.h on mips-*-linux-gnu. */ 2703 2704#undef SIZE_TYPE 2705#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 2706 2707#undef PTRDIFF_TYPE 2708#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 2709 2710#ifndef __mips16 2711/* Since the bits of the _init and _fini function is spread across 2712 many object files, each potentially with its own GP, we must assume 2713 we need to load our GP. We don't preserve $gp or $ra, since each 2714 init/fini chunk is supposed to initialize $gp, and crti/crtn 2715 already take care of preserving $ra and, when appropriate, $gp. */ 2716#if (defined _ABIO32 && _MIPS_SIM == _ABIO32) 2717#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2718 asm (SECTION_OP "\n\ 2719 .set noreorder\n\ 2720 bal 1f\n\ 2721 nop\n\ 27221: .cpload $31\n\ 2723 .set reorder\n\ 2724 jal " USER_LABEL_PREFIX #FUNC "\n\ 2725 " TEXT_SECTION_ASM_OP); 2726#endif /* Switch to #elif when we're no longer limited by K&R C. */ 2727#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 2728 || (defined _ABI64 && _MIPS_SIM == _ABI64) 2729#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2730 asm (SECTION_OP "\n\ 2731 .set noreorder\n\ 2732 bal 1f\n\ 2733 nop\n\ 27341: .set reorder\n\ 2735 .cpsetup $31, $2, 1b\n\ 2736 jal " USER_LABEL_PREFIX #FUNC "\n\ 2737 " TEXT_SECTION_ASM_OP); 2738#endif 2739#endif 2740 2741#ifndef HAVE_AS_TLS 2742#define HAVE_AS_TLS 0 2743#endif 2744