1;; DFA-based pipeline descriptions for MIPS32 4K processor family 2;; Contributed by Nigel Stephens (nigel@mips.com) 3;; and David Ung (davidu@mips.com) 4;; 5;; References: 6;; "MIPS32 4K Processor Core Family Software User's Manual, 7;; Doc no: MD00016, Rev 1.18, Nov 15, 2004." 8;; 9;; 4Kc - pipelined multiplier and translation lookaside buffer (TLB) 10;; 4km - pipelined multiplier and block address translator (BAT) 11;; 4kp - non-pipelined multiplier and block address translator (BAT) 12;; 13;; Copyright (C) 2005 Free Software Foundation, Inc. 14;; 15;; This file is part of GCC. 16;; 17;; GCC is free software; you can redistribute it and/or modify it 18;; under the terms of the GNU General Public License as published 19;; by the Free Software Foundation; either version 2, or (at your 20;; option) any later version. 21 22;; GCC is distributed in the hope that it will be useful, but WITHOUT 23;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 25;; License for more details. 26 27;; You should have received a copy of the GNU General Public License 28;; along with GCC; see the file COPYING. If not, write to the 29;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 30;; MA 02110-1301, USA. 31 32(define_automaton "r4k_cpu, r4k_mdu") 33 34;; Integer execution unit. 35(define_cpu_unit "r4k_ixu_arith" "r4k_cpu") 36(define_cpu_unit "r4k_ixu_mpydiv" "r4k_mdu") 37 38(define_insn_reservation "r4k_int_load" 2 39 (and (eq_attr "cpu" "4kc,4kp") 40 (eq_attr "type" "load")) 41 "r4k_ixu_arith") 42 43(define_insn_reservation "r4k_int_prefetch" 1 44 (and (eq_attr "cpu" "4kc,4kp") 45 (eq_attr "type" "prefetch")) 46 "r4k_ixu_arith") 47 48(define_insn_reservation "r4k_int_store" 1 49 (and (eq_attr "cpu" "4kc,4kp") 50 (eq_attr "type" "store")) 51 "r4k_ixu_arith") 52 53;; 4Kc/4Km 54;; unsigned divide - 8/16/24/32 bit operand have latencies 9/17/25/33 55;; signed divide - 8/16/24/32 bit operand have latencies 10/18/26/34 56(define_insn_reservation "r4k_idiv_4kc" 34 57 (and (eq_attr "cpu" "4kc") 58 (and (eq_attr "type" "idiv") 59 (eq_attr "mode" "!DI"))) 60 "r4k_ixu_arith+(r4k_ixu_mpydiv*34)") 61 62;; 4Kp 63;; unsigned divide - 33 64;; signed divide - 33-35 65(define_insn_reservation "r4k_idiv_4kp" 35 66 (and (eq_attr "cpu" "4kp") 67 (and (eq_attr "type" "idiv") 68 (eq_attr "mode" "!DI"))) 69 "r4k_ixu_arith+(r4k_ixu_mpydiv*35)") 70 71;; 4Kc/4Km fast 32x32 multiply 72;; 16x32 is faster, but there's no way to detect this 73(define_insn_reservation "r4k_mult_4kc" 2 74 (and (eq_attr "cpu" "4kc") 75 (and (eq_attr "type" "imul,imadd") 76 (eq_attr "mode" "SI"))) 77 "r4k_ixu_arith+(r4k_ixu_mpydiv*2)") 78 79;; 4Kc/4Km MUL has 2 cycle latency, but has the special property that it will 80;; stall the integer unit pipeline. MUL 16x16 or 32x16 forces 1 cycle stall, 81;; while MUL 32x32 forces 2 cycle stall. If next insn use the result, an 82;; additional stall is forced. 83(define_insn_reservation "r4k_mul_4kc" 4 84 (and (eq_attr "cpu" "4kc") 85 (and (eq_attr "type" "imul3") 86 (eq_attr "mode" "SI"))) 87 "(r4k_ixu_arith+r4k_ixu_mpydiv)*3") 88 89;; 4Kp slow iterative 2-op MULT 90;; Latency of 32 if next insn is MADD/MSUB,MFHI/MFLO. 91;; Repeat rate of 33 cycles. 92(define_insn_reservation "r4k_mult_4kp" 32 93 (and (eq_attr "cpu" "4kp") 94 (and (eq_attr "type" "imul") 95 (eq_attr "mode" "SI"))) 96 "r4k_ixu_arith+(r4k_ixu_mpydiv*32)") 97 98;; 4Kp slow iterative 3-op MUL 99;; Latency of 32 cycles, but stalls the whole pipeline until complete. 100(define_insn_reservation "r4k_mul_4kp" 32 101 (and (eq_attr "cpu" "4kp") 102 (and (eq_attr "type" "imul3") 103 (eq_attr "mode" "SI"))) 104 "(r4k_ixu_arith+r4k_ixu_mpydiv)*32") 105 106;; 4Kp slow iterative MADD 107;; Latency of 34 if next use insn is MADD/MSUB,MFHI/MFLO. 108;; Repeat rate of 35 cycles. 109(define_insn_reservation "r4k_madd_4kp" 34 110 (and (eq_attr "cpu" "4kp") 111 (and (eq_attr "type" "imadd") 112 (eq_attr "mode" "SI"))) 113 "r4k_ixu_arith+(r4k_ixu_mpydiv*34)") 114 115;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency. 116(define_insn_reservation "r4k_int_mthilo" 1 117 (and (eq_attr "cpu" "4kc,4kp") 118 (eq_attr "type" "mthilo")) 119 "r4k_ixu_arith+r4k_ixu_mpydiv") 120 121;; Move from HI/LO -> integer operation has a 2 cycle latency. 122(define_insn_reservation "r4k_int_mfhilo" 2 123 (and (eq_attr "cpu" "4kc,4kp") 124 (eq_attr "type" "mfhilo")) 125 "r4k_ixu_arith+r4k_ixu_mpydiv") 126 127;; All other integer insns. 128(define_insn_reservation "r4k_int_alu" 1 129 (and (eq_attr "cpu" "4kc,4kp") 130 (eq_attr "type" "arith,condmove,shift,const,nop,slt")) 131 "r4k_ixu_arith") 132 133(define_insn_reservation "r4k_int_branch" 1 134 (and (eq_attr "cpu" "4kc,4kp") 135 (eq_attr "type" "branch")) 136 "r4k_ixu_arith") 137 138(define_insn_reservation "r4k_int_jump_4k" 1 139 (and (eq_attr "cpu" "4kc,4kp") 140 (eq_attr "type" "jump,call")) 141 "r4k_ixu_arith") 142 143;; mfcx/mtcx - non FPU 144;; (Disabled until we add cop0 support) 145;; (define_insn_reservation "r4k_int_cop" 2 146;; (and (eq_attr "cpu" "4kc,4kp") 147;; (eq_attr "type" "cop0")) 148;; "r4k_ixu_arith") 149 150;; Unknown or multi - single issue 151(define_insn_reservation "r4k_unknown" 1 152 (and (eq_attr "cpu" "4kc,4kp") 153 (eq_attr "type" "unknown,multi")) 154 "r4k_ixu_arith+r4k_ixu_mpydiv") 155