1/* This file is automatically generated by i386-gen.  Do not edit!  */
2
3/* i386 opcode table.  */
4
5const template i386_optab[] =
6{
7  { "mov", 2, 0xa0, None, Cpu64,
8    D|W|No_sSuf|No_xSuf,
9    { Disp64,
10      Acc } },
11  { "mov", 2, 0xa0, None, CpuNo64,
12    D|W|No_sSuf|No_qSuf|No_xSuf,
13    { Disp16|Disp32,
14      Acc } },
15  { "mov", 2, 0x88, None, 0,
16    D|W|Modrm|No_sSuf|No_xSuf,
17    { Reg8|Reg16|Reg32|Reg64,
18      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
19  { "mov", 2, 0xb0, None, 0,
20    W|ShortForm|No_sSuf|No_qSuf|No_xSuf,
21    { Imm8|Imm16|Imm32|Imm32S,
22      Reg8|Reg16|Reg32 } },
23  { "mov", 2, 0xc6, 0x0, 0,
24    W|Modrm|No_sSuf|No_xSuf,
25    { Imm8|Imm16|Imm32|Imm32S,
26      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
27  { "mov", 2, 0xb0, None, Cpu64,
28    W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
29    { Imm64,
30      Reg64 } },
31  { "mov", 2, 0x8c, None, 0,
32    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
33    { SReg2,
34      Reg16|Reg32|Reg64|RegMem } },
35  { "mov", 2, 0x8c, None, 0,
36    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
37    { SReg2,
38      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
39  { "mov", 2, 0x8c, None, Cpu386,
40    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
41    { SReg3,
42      Reg16|Reg32|Reg64|RegMem } },
43  { "mov", 2, 0x8c, None, Cpu386,
44    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
45    { SReg3,
46      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
47  { "mov", 2, 0x8e, None, 0,
48    Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
49    { Reg16|Reg32|Reg64,
50      SReg2 } },
51  { "mov", 2, 0x8e, None, 0,
52    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
53    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
54      SReg2 } },
55  { "mov", 2, 0x8e, None, Cpu386,
56    Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
57    { Reg16|Reg32|Reg64,
58      SReg3 } },
59  { "mov", 2, 0x8e, None, Cpu386,
60    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
61    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
62      SReg3 } },
63  { "mov", 2, 0xf20, None, Cpu386|CpuNo64,
64    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
65    { Control,
66      Reg32|RegMem } },
67  { "mov", 2, 0xf20, None, Cpu64,
68    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
69    { Control,
70      Reg64|RegMem } },
71  { "mov", 2, 0xf21, None, Cpu386|CpuNo64,
72    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
73    { Debug,
74      Reg32|RegMem } },
75  { "mov", 2, 0xf21, None, Cpu64,
76    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
77    { Debug,
78      Reg64|RegMem } },
79  { "mov", 2, 0xf24, None, Cpu386|CpuNo64,
80    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
81    { Test,
82      Reg32|RegMem } },
83  { "movabs", 2, 0xa0, None, Cpu64,
84    D|W|No_sSuf|No_xSuf,
85    { Disp64,
86      Acc } },
87  { "movabs", 2, 0xb0, None, Cpu64,
88    W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
89    { Imm64,
90      Reg64 } },
91  { "movsbl", 2, 0xfbe, None, Cpu386,
92    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
93    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
94      Reg32 } },
95  { "movsbw", 2, 0xfbe, None, Cpu386,
96    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
97    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
98      Reg16 } },
99  { "movswl", 2, 0xfbf, None, Cpu386,
100    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
101    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
102      Reg32 } },
103  { "movsbq", 2, 0xfbe, None, Cpu64,
104    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
105    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
106      Reg64 } },
107  { "movswq", 2, 0xfbf, None, Cpu64,
108    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
109    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
110      Reg64 } },
111  { "movslq", 2, 0x63, None, Cpu64,
112    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
113    { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
114      Reg64 } },
115  { "movsx", 2, 0xfbe, None, Cpu386,
116    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
117    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
118      Reg16|Reg32|Reg64 } },
119  { "movsx", 2, 0xfbf, None, Cpu386,
120    Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
121    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
122      Reg32|Reg64 } },
123  { "movsx", 2, 0x63, None, Cpu64,
124    Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
125    { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
126      Reg64 } },
127  { "movzb", 2, 0xfb6, None, Cpu386,
128    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
129    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
130      Reg16|Reg32|Reg64 } },
131  { "movzbl", 2, 0xfb6, None, Cpu386,
132    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
133    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
134      Reg32 } },
135  { "movzbw", 2, 0xfb6, None, Cpu386,
136    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
137    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
138      Reg16 } },
139  { "movzwl", 2, 0xfb7, None, Cpu386,
140    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
141    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
142      Reg32 } },
143  { "movzbq", 2, 0xfb6, None, Cpu64,
144    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
145    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
146      Reg64 } },
147  { "movzwq", 2, 0xfb7, None, Cpu64,
148    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
149    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
150      Reg64 } },
151  { "movzx", 2, 0xfb6, None, Cpu386,
152    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
153    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
154      Reg16|Reg32|Reg64 } },
155  { "movzx", 2, 0xfb7, None, Cpu386,
156    Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
157    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
158      Reg32|Reg64 } },
159  { "push", 1, 0x50, None, CpuNo64,
160    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
161    { Reg16|Reg32|Reg64 } },
162  { "push", 1, 0xff, 0x6, CpuNo64,
163    Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
164    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
165  { "push", 1, 0x6a, None, Cpu186|CpuNo64,
166    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
167    { Imm8S } },
168  { "push", 1, 0x68, None, Cpu186|CpuNo64,
169    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
170    { Imm16|Imm32 } },
171  { "push", 1, 0x6, None, CpuNo64,
172    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
173    { SReg2 } },
174  { "push", 1, 0xfa0, None, Cpu386|CpuNo64,
175    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
176    { SReg3 } },
177  { "push", 1, 0x50, None, Cpu64,
178    ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
179    { Reg16|Reg64 } },
180  { "push", 1, 0xff, 0x6, Cpu64,
181    Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
182    { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
183  { "push", 1, 0x6a, None, Cpu64,
184    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
185    { Imm8S } },
186  { "push", 1, 0x68, None, Cpu64,
187    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
188    { Imm16|Imm32S } },
189  { "push", 1, 0xfa0, None, Cpu64,
190    ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
191    { SReg3 } },
192  { "pusha", 0, 0x60, None, Cpu186|CpuNo64,
193    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
194    { 0 } },
195  { "pop", 1, 0x58, None, CpuNo64,
196    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
197    { Reg16|Reg32|Reg64 } },
198  { "pop", 1, 0x8f, 0x0, CpuNo64,
199    Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
200    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
201  { "pop", 1, 0x7, None, CpuNo64,
202    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
203    { SReg2 } },
204  { "pop", 1, 0xfa1, None, Cpu386|CpuNo64,
205    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
206    { SReg3 } },
207  { "pop", 1, 0x58, None, Cpu64,
208    ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
209    { Reg16|Reg64 } },
210  { "pop", 1, 0x8f, 0x0, Cpu64,
211    Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
212    { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
213  { "pop", 1, 0xfa1, None, Cpu64,
214    ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
215    { SReg3 } },
216  { "popa", 0, 0x61, None, Cpu186|CpuNo64,
217    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
218    { 0 } },
219  { "xchg", 2, 0x90, None, 0,
220    ShortForm|No_bSuf|No_sSuf|No_xSuf,
221    { Reg16|Reg32|Reg64,
222      Acc } },
223  { "xchg", 2, 0x90, None, 0,
224    ShortForm|No_bSuf|No_sSuf|No_xSuf,
225    { Acc,
226      Reg16|Reg32|Reg64 } },
227  { "xchg", 2, 0x86, None, 0,
228    W|Modrm|No_sSuf|No_xSuf,
229    { Reg8|Reg16|Reg32|Reg64,
230      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
231  { "xchg", 2, 0x86, None, 0,
232    W|Modrm|No_sSuf|No_xSuf,
233    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
234      Reg8|Reg16|Reg32|Reg64 } },
235  { "in", 2, 0xe4, None, 0,
236    W|No_sSuf|No_qSuf|No_xSuf,
237    { Imm8,
238      Acc } },
239  { "in", 2, 0xec, None, 0,
240    W|No_sSuf|No_qSuf|No_xSuf,
241    { InOutPortReg,
242      Acc } },
243  { "in", 1, 0xe4, None, 0,
244    W|No_sSuf|No_qSuf|No_xSuf,
245    { Imm8 } },
246  { "in", 1, 0xec, None, 0,
247    W|No_sSuf|No_qSuf|No_xSuf,
248    { InOutPortReg } },
249  { "out", 2, 0xe6, None, 0,
250    W|No_sSuf|No_qSuf|No_xSuf,
251    { Acc,
252      Imm8 } },
253  { "out", 2, 0xee, None, 0,
254    W|No_sSuf|No_qSuf|No_xSuf,
255    { Acc,
256      InOutPortReg } },
257  { "out", 1, 0xe6, None, 0,
258    W|No_sSuf|No_qSuf|No_xSuf,
259    { Imm8 } },
260  { "out", 1, 0xee, None, 0,
261    W|No_sSuf|No_qSuf|No_xSuf,
262    { InOutPortReg } },
263  { "lea", 2, 0x8d, None, 0,
264    Modrm|No_bSuf|No_sSuf|No_xSuf,
265    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
266      Reg16|Reg32|Reg64 } },
267  { "lds", 2, 0xc5, None, CpuNo64,
268    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
269    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
270      Reg16|Reg32|Reg64 } },
271  { "les", 2, 0xc4, None, CpuNo64,
272    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
273    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
274      Reg16|Reg32|Reg64 } },
275  { "lfs", 2, 0xfb4, None, Cpu386,
276    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
277    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
278      Reg16|Reg32|Reg64 } },
279  { "lgs", 2, 0xfb5, None, Cpu386,
280    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
281    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
282      Reg16|Reg32|Reg64 } },
283  { "lss", 2, 0xfb2, None, Cpu386,
284    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
285    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
286      Reg16|Reg32|Reg64 } },
287  { "clc", 0, 0xf8, None, 0,
288    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
289    { 0 } },
290  { "cld", 0, 0xfc, None, 0,
291    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
292    { 0 } },
293  { "cli", 0, 0xfa, None, 0,
294    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
295    { 0 } },
296  { "clts", 0, 0xf06, None, Cpu286,
297    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
298    { 0 } },
299  { "cmc", 0, 0xf5, None, 0,
300    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
301    { 0 } },
302  { "lahf", 0, 0x9f, None, 0,
303    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
304    { 0 } },
305  { "sahf", 0, 0x9e, None, 0,
306    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
307    { 0 } },
308  { "pushf", 0, 0x9c, None, CpuNo64,
309    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
310    { 0 } },
311  { "pushf", 0, 0x9c, None, Cpu64,
312    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
313    { 0 } },
314  { "popf", 0, 0x9d, None, CpuNo64,
315    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
316    { 0 } },
317  { "popf", 0, 0x9d, None, Cpu64,
318    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
319    { 0 } },
320  { "stc", 0, 0xf9, None, 0,
321    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
322    { 0 } },
323  { "std", 0, 0xfd, None, 0,
324    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
325    { 0 } },
326  { "sti", 0, 0xfb, None, 0,
327    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
328    { 0 } },
329  { "add", 2, 0x0, None, 0,
330    D|W|Modrm|No_sSuf|No_xSuf,
331    { Reg8|Reg16|Reg32|Reg64,
332      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
333  { "add", 2, 0x83, 0x0, 0,
334    Modrm|No_bSuf|No_sSuf|No_xSuf,
335    { Imm8S,
336      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
337  { "add", 2, 0x4, None, 0,
338    W|No_sSuf|No_xSuf,
339    { Imm8|Imm16|Imm32|Imm32S,
340      Acc } },
341  { "add", 2, 0x80, 0x0, 0,
342    W|Modrm|No_sSuf|No_xSuf,
343    { Imm8|Imm16|Imm32|Imm32S,
344      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
345  { "inc", 1, 0x40, None, CpuNo64,
346    ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
347    { Reg16|Reg32|Reg64 } },
348  { "inc", 1, 0xfe, 0x0, 0,
349    W|Modrm|No_sSuf|No_xSuf,
350    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
351  { "sub", 2, 0x28, None, 0,
352    D|W|Modrm|No_sSuf|No_xSuf,
353    { Reg8|Reg16|Reg32|Reg64,
354      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
355  { "sub", 2, 0x83, 0x5, 0,
356    Modrm|No_bSuf|No_sSuf|No_xSuf,
357    { Imm8S,
358      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
359  { "sub", 2, 0x2c, None, 0,
360    W|No_sSuf|No_xSuf,
361    { Imm8|Imm16|Imm32|Imm32S,
362      Acc } },
363  { "sub", 2, 0x80, 0x5, 0,
364    W|Modrm|No_sSuf|No_xSuf,
365    { Imm8|Imm16|Imm32|Imm32S,
366      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
367  { "dec", 1, 0x48, None, CpuNo64,
368    ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
369    { Reg16|Reg32|Reg64 } },
370  { "dec", 1, 0xfe, 0x1, 0,
371    W|Modrm|No_sSuf|No_xSuf,
372    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
373  { "sbb", 2, 0x18, None, 0,
374    D|W|Modrm|No_sSuf|No_xSuf,
375    { Reg8|Reg16|Reg32|Reg64,
376      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
377  { "sbb", 2, 0x83, 0x3, 0,
378    Modrm|No_bSuf|No_sSuf|No_xSuf,
379    { Imm8S,
380      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
381  { "sbb", 2, 0x1c, None, 0,
382    W|No_sSuf|No_xSuf,
383    { Imm8|Imm16|Imm32|Imm32S,
384      Acc } },
385  { "sbb", 2, 0x80, 0x3, 0,
386    W|Modrm|No_sSuf|No_xSuf,
387    { Imm8|Imm16|Imm32|Imm32S,
388      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
389  { "cmp", 2, 0x38, None, 0,
390    D|W|Modrm|No_sSuf|No_xSuf,
391    { Reg8|Reg16|Reg32|Reg64,
392      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
393  { "cmp", 2, 0x83, 0x7, 0,
394    Modrm|No_bSuf|No_sSuf|No_xSuf,
395    { Imm8S,
396      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
397  { "cmp", 2, 0x3c, None, 0,
398    W|No_sSuf|No_xSuf,
399    { Imm8|Imm16|Imm32|Imm32S,
400      Acc } },
401  { "cmp", 2, 0x80, 0x7, 0,
402    W|Modrm|No_sSuf|No_xSuf,
403    { Imm8|Imm16|Imm32|Imm32S,
404      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
405  { "test", 2, 0x84, None, 0,
406    W|Modrm|No_sSuf|No_xSuf,
407    { Reg8|Reg16|Reg32|Reg64,
408      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
409  { "test", 2, 0x84, None, 0,
410    W|Modrm|No_sSuf|No_xSuf,
411    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
412      Reg8|Reg16|Reg32|Reg64 } },
413  { "test", 2, 0xa8, None, 0,
414    W|No_sSuf|No_xSuf,
415    { Imm8|Imm16|Imm32|Imm32S,
416      Acc } },
417  { "test", 2, 0xf6, 0x0, 0,
418    W|Modrm|No_sSuf|No_xSuf,
419    { Imm8|Imm16|Imm32|Imm32S,
420      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
421  { "and", 2, 0x20, None, 0,
422    D|W|Modrm|No_sSuf|No_xSuf,
423    { Reg8|Reg16|Reg32|Reg64,
424      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
425  { "and", 2, 0x83, 0x4, 0,
426    Modrm|No_bSuf|No_sSuf|No_xSuf,
427    { Imm8S,
428      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
429  { "and", 2, 0x24, None, 0,
430    W|No_sSuf|No_xSuf,
431    { Imm8|Imm16|Imm32|Imm32S,
432      Acc } },
433  { "and", 2, 0x80, 0x4, 0,
434    W|Modrm|No_sSuf|No_xSuf,
435    { Imm8|Imm16|Imm32|Imm32S,
436      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
437  { "or", 2, 0x8, None, 0,
438    D|W|Modrm|No_sSuf|No_xSuf,
439    { Reg8|Reg16|Reg32|Reg64,
440      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
441  { "or", 2, 0x83, 0x1, 0,
442    Modrm|No_bSuf|No_sSuf|No_xSuf,
443    { Imm8S,
444      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
445  { "or", 2, 0xc, None, 0,
446    W|No_sSuf|No_xSuf,
447    { Imm8|Imm16|Imm32|Imm32S,
448      Acc } },
449  { "or", 2, 0x80, 0x1, 0,
450    W|Modrm|No_sSuf|No_xSuf,
451    { Imm8|Imm16|Imm32|Imm32S,
452      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
453  { "xor", 2, 0x30, None, 0,
454    D|W|Modrm|No_sSuf|No_xSuf,
455    { Reg8|Reg16|Reg32|Reg64,
456      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
457  { "xor", 2, 0x83, 0x6, 0,
458    Modrm|No_bSuf|No_sSuf|No_xSuf,
459    { Imm8S,
460      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
461  { "xor", 2, 0x34, None, 0,
462    W|No_sSuf|No_xSuf,
463    { Imm8|Imm16|Imm32|Imm32S,
464      Acc } },
465  { "xor", 2, 0x80, 0x6, 0,
466    W|Modrm|No_sSuf|No_xSuf,
467    { Imm8|Imm16|Imm32|Imm32S,
468      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
469  { "clr", 1, 0x30, None, 0,
470    W|Modrm|No_sSuf|No_xSuf|RegKludge,
471    { Reg8|Reg16|Reg32|Reg64 } },
472  { "adc", 2, 0x10, None, 0,
473    D|W|Modrm|No_sSuf|No_xSuf,
474    { Reg8|Reg16|Reg32|Reg64,
475      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
476  { "adc", 2, 0x83, 0x2, 0,
477    Modrm|No_bSuf|No_sSuf|No_xSuf,
478    { Imm8S,
479      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
480  { "adc", 2, 0x14, None, 0,
481    W|No_sSuf|No_xSuf,
482    { Imm8|Imm16|Imm32|Imm32S,
483      Acc } },
484  { "adc", 2, 0x80, 0x2, 0,
485    W|Modrm|No_sSuf|No_xSuf,
486    { Imm8|Imm16|Imm32|Imm32S,
487      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
488  { "neg", 1, 0xf6, 0x3, 0,
489    W|Modrm|No_sSuf|No_xSuf,
490    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
491  { "not", 1, 0xf6, 0x2, 0,
492    W|Modrm|No_sSuf|No_xSuf,
493    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
494  { "aaa", 0, 0x37, None, CpuNo64,
495    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
496    { 0 } },
497  { "aas", 0, 0x3f, None, CpuNo64,
498    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
499    { 0 } },
500  { "daa", 0, 0x27, None, CpuNo64,
501    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
502    { 0 } },
503  { "das", 0, 0x2f, None, CpuNo64,
504    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
505    { 0 } },
506  { "aad", 0, 0xd50a, None, CpuNo64,
507    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
508    { 0 } },
509  { "aad", 1, 0xd5, None, CpuNo64,
510    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
511    { Imm8 } },
512  { "aam", 0, 0xd40a, None, CpuNo64,
513    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
514    { 0 } },
515  { "aam", 1, 0xd4, None, CpuNo64,
516    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
517    { Imm8 } },
518  { "cbw", 0, 0x98, None, 0,
519    Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
520    { 0 } },
521  { "cdqe", 0, 0x98, None, Cpu64,
522    Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
523    { 0 } },
524  { "cwde", 0, 0x98, None, 0,
525    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
526    { 0 } },
527  { "cwd", 0, 0x99, None, 0,
528    Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
529    { 0 } },
530  { "cdq", 0, 0x99, None, 0,
531    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
532    { 0 } },
533  { "cqo", 0, 0x99, None, Cpu64,
534    Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
535    { 0 } },
536  { "cbtw", 0, 0x98, None, 0,
537    Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
538    { 0 } },
539  { "cltq", 0, 0x98, None, Cpu64,
540    Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
541    { 0 } },
542  { "cwtl", 0, 0x98, None, 0,
543    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
544    { 0 } },
545  { "cwtd", 0, 0x99, None, 0,
546    Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
547    { 0 } },
548  { "cltd", 0, 0x99, None, 0,
549    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
550    { 0 } },
551  { "cqto", 0, 0x99, None, Cpu64,
552    Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
553    { 0 } },
554  { "mul", 1, 0xf6, 0x4, 0,
555    W|Modrm|No_sSuf|No_xSuf,
556    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
557  { "imul", 1, 0xf6, 0x5, 0,
558    W|Modrm|No_sSuf|No_xSuf,
559    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
560  { "imul", 2, 0xfaf, None, Cpu386,
561    Modrm|No_bSuf|No_sSuf|No_xSuf,
562    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
563      Reg16|Reg32|Reg64 } },
564  { "imul", 3, 0x6b, None, Cpu186,
565    Modrm|No_bSuf|No_sSuf|No_xSuf,
566    { Imm8S,
567      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
568      Reg16|Reg32|Reg64 } },
569  { "imul", 3, 0x69, None, Cpu186,
570    Modrm|No_bSuf|No_sSuf|No_xSuf,
571    { Imm16|Imm32|Imm32S,
572      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
573      Reg16|Reg32|Reg64 } },
574  { "imul", 2, 0x6b, None, Cpu186,
575    Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge,
576    { Imm8S,
577      Reg16|Reg32|Reg64 } },
578  { "imul", 2, 0x69, None, Cpu186,
579    Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge,
580    { Imm16|Imm32|Imm32S,
581      Reg16|Reg32|Reg64 } },
582  { "div", 1, 0xf6, 0x6, 0,
583    W|Modrm|No_sSuf|No_xSuf,
584    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
585  { "div", 2, 0xf6, 0x6, 0,
586    W|Modrm|No_sSuf|No_xSuf,
587    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
588      Acc } },
589  { "idiv", 1, 0xf6, 0x7, 0,
590    W|Modrm|No_sSuf|No_xSuf,
591    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
592  { "idiv", 2, 0xf6, 0x7, 0,
593    W|Modrm|No_sSuf|No_xSuf,
594    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
595      Acc } },
596  { "rol", 2, 0xd0, 0x0, 0,
597    W|Modrm|No_sSuf|No_xSuf,
598    { Imm1,
599      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
600  { "rol", 2, 0xc0, 0x0, Cpu186,
601    W|Modrm|No_sSuf|No_xSuf,
602    { Imm8,
603      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
604  { "rol", 2, 0xd2, 0x0, 0,
605    W|Modrm|No_sSuf|No_xSuf,
606    { ShiftCount,
607      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
608  { "rol", 1, 0xd0, 0x0, 0,
609    W|Modrm|No_sSuf|No_xSuf,
610    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
611  { "ror", 2, 0xd0, 0x1, 0,
612    W|Modrm|No_sSuf|No_xSuf,
613    { Imm1,
614      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
615  { "ror", 2, 0xc0, 0x1, Cpu186,
616    W|Modrm|No_sSuf|No_xSuf,
617    { Imm8,
618      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
619  { "ror", 2, 0xd2, 0x1, 0,
620    W|Modrm|No_sSuf|No_xSuf,
621    { ShiftCount,
622      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
623  { "ror", 1, 0xd0, 0x1, 0,
624    W|Modrm|No_sSuf|No_xSuf,
625    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
626  { "rcl", 2, 0xd0, 0x2, 0,
627    W|Modrm|No_sSuf|No_xSuf,
628    { Imm1,
629      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
630  { "rcl", 2, 0xc0, 0x2, Cpu186,
631    W|Modrm|No_sSuf|No_xSuf,
632    { Imm8,
633      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
634  { "rcl", 2, 0xd2, 0x2, 0,
635    W|Modrm|No_sSuf|No_xSuf,
636    { ShiftCount,
637      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
638  { "rcl", 1, 0xd0, 0x2, 0,
639    W|Modrm|No_sSuf|No_xSuf,
640    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
641  { "rcr", 2, 0xd0, 0x3, 0,
642    W|Modrm|No_sSuf|No_xSuf,
643    { Imm1,
644      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
645  { "rcr", 2, 0xc0, 0x3, Cpu186,
646    W|Modrm|No_sSuf|No_xSuf,
647    { Imm8,
648      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
649  { "rcr", 2, 0xd2, 0x3, 0,
650    W|Modrm|No_sSuf|No_xSuf,
651    { ShiftCount,
652      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
653  { "rcr", 1, 0xd0, 0x3, 0,
654    W|Modrm|No_sSuf|No_xSuf,
655    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
656  { "sal", 2, 0xd0, 0x4, 0,
657    W|Modrm|No_sSuf|No_xSuf,
658    { Imm1,
659      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
660  { "sal", 2, 0xc0, 0x4, Cpu186,
661    W|Modrm|No_sSuf|No_xSuf,
662    { Imm8,
663      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
664  { "sal", 2, 0xd2, 0x4, 0,
665    W|Modrm|No_sSuf|No_xSuf,
666    { ShiftCount,
667      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
668  { "sal", 1, 0xd0, 0x4, 0,
669    W|Modrm|No_sSuf|No_xSuf,
670    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
671  { "shl", 2, 0xd0, 0x4, 0,
672    W|Modrm|No_sSuf|No_xSuf,
673    { Imm1,
674      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
675  { "shl", 2, 0xc0, 0x4, Cpu186,
676    W|Modrm|No_sSuf|No_xSuf,
677    { Imm8,
678      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
679  { "shl", 2, 0xd2, 0x4, 0,
680    W|Modrm|No_sSuf|No_xSuf,
681    { ShiftCount,
682      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
683  { "shl", 1, 0xd0, 0x4, 0,
684    W|Modrm|No_sSuf|No_xSuf,
685    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
686  { "shr", 2, 0xd0, 0x5, 0,
687    W|Modrm|No_sSuf|No_xSuf,
688    { Imm1,
689      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
690  { "shr", 2, 0xc0, 0x5, Cpu186,
691    W|Modrm|No_sSuf|No_xSuf,
692    { Imm8,
693      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
694  { "shr", 2, 0xd2, 0x5, 0,
695    W|Modrm|No_sSuf|No_xSuf,
696    { ShiftCount,
697      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
698  { "shr", 1, 0xd0, 0x5, 0,
699    W|Modrm|No_sSuf|No_xSuf,
700    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
701  { "sar", 2, 0xd0, 0x7, 0,
702    W|Modrm|No_sSuf|No_xSuf,
703    { Imm1,
704      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
705  { "sar", 2, 0xc0, 0x7, Cpu186,
706    W|Modrm|No_sSuf|No_xSuf,
707    { Imm8,
708      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
709  { "sar", 2, 0xd2, 0x7, 0,
710    W|Modrm|No_sSuf|No_xSuf,
711    { ShiftCount,
712      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
713  { "sar", 1, 0xd0, 0x7, 0,
714    W|Modrm|No_sSuf|No_xSuf,
715    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
716  { "shld", 3, 0xfa4, None, Cpu386,
717    Modrm|No_bSuf|No_sSuf|No_xSuf,
718    { Imm8,
719      Reg16|Reg32|Reg64,
720      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
721  { "shld", 3, 0xfa5, None, Cpu386,
722    Modrm|No_bSuf|No_sSuf|No_xSuf,
723    { ShiftCount,
724      Reg16|Reg32|Reg64,
725      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
726  { "shld", 2, 0xfa5, None, Cpu386,
727    Modrm|No_bSuf|No_sSuf|No_xSuf,
728    { Reg16|Reg32|Reg64,
729      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
730  { "shrd", 3, 0xfac, None, Cpu386,
731    Modrm|No_bSuf|No_sSuf|No_xSuf,
732    { Imm8,
733      Reg16|Reg32|Reg64,
734      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
735  { "shrd", 3, 0xfad, None, Cpu386,
736    Modrm|No_bSuf|No_sSuf|No_xSuf,
737    { ShiftCount,
738      Reg16|Reg32|Reg64,
739      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
740  { "shrd", 2, 0xfad, None, Cpu386,
741    Modrm|No_bSuf|No_sSuf|No_xSuf,
742    { Reg16|Reg32|Reg64,
743      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
744  { "call", 1, 0xe8, None, CpuNo64,
745    JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
746    { Disp16|Disp32 } },
747  { "call", 1, 0xe8, None, Cpu64,
748    JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
749    { Disp16|Disp32 } },
750  { "call", 1, 0xff, 0x2, CpuNo64,
751    Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
752    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
753  { "call", 1, 0xff, 0x2, Cpu64,
754    Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
755    { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
756  { "call", 2, 0x9a, None, CpuNo64,
757    JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
758    { Imm16,
759      Imm16|Imm32 } },
760  { "call", 1, 0xff, 0x3, 0,
761    Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
762    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
763  { "lcall", 2, 0x9a, None, CpuNo64,
764    JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
765    { Imm16,
766      Imm16|Imm32 } },
767  { "lcall", 1, 0xff, 0x3, 0,
768    Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
769    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
770  { "jmp", 1, 0xeb, None, 0,
771    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
772    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
773  { "jmp", 1, 0xff, 0x4, CpuNo64,
774    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
775    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
776  { "jmp", 1, 0xff, 0x4, Cpu64,
777    Modrm|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
778    { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
779  { "jmp", 2, 0xea, None, CpuNo64,
780    JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
781    { Imm16,
782      Imm16|Imm32 } },
783  { "jmp", 1, 0xff, 0x5, 0,
784    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
785    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
786  { "ljmp", 2, 0xea, None, CpuNo64,
787    JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
788    { Imm16,
789      Imm16|Imm32 } },
790  { "ljmp", 1, 0xff, 0x5, 0,
791    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
792    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
793  { "ret", 0, 0xc3, None, CpuNo64,
794    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
795    { 0 } },
796  { "ret", 1, 0xc2, None, CpuNo64,
797    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
798    { Imm16 } },
799  { "ret", 0, 0xc3, None, Cpu64,
800    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
801    { 0 } },
802  { "ret", 1, 0xc2, None, Cpu64,
803    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
804    { Imm16 } },
805  { "lret", 0, 0xcb, None, 0,
806    DefaultSize|No_bSuf|No_sSuf|No_xSuf,
807    { 0 } },
808  { "lret", 1, 0xca, None, 0,
809    DefaultSize|No_bSuf|No_sSuf|No_xSuf,
810    { Imm16 } },
811  { "enter", 2, 0xc8, None, Cpu186|CpuNo64,
812    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
813    { Imm16,
814      Imm8 } },
815  { "enter", 2, 0xc8, None, Cpu64,
816    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
817    { Imm16,
818      Imm8 } },
819  { "leave", 0, 0xc9, None, Cpu186|CpuNo64,
820    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
821    { 0 } },
822  { "leave", 0, 0xc9, None, Cpu64,
823    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
824    { 0 } },
825  { "jo", 1, 0x70, None, 0,
826    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
827    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
828  { "jno", 1, 0x71, None, 0,
829    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
830    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
831  { "jb", 1, 0x72, None, 0,
832    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
833    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
834  { "jc", 1, 0x72, None, 0,
835    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
836    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
837  { "jnae", 1, 0x72, None, 0,
838    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
839    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
840  { "jnb", 1, 0x73, None, 0,
841    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
842    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
843  { "jnc", 1, 0x73, None, 0,
844    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
845    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
846  { "jae", 1, 0x73, None, 0,
847    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
848    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
849  { "je", 1, 0x74, None, 0,
850    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
851    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
852  { "jz", 1, 0x74, None, 0,
853    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
854    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
855  { "jne", 1, 0x75, None, 0,
856    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
857    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
858  { "jnz", 1, 0x75, None, 0,
859    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
860    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
861  { "jbe", 1, 0x76, None, 0,
862    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
863    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
864  { "jna", 1, 0x76, None, 0,
865    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
866    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
867  { "jnbe", 1, 0x77, None, 0,
868    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
869    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
870  { "ja", 1, 0x77, None, 0,
871    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
872    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
873  { "js", 1, 0x78, None, 0,
874    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
875    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
876  { "jns", 1, 0x79, None, 0,
877    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
878    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
879  { "jp", 1, 0x7a, None, 0,
880    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
881    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
882  { "jpe", 1, 0x7a, None, 0,
883    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
884    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
885  { "jnp", 1, 0x7b, None, 0,
886    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
887    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
888  { "jpo", 1, 0x7b, None, 0,
889    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
890    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
891  { "jl", 1, 0x7c, None, 0,
892    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
893    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
894  { "jnge", 1, 0x7c, None, 0,
895    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
896    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
897  { "jnl", 1, 0x7d, None, 0,
898    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
899    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
900  { "jge", 1, 0x7d, None, 0,
901    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
902    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
903  { "jle", 1, 0x7e, None, 0,
904    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
905    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
906  { "jng", 1, 0x7e, None, 0,
907    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
908    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
909  { "jnle", 1, 0x7f, None, 0,
910    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
911    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
912  { "jg", 1, 0x7f, None, 0,
913    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
914    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
915  { "jcxz", 1, 0xe3, None, CpuNo64,
916    JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
917    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
918  { "jecxz", 1, 0xe3, None, CpuNo64,
919    JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
920    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
921  { "jecxz", 1, 0x67e3, None, Cpu64,
922    JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
923    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
924  { "jrcxz", 1, 0xe3, None, Cpu64,
925    JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
926    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
927  { "loop", 1, 0xe2, None, CpuNo64,
928    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
929    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
930  { "loop", 1, 0xe2, None, Cpu64,
931    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
932    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
933  { "loopz", 1, 0xe1, None, CpuNo64,
934    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
935    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
936  { "loopz", 1, 0xe1, None, Cpu64,
937    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
938    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
939  { "loope", 1, 0xe1, None, CpuNo64,
940    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
941    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
942  { "loope", 1, 0xe1, None, Cpu64,
943    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
944    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
945  { "loopnz", 1, 0xe0, None, CpuNo64,
946    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
947    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
948  { "loopnz", 1, 0xe0, None, Cpu64,
949    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
950    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
951  { "loopne", 1, 0xe0, None, CpuNo64,
952    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
953    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
954  { "loopne", 1, 0xe0, None, Cpu64,
955    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
956    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
957  { "seto", 1, 0xf90, 0x0, Cpu386,
958    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
959    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
960  { "setno", 1, 0xf91, 0x0, Cpu386,
961    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
962    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
963  { "setb", 1, 0xf92, 0x0, Cpu386,
964    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
965    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
966  { "setc", 1, 0xf92, 0x0, Cpu386,
967    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
968    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
969  { "setnae", 1, 0xf92, 0x0, Cpu386,
970    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
971    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
972  { "setnb", 1, 0xf93, 0x0, Cpu386,
973    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
974    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
975  { "setnc", 1, 0xf93, 0x0, Cpu386,
976    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
977    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
978  { "setae", 1, 0xf93, 0x0, Cpu386,
979    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
980    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
981  { "sete", 1, 0xf94, 0x0, Cpu386,
982    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
983    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
984  { "setz", 1, 0xf94, 0x0, Cpu386,
985    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
986    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
987  { "setne", 1, 0xf95, 0x0, Cpu386,
988    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
989    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
990  { "setnz", 1, 0xf95, 0x0, Cpu386,
991    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
992    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
993  { "setbe", 1, 0xf96, 0x0, Cpu386,
994    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
995    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
996  { "setna", 1, 0xf96, 0x0, Cpu386,
997    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
998    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
999  { "setnbe", 1, 0xf97, 0x0, Cpu386,
1000    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1001    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1002  { "seta", 1, 0xf97, 0x0, Cpu386,
1003    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1004    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1005  { "sets", 1, 0xf98, 0x0, Cpu386,
1006    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1007    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1008  { "setns", 1, 0xf99, 0x0, Cpu386,
1009    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1010    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1011  { "setp", 1, 0xf9a, 0x0, Cpu386,
1012    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1013    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1014  { "setpe", 1, 0xf9a, 0x0, Cpu386,
1015    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1016    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1017  { "setnp", 1, 0xf9b, 0x0, Cpu386,
1018    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1019    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1020  { "setpo", 1, 0xf9b, 0x0, Cpu386,
1021    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1022    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1023  { "setl", 1, 0xf9c, 0x0, Cpu386,
1024    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1025    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1026  { "setnge", 1, 0xf9c, 0x0, Cpu386,
1027    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1028    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1029  { "setnl", 1, 0xf9d, 0x0, Cpu386,
1030    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1031    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1032  { "setge", 1, 0xf9d, 0x0, Cpu386,
1033    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1034    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1035  { "setle", 1, 0xf9e, 0x0, Cpu386,
1036    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1037    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1038  { "setng", 1, 0xf9e, 0x0, Cpu386,
1039    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1040    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1041  { "setnle", 1, 0xf9f, 0x0, Cpu386,
1042    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1043    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1044  { "setg", 1, 0xf9f, 0x0, Cpu386,
1045    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1046    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1047  { "cmps", 0, 0xa6, None, 0,
1048    W|No_sSuf|No_xSuf|IsString,
1049    { 0 } },
1050  { "cmps", 2, 0xa6, None, 0,
1051    W|No_sSuf|No_xSuf|IsString,
1052    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1053      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1054  { "scmp", 0, 0xa6, None, 0,
1055    W|No_sSuf|No_xSuf|IsString,
1056    { 0 } },
1057  { "scmp", 2, 0xa6, None, 0,
1058    W|No_sSuf|No_xSuf|IsString,
1059    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1060      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1061  { "ins", 0, 0x6c, None, Cpu186,
1062    W|No_sSuf|No_qSuf|No_xSuf|IsString,
1063    { 0 } },
1064  { "ins", 2, 0x6c, None, Cpu186,
1065    W|No_sSuf|No_qSuf|No_xSuf|IsString,
1066    { InOutPortReg,
1067      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1068  { "outs", 0, 0x6e, None, Cpu186,
1069    W|No_sSuf|No_qSuf|No_xSuf|IsString,
1070    { 0 } },
1071  { "outs", 2, 0x6e, None, Cpu186,
1072    W|No_sSuf|No_qSuf|No_xSuf|IsString,
1073    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1074      InOutPortReg } },
1075  { "lods", 0, 0xac, None, 0,
1076    W|No_sSuf|No_xSuf|IsString,
1077    { 0 } },
1078  { "lods", 1, 0xac, None, 0,
1079    W|No_sSuf|No_xSuf|IsString,
1080    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1081  { "lods", 2, 0xac, None, 0,
1082    W|No_sSuf|No_xSuf|IsString,
1083    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1084      Acc } },
1085  { "slod", 0, 0xac, None, 0,
1086    W|No_sSuf|No_xSuf|IsString,
1087    { 0 } },
1088  { "slod", 1, 0xac, None, 0,
1089    W|No_sSuf|No_xSuf|IsString,
1090    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1091  { "slod", 2, 0xac, None, 0,
1092    W|No_sSuf|No_xSuf|IsString,
1093    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1094      Acc } },
1095  { "movs", 0, 0xa4, None, 0,
1096    W|No_sSuf|No_xSuf|IsString,
1097    { 0 } },
1098  { "movs", 2, 0xa4, None, 0,
1099    W|No_sSuf|No_xSuf|IsString,
1100    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1101      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1102  { "smov", 0, 0xa4, None, 0,
1103    W|No_sSuf|No_xSuf|IsString,
1104    { 0 } },
1105  { "smov", 2, 0xa4, None, 0,
1106    W|No_sSuf|No_xSuf|IsString,
1107    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1108      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1109  { "scas", 0, 0xae, None, 0,
1110    W|No_sSuf|No_xSuf|IsString,
1111    { 0 } },
1112  { "scas", 1, 0xae, None, 0,
1113    W|No_sSuf|No_xSuf|IsString,
1114    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1115  { "scas", 2, 0xae, None, 0,
1116    W|No_sSuf|No_xSuf|IsString,
1117    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1118      Acc } },
1119  { "ssca", 0, 0xae, None, 0,
1120    W|No_sSuf|No_xSuf|IsString,
1121    { 0 } },
1122  { "ssca", 1, 0xae, None, 0,
1123    W|No_sSuf|No_xSuf|IsString,
1124    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1125  { "ssca", 2, 0xae, None, 0,
1126    W|No_sSuf|No_xSuf|IsString,
1127    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1128      Acc } },
1129  { "stos", 0, 0xaa, None, 0,
1130    W|No_sSuf|No_xSuf|IsString,
1131    { 0 } },
1132  { "stos", 1, 0xaa, None, 0,
1133    W|No_sSuf|No_xSuf|IsString,
1134    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1135  { "stos", 2, 0xaa, None, 0,
1136    W|No_sSuf|No_xSuf|IsString,
1137    { Acc,
1138      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1139  { "ssto", 0, 0xaa, None, 0,
1140    W|No_sSuf|No_xSuf|IsString,
1141    { 0 } },
1142  { "ssto", 1, 0xaa, None, 0,
1143    W|No_sSuf|No_xSuf|IsString,
1144    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1145  { "ssto", 2, 0xaa, None, 0,
1146    W|No_sSuf|No_xSuf|IsString,
1147    { Acc,
1148      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1149  { "xlat", 0, 0xd7, None, 0,
1150    No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
1151    { 0 } },
1152  { "xlat", 1, 0xd7, None, 0,
1153    No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
1154    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1155  { "bsf", 2, 0xfbc, None, Cpu386,
1156    Modrm|No_bSuf|No_sSuf|No_xSuf,
1157    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1158      Reg16|Reg32|Reg64 } },
1159  { "bsr", 2, 0xfbd, None, Cpu386,
1160    Modrm|No_bSuf|No_sSuf|No_xSuf,
1161    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1162      Reg16|Reg32|Reg64 } },
1163  { "bt", 2, 0xfa3, None, Cpu386,
1164    Modrm|No_bSuf|No_sSuf|No_xSuf,
1165    { Reg16|Reg32|Reg64,
1166      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1167  { "bt", 2, 0xfba, 0x4, Cpu386,
1168    Modrm|No_bSuf|No_sSuf|No_xSuf,
1169    { Imm8,
1170      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1171  { "btc", 2, 0xfbb, None, Cpu386,
1172    Modrm|No_bSuf|No_sSuf|No_xSuf,
1173    { Reg16|Reg32|Reg64,
1174      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1175  { "btc", 2, 0xfba, 0x7, Cpu386,
1176    Modrm|No_bSuf|No_sSuf|No_xSuf,
1177    { Imm8,
1178      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1179  { "btr", 2, 0xfb3, None, Cpu386,
1180    Modrm|No_bSuf|No_sSuf|No_xSuf,
1181    { Reg16|Reg32|Reg64,
1182      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1183  { "btr", 2, 0xfba, 0x6, Cpu386,
1184    Modrm|No_bSuf|No_sSuf|No_xSuf,
1185    { Imm8,
1186      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1187  { "bts", 2, 0xfab, None, Cpu386,
1188    Modrm|No_bSuf|No_sSuf|No_xSuf,
1189    { Reg16|Reg32|Reg64,
1190      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1191  { "bts", 2, 0xfba, 0x5, Cpu386,
1192    Modrm|No_bSuf|No_sSuf|No_xSuf,
1193    { Imm8,
1194      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1195  { "int", 1, 0xcd, None, 0,
1196    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1197    { Imm8 } },
1198  { "int3", 0, 0xcc, None, 0,
1199    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1200    { 0 } },
1201  { "into", 0, 0xce, None, CpuNo64,
1202    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1203    { 0 } },
1204  { "iret", 0, 0xcf, None, 0,
1205    DefaultSize|No_bSuf|No_sSuf|No_xSuf,
1206    { 0 } },
1207  { "rsm", 0, 0xfaa, None, Cpu386,
1208    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1209    { 0 } },
1210  { "bound", 2, 0x62, None, Cpu186|CpuNo64,
1211    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1212    { Reg16|Reg32|Reg64,
1213      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1214  { "hlt", 0, 0xf4, None, 0,
1215    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1216    { 0 } },
1217  { "nop", 1, 0xf1f, 0x0, Cpu686,
1218    Modrm|No_bSuf|No_sSuf|No_xSuf,
1219    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1220  { "nop", 0, 0x90, None, 0,
1221    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1222    { 0 } },
1223  { "arpl", 2, 0x63, None, Cpu286|CpuNo64,
1224    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1225    { Reg16,
1226      Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1227  { "lar", 2, 0xf02, None, Cpu286,
1228    Modrm|No_bSuf|No_sSuf|No_xSuf,
1229    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1230      Reg16|Reg32|Reg64 } },
1231  { "lgdt", 1, 0xf01, 0x2, Cpu286|CpuNo64,
1232    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1233    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1234  { "lgdt", 1, 0xf01, 0x2, Cpu64,
1235    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1236    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1237  { "lidt", 1, 0xf01, 0x3, Cpu286|CpuNo64,
1238    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1239    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1240  { "lidt", 1, 0xf01, 0x3, Cpu64,
1241    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1242    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1243  { "lldt", 1, 0xf00, 0x2, Cpu286,
1244    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1245    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1246  { "lmsw", 1, 0xf01, 0x6, Cpu286,
1247    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1248    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1249  { "lsl", 2, 0xf03, None, Cpu286,
1250    Modrm|No_bSuf|No_sSuf|No_xSuf,
1251    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1252      Reg16|Reg32|Reg64 } },
1253  { "ltr", 1, 0xf00, 0x3, Cpu286,
1254    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1255    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1256  { "sgdt", 1, 0xf01, 0x0, Cpu286|CpuNo64,
1257    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1258    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1259  { "sgdt", 1, 0xf01, 0x0, Cpu64,
1260    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1261    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1262  { "sidt", 1, 0xf01, 0x1, Cpu286|CpuNo64,
1263    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1264    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1265  { "sidt", 1, 0xf01, 0x1, Cpu64,
1266    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1267    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1268  { "sldt", 1, 0xf00, 0x0, Cpu286,
1269    Modrm|No_bSuf|No_sSuf|No_xSuf,
1270    { Reg16|Reg32|Reg64 } },
1271  { "sldt", 1, 0xf00, 0x0, Cpu286,
1272    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1273    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1274  { "smsw", 1, 0xf01, 0x4, Cpu286,
1275    Modrm|No_bSuf|No_sSuf|No_xSuf,
1276    { Reg16|Reg32|Reg64 } },
1277  { "smsw", 1, 0xf01, 0x4, Cpu286,
1278    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1279    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1280  { "str", 1, 0xf00, 0x1, Cpu286,
1281    Modrm|No_bSuf|No_sSuf|No_xSuf,
1282    { Reg16|Reg32|Reg64 } },
1283  { "str", 1, 0xf00, 0x1, Cpu286,
1284    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1285    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1286  { "verr", 1, 0xf00, 0x4, Cpu286,
1287    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1288    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1289  { "verw", 1, 0xf00, 0x5, Cpu286,
1290    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1291    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1292  { "fld", 1, 0xd9c0, None, 0,
1293    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1294    { FloatReg } },
1295  { "fld", 1, 0xd9, 0x0, 0,
1296    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1297    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1298  { "fld", 1, 0xd9c0, None, 0,
1299    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1300    { FloatReg } },
1301  { "fld", 1, 0xdb, 0x5, 0,
1302    Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1303    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1304  { "fild", 1, 0xdf, 0x0, 0,
1305    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1306    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1307  { "fild", 1, 0xdf, 0x5, 0,
1308    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1309    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1310  { "fildll", 1, 0xdf, 0x5, 0,
1311    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1312    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1313  { "fldt", 1, 0xdb, 0x5, 0,
1314    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1315    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1316  { "fbld", 1, 0xdf, 0x4, 0,
1317    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1318    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1319  { "fst", 1, 0xddd0, None, 0,
1320    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1321    { FloatReg } },
1322  { "fst", 1, 0xd9, 0x2, 0,
1323    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1324    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1325  { "fst", 1, 0xddd0, None, 0,
1326    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1327    { FloatReg } },
1328  { "fist", 1, 0xdf, 0x2, 0,
1329    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1330    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1331  { "fstp", 1, 0xddd8, None, 0,
1332    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1333    { FloatReg } },
1334  { "fstp", 1, 0xd9, 0x3, 0,
1335    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1336    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1337  { "fstp", 1, 0xddd8, None, 0,
1338    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1339    { FloatReg } },
1340  { "fstp", 1, 0xdb, 0x7, 0,
1341    Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1342    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1343  { "fistp", 1, 0xdf, 0x3, 0,
1344    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1345    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1346  { "fistp", 1, 0xdf, 0x7, 0,
1347    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1348    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1349  { "fistpll", 1, 0xdf, 0x7, 0,
1350    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1351    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1352  { "fstpt", 1, 0xdb, 0x7, 0,
1353    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1354    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1355  { "fbstp", 1, 0xdf, 0x6, 0,
1356    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1357    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1358  { "fxch", 1, 0xd9c8, None, 0,
1359    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1360    { FloatReg } },
1361  { "fxch", 0, 0xd9c9, None, 0,
1362    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1363    { 0 } },
1364  { "fcom", 1, 0xd8d0, None, 0,
1365    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1366    { FloatReg } },
1367  { "fcom", 0, 0xd8d1, None, 0,
1368    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1369    { 0 } },
1370  { "fcom", 1, 0xd8, 0x2, 0,
1371    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1372    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1373  { "fcom", 1, 0xd8d0, None, 0,
1374    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1375    { FloatReg } },
1376  { "ficom", 1, 0xde, 0x2, 0,
1377    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1378    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1379  { "fcomp", 1, 0xd8d8, None, 0,
1380    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1381    { FloatReg } },
1382  { "fcomp", 0, 0xd8d9, None, 0,
1383    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1384    { 0 } },
1385  { "fcomp", 1, 0xd8, 0x3, 0,
1386    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1387    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1388  { "fcomp", 1, 0xd8d8, None, 0,
1389    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1390    { FloatReg } },
1391  { "ficomp", 1, 0xde, 0x3, 0,
1392    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1393    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1394  { "fcompp", 0, 0xded9, None, 0,
1395    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1396    { 0 } },
1397  { "fucom", 1, 0xdde0, None, Cpu286,
1398    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1399    { FloatReg } },
1400  { "fucom", 0, 0xdde1, None, Cpu286,
1401    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1402    { 0 } },
1403  { "fucomp", 1, 0xdde8, None, Cpu286,
1404    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1405    { FloatReg } },
1406  { "fucomp", 0, 0xdde9, None, Cpu286,
1407    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1408    { 0 } },
1409  { "fucompp", 0, 0xdae9, None, Cpu286,
1410    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1411    { 0 } },
1412  { "ftst", 0, 0xd9e4, None, 0,
1413    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1414    { 0 } },
1415  { "fxam", 0, 0xd9e5, None, 0,
1416    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1417    { 0 } },
1418  { "fld1", 0, 0xd9e8, None, 0,
1419    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1420    { 0 } },
1421  { "fldl2t", 0, 0xd9e9, None, 0,
1422    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1423    { 0 } },
1424  { "fldl2e", 0, 0xd9ea, None, 0,
1425    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1426    { 0 } },
1427  { "fldpi", 0, 0xd9eb, None, 0,
1428    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1429    { 0 } },
1430  { "fldlg2", 0, 0xd9ec, None, 0,
1431    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1432    { 0 } },
1433  { "fldln2", 0, 0xd9ed, None, 0,
1434    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1435    { 0 } },
1436  { "fldz", 0, 0xd9ee, None, 0,
1437    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1438    { 0 } },
1439  { "fadd", 2, 0xd8c0, None, 0,
1440    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1441    { FloatReg,
1442      FloatAcc } },
1443  { "fadd", 1, 0xd8c0, None, 0,
1444    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1445    { FloatReg } },
1446#if SYSV386_COMPAT
1447  { "fadd", 0, 0xdec1, None, 0,
1448    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1449    { 0 } },
1450#endif
1451  { "fadd", 1, 0xd8, 0x0, 0,
1452    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1453    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1454  { "fiadd", 1, 0xde, 0x0, 0,
1455    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1456    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1457  { "faddp", 2, 0xdec0, None, 0,
1458    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1459    { FloatAcc,
1460      FloatReg } },
1461  { "faddp", 1, 0xdec0, None, 0,
1462    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1463    { FloatReg } },
1464  { "faddp", 0, 0xdec1, None, 0,
1465    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1466    { 0 } },
1467  { "faddp", 2, 0xdec0, None, 0,
1468    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1469    { FloatReg,
1470      FloatAcc } },
1471  { "fsub", 1, 0xd8e0, None, 0,
1472    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1473    { FloatReg } },
1474#if SYSV386_COMPAT
1475  { "fsub", 2, 0xd8e0, None, 0,
1476    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1477    { FloatReg,
1478      FloatAcc } },
1479  { "fsub", 0, 0xdee1, None, 0,
1480    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1481    { 0 } },
1482#else
1483  { "fsub", 2, 0xd8e0, None, 0,
1484    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1485    { FloatReg,
1486      FloatAcc } },
1487#endif
1488  { "fsub", 1, 0xd8, 0x4, 0,
1489    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1490    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1491  { "fisub", 1, 0xde, 0x4, 0,
1492    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1493    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1494#if SYSV386_COMPAT
1495  { "fsubp", 2, 0xdee0, None, 0,
1496    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1497    { FloatAcc,
1498      FloatReg } },
1499  { "fsubp", 1, 0xdee0, None, 0,
1500    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1501    { FloatReg } },
1502  { "fsubp", 0, 0xdee1, None, 0,
1503    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1504    { 0 } },
1505#if OLDGCC_COMPAT
1506  { "fsubp", 2, 0xdee0, None, 0,
1507    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1508    { FloatReg,
1509      FloatAcc } },
1510#endif
1511#else
1512  { "fsubp", 2, 0xdee8, None, 0,
1513    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1514    { FloatAcc,
1515      FloatReg } },
1516  { "fsubp", 1, 0xdee8, None, 0,
1517    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1518    { FloatReg } },
1519  { "fsubp", 0, 0xdee9, None, 0,
1520    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1521    { 0 } },
1522#endif
1523  { "fsubr", 1, 0xd8e8, None, 0,
1524    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1525    { FloatReg } },
1526#if SYSV386_COMPAT
1527  { "fsubr", 2, 0xd8e8, None, 0,
1528    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1529    { FloatReg,
1530      FloatAcc } },
1531  { "fsubr", 0, 0xdee9, None, 0,
1532    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1533    { 0 } },
1534#else
1535  { "fsubr", 2, 0xd8e8, None, 0,
1536    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1537    { FloatReg,
1538      FloatAcc } },
1539#endif
1540  { "fsubr", 1, 0xd8, 0x5, 0,
1541    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1542    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1543  { "fisubr", 1, 0xde, 0x5, 0,
1544    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1545    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1546#if SYSV386_COMPAT
1547  { "fsubrp", 2, 0xdee8, None, 0,
1548    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1549    { FloatAcc,
1550      FloatReg } },
1551  { "fsubrp", 1, 0xdee8, None, 0,
1552    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1553    { FloatReg } },
1554  { "fsubrp", 0, 0xdee9, None, 0,
1555    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1556    { 0 } },
1557#if OLDGCC_COMPAT
1558  { "fsubrp", 2, 0xdee8, None, 0,
1559    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1560    { FloatReg,
1561      FloatAcc } },
1562#endif
1563#else
1564  { "fsubrp", 2, 0xdee0, None, 0,
1565    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1566    { FloatAcc,
1567      FloatReg } },
1568  { "fsubrp", 1, 0xdee0, None, 0,
1569    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1570    { FloatReg } },
1571  { "fsubrp", 0, 0xdee1, None, 0,
1572    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1573    { 0 } },
1574#endif
1575  { "fmul", 2, 0xd8c8, None, 0,
1576    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1577    { FloatReg,
1578      FloatAcc } },
1579  { "fmul", 1, 0xd8c8, None, 0,
1580    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1581    { FloatReg } },
1582#if SYSV386_COMPAT
1583  { "fmul", 0, 0xdec9, None, 0,
1584    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1585    { 0 } },
1586#endif
1587  { "fmul", 1, 0xd8, 0x1, 0,
1588    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1589    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1590  { "fimul", 1, 0xde, 0x1, 0,
1591    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1592    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1593  { "fmulp", 2, 0xdec8, None, 0,
1594    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1595    { FloatAcc,
1596      FloatReg } },
1597  { "fmulp", 1, 0xdec8, None, 0,
1598    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1599    { FloatReg } },
1600  { "fmulp", 0, 0xdec9, None, 0,
1601    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1602    { 0 } },
1603  { "fmulp", 2, 0xdec8, None, 0,
1604    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1605    { FloatReg,
1606      FloatAcc } },
1607  { "fdiv", 1, 0xd8f0, None, 0,
1608    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1609    { FloatReg } },
1610#if SYSV386_COMPAT
1611  { "fdiv", 2, 0xd8f0, None, 0,
1612    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1613    { FloatReg,
1614      FloatAcc } },
1615  { "fdiv", 0, 0xdef1, None, 0,
1616    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1617    { 0 } },
1618#else
1619  { "fdiv", 2, 0xd8f0, None, 0,
1620    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1621    { FloatReg,
1622      FloatAcc } },
1623#endif
1624  { "fdiv", 1, 0xd8, 0x6, 0,
1625    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1626    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1627  { "fidiv", 1, 0xde, 0x6, 0,
1628    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1629    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1630#if SYSV386_COMPAT
1631  { "fdivp", 2, 0xdef0, None, 0,
1632    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1633    { FloatAcc,
1634      FloatReg } },
1635  { "fdivp", 1, 0xdef0, None, 0,
1636    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1637    { FloatReg } },
1638  { "fdivp", 0, 0xdef1, None, 0,
1639    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1640    { 0 } },
1641#if OLDGCC_COMPAT
1642  { "fdivp", 2, 0xdef0, None, 0,
1643    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1644    { FloatReg,
1645      FloatAcc } },
1646#endif
1647#else
1648  { "fdivp", 2, 0xdef8, None, 0,
1649    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1650    { FloatAcc,
1651      FloatReg } },
1652  { "fdivp", 1, 0xdef8, None, 0,
1653    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1654    { FloatReg } },
1655  { "fdivp", 0, 0xdef9, None, 0,
1656    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1657    { 0 } },
1658#endif
1659  { "fdivr", 1, 0xd8f8, None, 0,
1660    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1661    { FloatReg } },
1662#if SYSV386_COMPAT
1663  { "fdivr", 2, 0xd8f8, None, 0,
1664    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1665    { FloatReg,
1666      FloatAcc } },
1667  { "fdivr", 0, 0xdef9, None, 0,
1668    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1669    { 0 } },
1670#else
1671  { "fdivr", 2, 0xd8f8, None, 0,
1672    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1673    { FloatReg,
1674      FloatAcc } },
1675#endif
1676  { "fdivr", 1, 0xd8, 0x7, 0,
1677    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1678    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1679  { "fidivr", 1, 0xde, 0x7, 0,
1680    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1681    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1682#if SYSV386_COMPAT
1683  { "fdivrp", 2, 0xdef8, None, 0,
1684    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1685    { FloatAcc,
1686      FloatReg } },
1687  { "fdivrp", 1, 0xdef8, None, 0,
1688    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1689    { FloatReg } },
1690  { "fdivrp", 0, 0xdef9, None, 0,
1691    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1692    { 0 } },
1693#if OLDGCC_COMPAT
1694  { "fdivrp", 2, 0xdef8, None, 0,
1695    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1696    { FloatReg,
1697      FloatAcc } },
1698#endif
1699#else
1700  { "fdivrp", 2, 0xdef0, None, 0,
1701    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1702    { FloatAcc,
1703      FloatReg } },
1704  { "fdivrp", 1, 0xdef0, None, 0,
1705    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1706    { FloatReg } },
1707  { "fdivrp", 0, 0xdef1, None, 0,
1708    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1709    { 0 } },
1710#endif
1711  { "f2xm1", 0, 0xd9f0, None, 0,
1712    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1713    { 0 } },
1714  { "fyl2x", 0, 0xd9f1, None, 0,
1715    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1716    { 0 } },
1717  { "fptan", 0, 0xd9f2, None, 0,
1718    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1719    { 0 } },
1720  { "fpatan", 0, 0xd9f3, None, 0,
1721    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1722    { 0 } },
1723  { "fxtract", 0, 0xd9f4, None, 0,
1724    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1725    { 0 } },
1726  { "fprem1", 0, 0xd9f5, None, Cpu286,
1727    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1728    { 0 } },
1729  { "fdecstp", 0, 0xd9f6, None, 0,
1730    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1731    { 0 } },
1732  { "fincstp", 0, 0xd9f7, None, 0,
1733    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1734    { 0 } },
1735  { "fprem", 0, 0xd9f8, None, 0,
1736    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1737    { 0 } },
1738  { "fyl2xp1", 0, 0xd9f9, None, 0,
1739    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1740    { 0 } },
1741  { "fsqrt", 0, 0xd9fa, None, 0,
1742    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1743    { 0 } },
1744  { "fsincos", 0, 0xd9fb, None, Cpu286,
1745    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1746    { 0 } },
1747  { "frndint", 0, 0xd9fc, None, 0,
1748    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1749    { 0 } },
1750  { "fscale", 0, 0xd9fd, None, 0,
1751    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1752    { 0 } },
1753  { "fsin", 0, 0xd9fe, None, Cpu286,
1754    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1755    { 0 } },
1756  { "fcos", 0, 0xd9ff, None, Cpu286,
1757    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1758    { 0 } },
1759  { "fchs", 0, 0xd9e0, None, 0,
1760    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1761    { 0 } },
1762  { "fabs", 0, 0xd9e1, None, 0,
1763    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1764    { 0 } },
1765  { "fninit", 0, 0xdbe3, None, 0,
1766    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1767    { 0 } },
1768  { "finit", 0, 0xdbe3, None, 0,
1769    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1770    { 0 } },
1771  { "fldcw", 1, 0xd9, 0x5, 0,
1772    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1773    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1774  { "fnstcw", 1, 0xd9, 0x7, 0,
1775    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1776    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1777  { "fstcw", 1, 0xd9, 0x7, 0,
1778    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1779    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1780  { "fnstsw", 1, 0xdfe0, None, 0,
1781    IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1782    { Acc } },
1783  { "fnstsw", 1, 0xdd, 0x7, 0,
1784    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1785    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1786  { "fnstsw", 0, 0xdfe0, None, 0,
1787    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1788    { 0 } },
1789  { "fstsw", 1, 0xdfe0, None, 0,
1790    IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1791    { Acc } },
1792  { "fstsw", 1, 0xdd, 0x7, 0,
1793    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1794    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1795  { "fstsw", 0, 0xdfe0, None, 0,
1796    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1797    { 0 } },
1798  { "fnclex", 0, 0xdbe2, None, 0,
1799    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1800    { 0 } },
1801  { "fclex", 0, 0xdbe2, None, 0,
1802    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1803    { 0 } },
1804  { "fnstenv", 1, 0xd9, 0x6, 0,
1805    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1806    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1807  { "fstenv", 1, 0xd9, 0x6, 0,
1808    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait,
1809    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1810  { "fldenv", 1, 0xd9, 0x4, 0,
1811    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1812    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1813  { "fnsave", 1, 0xdd, 0x6, 0,
1814    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1815    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1816  { "fsave", 1, 0xdd, 0x6, 0,
1817    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait,
1818    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1819  { "frstor", 1, 0xdd, 0x4, 0,
1820    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1821    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1822  { "ffree", 1, 0xddc0, None, 0,
1823    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1824    { FloatReg } },
1825  { "ffreep", 1, 0xdfc0, None, Cpu686,
1826    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1827    { FloatReg } },
1828  { "fnop", 0, 0xd9d0, None, 0,
1829    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1830    { 0 } },
1831  { "fwait", 0, 0x9b, None, 0,
1832    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1833    { 0 } },
1834  { "addr16", 0, 0x67, None, Cpu386|CpuNo64,
1835    Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1836    { 0 } },
1837  { "addr32", 0, 0x67, None, Cpu386,
1838    Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1839    { 0 } },
1840  { "aword", 0, 0x67, None, Cpu386|CpuNo64,
1841    Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1842    { 0 } },
1843  { "adword", 0, 0x67, None, Cpu386,
1844    Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1845    { 0 } },
1846  { "data16", 0, 0x66, None, Cpu386,
1847    Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1848    { 0 } },
1849  { "data32", 0, 0x66, None, Cpu386|CpuNo64,
1850    Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1851    { 0 } },
1852  { "word", 0, 0x66, None, Cpu386,
1853    Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1854    { 0 } },
1855  { "dword", 0, 0x66, None, Cpu386|CpuNo64,
1856    Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1857    { 0 } },
1858  { "lock", 0, 0xf0, None, 0,
1859    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1860    { 0 } },
1861  { "wait", 0, 0x9b, None, 0,
1862    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1863    { 0 } },
1864  { "cs", 0, 0x2e, None, 0,
1865    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1866    { 0 } },
1867  { "ds", 0, 0x3e, None, 0,
1868    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1869    { 0 } },
1870  { "es", 0, 0x26, None, CpuNo64,
1871    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1872    { 0 } },
1873  { "fs", 0, 0x64, None, Cpu386,
1874    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1875    { 0 } },
1876  { "gs", 0, 0x65, None, Cpu386,
1877    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1878    { 0 } },
1879  { "ss", 0, 0x36, None, CpuNo64,
1880    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1881    { 0 } },
1882  { "rep", 0, 0xf3, None, 0,
1883    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1884    { 0 } },
1885  { "repe", 0, 0xf3, None, 0,
1886    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1887    { 0 } },
1888  { "repz", 0, 0xf3, None, 0,
1889    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1890    { 0 } },
1891  { "repne", 0, 0xf2, None, 0,
1892    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1893    { 0 } },
1894  { "repnz", 0, 0xf2, None, 0,
1895    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1896    { 0 } },
1897  { "ht", 0, 0x3e, None, 0,
1898    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1899    { 0 } },
1900  { "hnt", 0, 0x2e, None, 0,
1901    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1902    { 0 } },
1903  { "rex", 0, 0x40, None, Cpu64,
1904    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1905    { 0 } },
1906  { "rexz", 0, 0x41, None, Cpu64,
1907    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1908    { 0 } },
1909  { "rexy", 0, 0x42, None, Cpu64,
1910    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1911    { 0 } },
1912  { "rexyz", 0, 0x43, None, Cpu64,
1913    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1914    { 0 } },
1915  { "rexx", 0, 0x44, None, Cpu64,
1916    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1917    { 0 } },
1918  { "rexxz", 0, 0x45, None, Cpu64,
1919    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1920    { 0 } },
1921  { "rexxy", 0, 0x46, None, Cpu64,
1922    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1923    { 0 } },
1924  { "rexxyz", 0, 0x47, None, Cpu64,
1925    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1926    { 0 } },
1927  { "rex64", 0, 0x48, None, Cpu64,
1928    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1929    { 0 } },
1930  { "rex64z", 0, 0x49, None, Cpu64,
1931    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1932    { 0 } },
1933  { "rex64y", 0, 0x4a, None, Cpu64,
1934    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1935    { 0 } },
1936  { "rex64yz", 0, 0x4b, None, Cpu64,
1937    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1938    { 0 } },
1939  { "rex64x", 0, 0x4c, None, Cpu64,
1940    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1941    { 0 } },
1942  { "rex64xz", 0, 0x4d, None, Cpu64,
1943    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1944    { 0 } },
1945  { "rex64xy", 0, 0x4e, None, Cpu64,
1946    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1947    { 0 } },
1948  { "rex64xyz", 0, 0x4f, None, Cpu64,
1949    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1950    { 0 } },
1951  { "rex.b", 0, 0x41, None, Cpu64,
1952    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1953    { 0 } },
1954  { "rex.x", 0, 0x42, None, Cpu64,
1955    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1956    { 0 } },
1957  { "rex.xb", 0, 0x43, None, Cpu64,
1958    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1959    { 0 } },
1960  { "rex.r", 0, 0x44, None, Cpu64,
1961    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1962    { 0 } },
1963  { "rex.rb", 0, 0x45, None, Cpu64,
1964    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1965    { 0 } },
1966  { "rex.rx", 0, 0x46, None, Cpu64,
1967    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1968    { 0 } },
1969  { "rex.rxb", 0, 0x47, None, Cpu64,
1970    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1971    { 0 } },
1972  { "rex.w", 0, 0x48, None, Cpu64,
1973    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1974    { 0 } },
1975  { "rex.wb", 0, 0x49, None, Cpu64,
1976    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1977    { 0 } },
1978  { "rex.wx", 0, 0x4a, None, Cpu64,
1979    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1980    { 0 } },
1981  { "rex.wxb", 0, 0x4b, None, Cpu64,
1982    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1983    { 0 } },
1984  { "rex.wr", 0, 0x4c, None, Cpu64,
1985    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1986    { 0 } },
1987  { "rex.wrb", 0, 0x4d, None, Cpu64,
1988    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1989    { 0 } },
1990  { "rex.wrx", 0, 0x4e, None, Cpu64,
1991    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1992    { 0 } },
1993  { "rex.wrxb", 0, 0x4f, None, Cpu64,
1994    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1995    { 0 } },
1996  { "bswap", 1, 0xfc8, None, Cpu486,
1997    ShortForm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
1998    { Reg32|Reg64 } },
1999  { "xadd", 2, 0xfc0, None, Cpu486,
2000    W|Modrm|No_sSuf|No_xSuf,
2001    { Reg8|Reg16|Reg32|Reg64,
2002      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2003  { "cmpxchg", 2, 0xfb0, None, Cpu486,
2004    W|Modrm|No_sSuf|No_xSuf,
2005    { Reg8|Reg16|Reg32|Reg64,
2006      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2007  { "invd", 0, 0xf08, None, Cpu486,
2008    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2009    { 0 } },
2010  { "wbinvd", 0, 0xf09, None, Cpu486,
2011    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2012    { 0 } },
2013  { "invlpg", 1, 0xf01, 0x7, Cpu486,
2014    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2015    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2016  { "cpuid", 0, 0xfa2, None, Cpu486,
2017    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2018    { 0 } },
2019  { "wrmsr", 0, 0xf30, None, Cpu586,
2020    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2021    { 0 } },
2022  { "rdtsc", 0, 0xf31, None, Cpu586,
2023    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2024    { 0 } },
2025  { "rdmsr", 0, 0xf32, None, Cpu586,
2026    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2027    { 0 } },
2028  { "cmpxchg8b", 1, 0xfc7, 0x1, Cpu586,
2029    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
2030    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2031  { "sysenter", 0, 0xf34, None, Cpu686,
2032    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2033    { 0 } },
2034  { "sysexit", 0, 0xf35, None, Cpu686,
2035    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2036    { 0 } },
2037  { "fxsave", 1, 0xfae, 0x0, Cpu686,
2038    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
2039    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2040  { "fxrstor", 1, 0xfae, 0x1, Cpu686,
2041    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
2042    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2043  { "rdpmc", 0, 0xf33, None, Cpu686,
2044    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2045    { 0 } },
2046  { "ud2", 0, 0xf0b, None, Cpu686,
2047    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2048    { 0 } },
2049  { "ud2a", 0, 0xf0b, None, Cpu686,
2050    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2051    { 0 } },
2052  { "ud2b", 0, 0xfb9, None, Cpu686,
2053    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2054    { 0 } },
2055  { "cmovo", 2, 0xf40, None, Cpu686,
2056    Modrm|No_bSuf|No_sSuf|No_xSuf,
2057    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2058      Reg16|Reg32|Reg64 } },
2059  { "cmovno", 2, 0xf41, None, Cpu686,
2060    Modrm|No_bSuf|No_sSuf|No_xSuf,
2061    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2062      Reg16|Reg32|Reg64 } },
2063  { "cmovb", 2, 0xf42, None, Cpu686,
2064    Modrm|No_bSuf|No_sSuf|No_xSuf,
2065    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2066      Reg16|Reg32|Reg64 } },
2067  { "cmovc", 2, 0xf42, None, Cpu686,
2068    Modrm|No_bSuf|No_sSuf|No_xSuf,
2069    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2070      Reg16|Reg32|Reg64 } },
2071  { "cmovnae", 2, 0xf42, None, Cpu686,
2072    Modrm|No_bSuf|No_sSuf|No_xSuf,
2073    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2074      Reg16|Reg32|Reg64 } },
2075  { "cmovae", 2, 0xf43, None, Cpu686,
2076    Modrm|No_bSuf|No_sSuf|No_xSuf,
2077    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2078      Reg16|Reg32|Reg64 } },
2079  { "cmovnc", 2, 0xf43, None, Cpu686,
2080    Modrm|No_bSuf|No_sSuf|No_xSuf,
2081    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2082      Reg16|Reg32|Reg64 } },
2083  { "cmovnb", 2, 0xf43, None, Cpu686,
2084    Modrm|No_bSuf|No_sSuf|No_xSuf,
2085    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2086      Reg16|Reg32|Reg64 } },
2087  { "cmove", 2, 0xf44, None, Cpu686,
2088    Modrm|No_bSuf|No_sSuf|No_xSuf,
2089    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2090      Reg16|Reg32|Reg64 } },
2091  { "cmovz", 2, 0xf44, None, Cpu686,
2092    Modrm|No_bSuf|No_sSuf|No_xSuf,
2093    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2094      Reg16|Reg32|Reg64 } },
2095  { "cmovne", 2, 0xf45, None, Cpu686,
2096    Modrm|No_bSuf|No_sSuf|No_xSuf,
2097    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2098      Reg16|Reg32|Reg64 } },
2099  { "cmovnz", 2, 0xf45, None, Cpu686,
2100    Modrm|No_bSuf|No_sSuf|No_xSuf,
2101    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2102      Reg16|Reg32|Reg64 } },
2103  { "cmovbe", 2, 0xf46, None, Cpu686,
2104    Modrm|No_bSuf|No_sSuf|No_xSuf,
2105    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2106      Reg16|Reg32|Reg64 } },
2107  { "cmovna", 2, 0xf46, None, Cpu686,
2108    Modrm|No_bSuf|No_sSuf|No_xSuf,
2109    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2110      Reg16|Reg32|Reg64 } },
2111  { "cmova", 2, 0xf47, None, Cpu686,
2112    Modrm|No_bSuf|No_sSuf|No_xSuf,
2113    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2114      Reg16|Reg32|Reg64 } },
2115  { "cmovnbe", 2, 0xf47, None, Cpu686,
2116    Modrm|No_bSuf|No_sSuf|No_xSuf,
2117    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2118      Reg16|Reg32|Reg64 } },
2119  { "cmovs", 2, 0xf48, None, Cpu686,
2120    Modrm|No_bSuf|No_sSuf|No_xSuf,
2121    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2122      Reg16|Reg32|Reg64 } },
2123  { "cmovns", 2, 0xf49, None, Cpu686,
2124    Modrm|No_bSuf|No_sSuf|No_xSuf,
2125    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2126      Reg16|Reg32|Reg64 } },
2127  { "cmovp", 2, 0xf4a, None, Cpu686,
2128    Modrm|No_bSuf|No_sSuf|No_xSuf,
2129    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2130      Reg16|Reg32|Reg64 } },
2131  { "cmovnp", 2, 0xf4b, None, Cpu686,
2132    Modrm|No_bSuf|No_sSuf|No_xSuf,
2133    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2134      Reg16|Reg32|Reg64 } },
2135  { "cmovl", 2, 0xf4c, None, Cpu686,
2136    Modrm|No_bSuf|No_sSuf|No_xSuf,
2137    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2138      Reg16|Reg32|Reg64 } },
2139  { "cmovnge", 2, 0xf4c, None, Cpu686,
2140    Modrm|No_bSuf|No_sSuf|No_xSuf,
2141    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2142      Reg16|Reg32|Reg64 } },
2143  { "cmovge", 2, 0xf4d, None, Cpu686,
2144    Modrm|No_bSuf|No_sSuf|No_xSuf,
2145    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2146      Reg16|Reg32|Reg64 } },
2147  { "cmovnl", 2, 0xf4d, None, Cpu686,
2148    Modrm|No_bSuf|No_sSuf|No_xSuf,
2149    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2150      Reg16|Reg32|Reg64 } },
2151  { "cmovle", 2, 0xf4e, None, Cpu686,
2152    Modrm|No_bSuf|No_sSuf|No_xSuf,
2153    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2154      Reg16|Reg32|Reg64 } },
2155  { "cmovng", 2, 0xf4e, None, Cpu686,
2156    Modrm|No_bSuf|No_sSuf|No_xSuf,
2157    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2158      Reg16|Reg32|Reg64 } },
2159  { "cmovg", 2, 0xf4f, None, Cpu686,
2160    Modrm|No_bSuf|No_sSuf|No_xSuf,
2161    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2162      Reg16|Reg32|Reg64 } },
2163  { "cmovnle", 2, 0xf4f, None, Cpu686,
2164    Modrm|No_bSuf|No_sSuf|No_xSuf,
2165    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2166      Reg16|Reg32|Reg64 } },
2167  { "fcmovb", 2, 0xdac0, None, Cpu686,
2168    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2169    { FloatReg,
2170      FloatAcc } },
2171  { "fcmovnae", 2, 0xdac0, None, Cpu686,
2172    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2173    { FloatReg,
2174      FloatAcc } },
2175  { "fcmove", 2, 0xdac8, None, Cpu686,
2176    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2177    { FloatReg,
2178      FloatAcc } },
2179  { "fcmovbe", 2, 0xdad0, None, Cpu686,
2180    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2181    { FloatReg,
2182      FloatAcc } },
2183  { "fcmovna", 2, 0xdad0, None, Cpu686,
2184    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2185    { FloatReg,
2186      FloatAcc } },
2187  { "fcmovu", 2, 0xdad8, None, Cpu686,
2188    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2189    { FloatReg,
2190      FloatAcc } },
2191  { "fcmovae", 2, 0xdbc0, None, Cpu686,
2192    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2193    { FloatReg,
2194      FloatAcc } },
2195  { "fcmovnb", 2, 0xdbc0, None, Cpu686,
2196    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2197    { FloatReg,
2198      FloatAcc } },
2199  { "fcmovne", 2, 0xdbc8, None, Cpu686,
2200    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2201    { FloatReg,
2202      FloatAcc } },
2203  { "fcmova", 2, 0xdbd0, None, Cpu686,
2204    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2205    { FloatReg,
2206      FloatAcc } },
2207  { "fcmovnbe", 2, 0xdbd0, None, Cpu686,
2208    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2209    { FloatReg,
2210      FloatAcc } },
2211  { "fcmovnu", 2, 0xdbd8, None, Cpu686,
2212    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2213    { FloatReg,
2214      FloatAcc } },
2215  { "fcomi", 2, 0xdbf0, None, Cpu686,
2216    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2217    { FloatReg,
2218      FloatAcc } },
2219  { "fcomi", 0, 0xdbf1, None, Cpu686,
2220    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2221    { 0 } },
2222  { "fcomi", 1, 0xdbf0, None, Cpu686,
2223    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2224    { FloatReg } },
2225  { "fucomi", 2, 0xdbe8, None, Cpu686,
2226    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2227    { FloatReg,
2228      FloatAcc } },
2229  { "fucomi", 0, 0xdbe9, None, Cpu686,
2230    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2231    { 0 } },
2232  { "fucomi", 1, 0xdbe8, None, Cpu686,
2233    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2234    { FloatReg } },
2235  { "fcomip", 2, 0xdff0, None, Cpu686,
2236    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2237    { FloatReg,
2238      FloatAcc } },
2239  { "fcomip", 0, 0xdff1, None, Cpu686,
2240    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2241    { 0 } },
2242  { "fcomip", 1, 0xdff0, None, Cpu686,
2243    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2244    { FloatReg } },
2245  { "fcompi", 2, 0xdff0, None, Cpu686,
2246    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2247    { FloatReg,
2248      FloatAcc } },
2249  { "fcompi", 0, 0xdff1, None, Cpu686,
2250    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2251    { 0 } },
2252  { "fcompi", 1, 0xdff0, None, Cpu686,
2253    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2254    { FloatReg } },
2255  { "fucomip", 2, 0xdfe8, None, Cpu686,
2256    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2257    { FloatReg,
2258      FloatAcc } },
2259  { "fucomip", 0, 0xdfe9, None, Cpu686,
2260    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2261    { 0 } },
2262  { "fucomip", 1, 0xdfe8, None, Cpu686,
2263    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2264    { FloatReg } },
2265  { "fucompi", 2, 0xdfe8, None, Cpu686,
2266    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2267    { FloatReg,
2268      FloatAcc } },
2269  { "fucompi", 0, 0xdfe9, None, Cpu686,
2270    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2271    { 0 } },
2272  { "fucompi", 1, 0xdfe8, None, Cpu686,
2273    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2274    { FloatReg } },
2275  { "movnti", 2, 0xfc3, None, CpuP4,
2276    Modrm|No_bSuf|No_sSuf|No_xSuf,
2277    { Reg16|Reg32|Reg64,
2278      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2279  { "clflush", 1, 0xfae, 0x7, CpuP4,
2280    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2281    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2282  { "lfence", 0, 0xfae, 0xe8, CpuP4,
2283    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2284    { 0 } },
2285  { "mfence", 0, 0xfae, 0xf0, CpuP4,
2286    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2287    { 0 } },
2288  { "pause", 0, 0xf390, None, CpuP4,
2289    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2290    { 0 } },
2291  { "emms", 0, 0xf77, None, CpuMMX,
2292    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2293    { 0 } },
2294  { "movd", 2, 0xf6e, None, CpuMMX,
2295    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2296    { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2297      RegMMX } },
2298  { "movd", 2, 0xf7e, None, CpuMMX,
2299    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2300    { RegMMX,
2301      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2302  { "movd", 2, 0x660f6e, None, CpuSSE2,
2303    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2304    { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2305      RegXMM } },
2306  { "movd", 2, 0x660f7e, None, CpuSSE2,
2307    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2308    { RegXMM,
2309      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2310  { "movq", 2, 0xf6f, None, CpuMMX,
2311    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2312    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2313      RegMMX } },
2314  { "movq", 2, 0xf7f, None, CpuMMX,
2315    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2316    { RegMMX,
2317      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } },
2318  { "movq", 2, 0xf30f7e, None, CpuSSE2,
2319    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2320    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2321      RegXMM } },
2322  { "movq", 2, 0x660fd6, None, CpuSSE2,
2323    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2324    { RegXMM,
2325      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
2326  { "movq", 2, 0xf6e, None, Cpu64,
2327    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2328    { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2329      RegMMX } },
2330  { "movq", 2, 0xf7e, None, Cpu64,
2331    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2332    { RegMMX,
2333      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2334  { "movq", 2, 0x660f6e, None, Cpu64,
2335    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2336    { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2337      RegXMM } },
2338  { "movq", 2, 0x660f7e, None, Cpu64,
2339    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2340    { RegXMM,
2341      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2342  { "movq", 2, 0xa0, None, Cpu64,
2343    D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2344    { Disp64,
2345      Acc } },
2346  { "movq", 2, 0x88, None, Cpu64,
2347    D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2348    { Reg64,
2349      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2350  { "movq", 2, 0xc6, 0x0, Cpu64,
2351    W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2352    { Imm32S,
2353      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2354  { "movq", 2, 0xb0, None, Cpu64,
2355    W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2356    { Imm64,
2357      Reg64 } },
2358  { "movq", 2, 0x8c, None, Cpu64,
2359    Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2360    { SReg2|SReg3,
2361      Reg64|RegMem } },
2362  { "movq", 2, 0x8e, None, Cpu64,
2363    Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2364    { Reg64,
2365      SReg2|SReg3 } },
2366  { "movq", 2, 0xf20, None, Cpu64,
2367    D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2368    { Control,
2369      Reg64|RegMem } },
2370  { "movq", 2, 0xf21, None, Cpu64,
2371    D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2372    { Debug,
2373      Reg64|RegMem } },
2374  { "packssdw", 2, 0xf6b, None, CpuMMX,
2375    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2376    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2377      RegMMX } },
2378  { "packssdw", 2, 0x660f6b, None, CpuSSE2,
2379    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2380    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2381      RegXMM } },
2382  { "packsswb", 2, 0xf63, None, CpuMMX,
2383    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2384    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2385      RegMMX } },
2386  { "packsswb", 2, 0x660f63, None, CpuSSE2,
2387    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2388    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2389      RegXMM } },
2390  { "packuswb", 2, 0xf67, None, CpuMMX,
2391    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2392    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2393      RegMMX } },
2394  { "packuswb", 2, 0x660f67, None, CpuSSE2,
2395    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2396    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2397      RegXMM } },
2398  { "paddb", 2, 0xffc, None, CpuMMX,
2399    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2400    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2401      RegMMX } },
2402  { "paddb", 2, 0x660ffc, None, CpuSSE2,
2403    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2404    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2405      RegXMM } },
2406  { "paddw", 2, 0xffd, None, CpuMMX,
2407    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2408    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2409      RegMMX } },
2410  { "paddw", 2, 0x660ffd, None, CpuSSE2,
2411    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2412    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2413      RegXMM } },
2414  { "paddd", 2, 0xffe, None, CpuMMX,
2415    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2416    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2417      RegMMX } },
2418  { "paddd", 2, 0x660ffe, None, CpuSSE2,
2419    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2420    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2421      RegXMM } },
2422  { "paddq", 2, 0xfd4, None, CpuSSE2,
2423    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2424    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2425      RegMMX } },
2426  { "paddq", 2, 0x660fd4, None, CpuSSE2,
2427    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2428    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2429      RegXMM } },
2430  { "paddsb", 2, 0xfec, None, CpuMMX,
2431    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2432    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2433      RegMMX } },
2434  { "paddsb", 2, 0x660fec, None, CpuSSE2,
2435    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2436    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2437      RegXMM } },
2438  { "paddsw", 2, 0xfed, None, CpuMMX,
2439    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2440    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2441      RegMMX } },
2442  { "paddsw", 2, 0x660fed, None, CpuSSE2,
2443    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2444    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2445      RegXMM } },
2446  { "paddusb", 2, 0xfdc, None, CpuMMX,
2447    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2448    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2449      RegMMX } },
2450  { "paddusb", 2, 0x660fdc, None, CpuSSE2,
2451    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2452    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2453      RegXMM } },
2454  { "paddusw", 2, 0xfdd, None, CpuMMX,
2455    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2456    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2457      RegMMX } },
2458  { "paddusw", 2, 0x660fdd, None, CpuSSE2,
2459    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2460    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2461      RegXMM } },
2462  { "pand", 2, 0xfdb, None, CpuMMX,
2463    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2464    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2465      RegMMX } },
2466  { "pand", 2, 0x660fdb, None, CpuSSE2,
2467    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2468    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2469      RegXMM } },
2470  { "pandn", 2, 0xfdf, None, CpuMMX,
2471    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2472    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2473      RegMMX } },
2474  { "pandn", 2, 0x660fdf, None, CpuSSE2,
2475    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2476    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2477      RegXMM } },
2478  { "pcmpeqb", 2, 0xf74, None, CpuMMX,
2479    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2480    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2481      RegMMX } },
2482  { "pcmpeqb", 2, 0x660f74, None, CpuSSE2,
2483    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2484    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2485      RegXMM } },
2486  { "pcmpeqw", 2, 0xf75, None, CpuMMX,
2487    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2488    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2489      RegMMX } },
2490  { "pcmpeqw", 2, 0x660f75, None, CpuSSE2,
2491    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2492    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2493      RegXMM } },
2494  { "pcmpeqd", 2, 0xf76, None, CpuMMX,
2495    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2496    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2497      RegMMX } },
2498  { "pcmpeqd", 2, 0x660f76, None, CpuSSE2,
2499    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2500    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2501      RegXMM } },
2502  { "pcmpgtb", 2, 0xf64, None, CpuMMX,
2503    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2504    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2505      RegMMX } },
2506  { "pcmpgtb", 2, 0x660f64, None, CpuSSE2,
2507    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2508    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2509      RegXMM } },
2510  { "pcmpgtw", 2, 0xf65, None, CpuMMX,
2511    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2512    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2513      RegMMX } },
2514  { "pcmpgtw", 2, 0x660f65, None, CpuSSE2,
2515    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2516    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2517      RegXMM } },
2518  { "pcmpgtd", 2, 0xf66, None, CpuMMX,
2519    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2520    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2521      RegMMX } },
2522  { "pcmpgtd", 2, 0x660f66, None, CpuSSE2,
2523    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2524    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2525      RegXMM } },
2526  { "pmaddwd", 2, 0xff5, None, CpuMMX,
2527    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2528    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2529      RegMMX } },
2530  { "pmaddwd", 2, 0x660ff5, None, CpuSSE2,
2531    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2532    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2533      RegXMM } },
2534  { "pmulhw", 2, 0xfe5, None, CpuMMX,
2535    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2536    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2537      RegMMX } },
2538  { "pmulhw", 2, 0x660fe5, None, CpuSSE2,
2539    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2540    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2541      RegXMM } },
2542  { "pmullw", 2, 0xfd5, None, CpuMMX,
2543    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2544    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2545      RegMMX } },
2546  { "pmullw", 2, 0x660fd5, None, CpuSSE2,
2547    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2548    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2549      RegXMM } },
2550  { "por", 2, 0xfeb, None, CpuMMX,
2551    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2552    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2553      RegMMX } },
2554  { "por", 2, 0x660feb, None, CpuSSE2,
2555    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2556    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2557      RegXMM } },
2558  { "psllw", 2, 0xff1, None, CpuMMX,
2559    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2560    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2561      RegMMX } },
2562  { "psllw", 2, 0x660ff1, None, CpuSSE2,
2563    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2564    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2565      RegXMM } },
2566  { "psllw", 2, 0xf71, 0x6, CpuMMX,
2567    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2568    { Imm8,
2569      RegMMX } },
2570  { "psllw", 2, 0x660f71, 0x6, CpuSSE2,
2571    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2572    { Imm8,
2573      RegXMM } },
2574  { "pslld", 2, 0xff2, None, CpuMMX,
2575    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2576    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2577      RegMMX } },
2578  { "pslld", 2, 0x660ff2, None, CpuSSE2,
2579    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2580    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2581      RegXMM } },
2582  { "pslld", 2, 0xf72, 0x6, CpuMMX,
2583    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2584    { Imm8,
2585      RegMMX } },
2586  { "pslld", 2, 0x660f72, 0x6, CpuSSE2,
2587    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2588    { Imm8,
2589      RegXMM } },
2590  { "psllq", 2, 0xff3, None, CpuMMX,
2591    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2592    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2593      RegMMX } },
2594  { "psllq", 2, 0x660ff3, None, CpuSSE2,
2595    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2596    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2597      RegXMM } },
2598  { "psllq", 2, 0xf73, 0x6, CpuMMX,
2599    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2600    { Imm8,
2601      RegMMX } },
2602  { "psllq", 2, 0x660f73, 0x6, CpuSSE2,
2603    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2604    { Imm8,
2605      RegXMM } },
2606  { "psraw", 2, 0xfe1, None, CpuMMX,
2607    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2608    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2609      RegMMX } },
2610  { "psraw", 2, 0x660fe1, None, CpuSSE2,
2611    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2612    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2613      RegXMM } },
2614  { "psraw", 2, 0xf71, 0x4, CpuMMX,
2615    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2616    { Imm8,
2617      RegMMX } },
2618  { "psraw", 2, 0x660f71, 0x4, CpuSSE2,
2619    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2620    { Imm8,
2621      RegXMM } },
2622  { "psrad", 2, 0xfe2, None, CpuMMX,
2623    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2624    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2625      RegMMX } },
2626  { "psrad", 2, 0x660fe2, None, CpuSSE2,
2627    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2628    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2629      RegXMM } },
2630  { "psrad", 2, 0xf72, 0x4, CpuMMX,
2631    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2632    { Imm8,
2633      RegMMX } },
2634  { "psrad", 2, 0x660f72, 0x4, CpuSSE2,
2635    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2636    { Imm8,
2637      RegXMM } },
2638  { "psrlw", 2, 0xfd1, None, CpuMMX,
2639    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2640    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2641      RegMMX } },
2642  { "psrlw", 2, 0x660fd1, None, CpuSSE2,
2643    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2644    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2645      RegXMM } },
2646  { "psrlw", 2, 0xf71, 0x2, CpuMMX,
2647    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2648    { Imm8,
2649      RegMMX } },
2650  { "psrlw", 2, 0x660f71, 0x2, CpuSSE2,
2651    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2652    { Imm8,
2653      RegXMM } },
2654  { "psrld", 2, 0xfd2, None, CpuMMX,
2655    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2656    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2657      RegMMX } },
2658  { "psrld", 2, 0x660fd2, None, CpuSSE2,
2659    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2660    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2661      RegXMM } },
2662  { "psrld", 2, 0xf72, 0x2, CpuMMX,
2663    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2664    { Imm8,
2665      RegMMX } },
2666  { "psrld", 2, 0x660f72, 0x2, CpuSSE2,
2667    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2668    { Imm8,
2669      RegXMM } },
2670  { "psrlq", 2, 0xfd3, None, CpuMMX,
2671    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2672    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2673      RegMMX } },
2674  { "psrlq", 2, 0x660fd3, None, CpuSSE2,
2675    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2676    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2677      RegXMM } },
2678  { "psrlq", 2, 0xf73, 0x2, CpuMMX,
2679    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2680    { Imm8,
2681      RegMMX } },
2682  { "psrlq", 2, 0x660f73, 0x2, CpuSSE2,
2683    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2684    { Imm8,
2685      RegXMM } },
2686  { "psubb", 2, 0xff8, None, CpuMMX,
2687    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2688    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2689      RegMMX } },
2690  { "psubb", 2, 0x660ff8, None, CpuSSE2,
2691    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2692    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2693      RegXMM } },
2694  { "psubw", 2, 0xff9, None, CpuMMX,
2695    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2696    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2697      RegMMX } },
2698  { "psubw", 2, 0x660ff9, None, CpuSSE2,
2699    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2700    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2701      RegXMM } },
2702  { "psubd", 2, 0xffa, None, CpuMMX,
2703    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2704    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2705      RegMMX } },
2706  { "psubd", 2, 0x660ffa, None, CpuSSE2,
2707    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2708    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2709      RegXMM } },
2710  { "psubq", 2, 0xffb, None, CpuSSE2,
2711    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2712    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2713      RegMMX } },
2714  { "psubq", 2, 0x660ffb, None, CpuSSE2,
2715    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2716    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2717      RegXMM } },
2718  { "psubsb", 2, 0xfe8, None, CpuMMX,
2719    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2720    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2721      RegMMX } },
2722  { "psubsb", 2, 0x660fe8, None, CpuSSE2,
2723    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2724    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2725      RegXMM } },
2726  { "psubsw", 2, 0xfe9, None, CpuMMX,
2727    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2728    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2729      RegMMX } },
2730  { "psubsw", 2, 0x660fe9, None, CpuSSE2,
2731    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2732    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2733      RegXMM } },
2734  { "psubusb", 2, 0xfd8, None, CpuMMX,
2735    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2736    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2737      RegMMX } },
2738  { "psubusb", 2, 0x660fd8, None, CpuSSE2,
2739    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2740    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2741      RegXMM } },
2742  { "psubusw", 2, 0xfd9, None, CpuMMX,
2743    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2744    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2745      RegMMX } },
2746  { "psubusw", 2, 0x660fd9, None, CpuSSE2,
2747    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2748    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2749      RegXMM } },
2750  { "punpckhbw", 2, 0xf68, None, CpuMMX,
2751    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2752    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2753      RegMMX } },
2754  { "punpckhbw", 2, 0x660f68, None, CpuSSE2,
2755    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2756    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2757      RegXMM } },
2758  { "punpckhwd", 2, 0xf69, None, CpuMMX,
2759    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2760    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2761      RegMMX } },
2762  { "punpckhwd", 2, 0x660f69, None, CpuSSE2,
2763    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2764    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2765      RegXMM } },
2766  { "punpckhdq", 2, 0xf6a, None, CpuMMX,
2767    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2768    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2769      RegMMX } },
2770  { "punpckhdq", 2, 0x660f6a, None, CpuSSE2,
2771    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2772    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2773      RegXMM } },
2774  { "punpcklbw", 2, 0xf60, None, CpuMMX,
2775    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2776    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2777      RegMMX } },
2778  { "punpcklbw", 2, 0x660f60, None, CpuSSE2,
2779    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2780    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2781      RegXMM } },
2782  { "punpcklwd", 2, 0xf61, None, CpuMMX,
2783    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2784    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2785      RegMMX } },
2786  { "punpcklwd", 2, 0x660f61, None, CpuSSE2,
2787    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2788    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2789      RegXMM } },
2790  { "punpckldq", 2, 0xf62, None, CpuMMX,
2791    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2792    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2793      RegMMX } },
2794  { "punpckldq", 2, 0x660f62, None, CpuSSE2,
2795    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2796    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2797      RegXMM } },
2798  { "pxor", 2, 0xfef, None, CpuMMX,
2799    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2800    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2801      RegMMX } },
2802  { "pxor", 2, 0x660fef, None, CpuSSE2,
2803    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2804    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2805      RegXMM } },
2806  { "addps", 2, 0xf58, None, CpuSSE,
2807    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2808    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2809      RegXMM } },
2810  { "addss", 2, 0xf30f58, None, CpuSSE,
2811    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2812    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2813      RegXMM } },
2814  { "andnps", 2, 0xf55, None, CpuSSE,
2815    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2816    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2817      RegXMM } },
2818  { "andps", 2, 0xf54, None, CpuSSE,
2819    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2820    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2821      RegXMM } },
2822  { "cmpeqps", 2, 0xfc2, 0x0, CpuSSE,
2823    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2824    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2825      RegXMM } },
2826  { "cmpeqss", 2, 0xf30fc2, 0x0, CpuSSE,
2827    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2828    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2829      RegXMM } },
2830  { "cmpleps", 2, 0xfc2, 0x2, CpuSSE,
2831    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2832    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2833      RegXMM } },
2834  { "cmpless", 2, 0xf30fc2, 0x2, CpuSSE,
2835    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2836    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2837      RegXMM } },
2838  { "cmpltps", 2, 0xfc2, 0x1, CpuSSE,
2839    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2840    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2841      RegXMM } },
2842  { "cmpltss", 2, 0xf30fc2, 0x1, CpuSSE,
2843    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2844    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2845      RegXMM } },
2846  { "cmpneqps", 2, 0xfc2, 0x4, CpuSSE,
2847    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2848    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2849      RegXMM } },
2850  { "cmpneqss", 2, 0xf30fc2, 0x4, CpuSSE,
2851    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2852    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2853      RegXMM } },
2854  { "cmpnleps", 2, 0xfc2, 0x6, CpuSSE,
2855    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2856    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2857      RegXMM } },
2858  { "cmpnless", 2, 0xf30fc2, 0x6, CpuSSE,
2859    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2860    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2861      RegXMM } },
2862  { "cmpnltps", 2, 0xfc2, 0x5, CpuSSE,
2863    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2864    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2865      RegXMM } },
2866  { "cmpnltss", 2, 0xf30fc2, 0x5, CpuSSE,
2867    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2868    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2869      RegXMM } },
2870  { "cmpordps", 2, 0xfc2, 0x7, CpuSSE,
2871    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2872    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2873      RegXMM } },
2874  { "cmpordss", 2, 0xf30fc2, 0x7, CpuSSE,
2875    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2876    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2877      RegXMM } },
2878  { "cmpunordps", 2, 0xfc2, 0x3, CpuSSE,
2879    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2880    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2881      RegXMM } },
2882  { "cmpunordss", 2, 0xf30fc2, 0x3, CpuSSE,
2883    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2884    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2885      RegXMM } },
2886  { "cmpps", 3, 0xfc2, None, CpuSSE,
2887    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2888    { Imm8,
2889      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2890      RegXMM } },
2891  { "cmpss", 3, 0xf30fc2, None, CpuSSE,
2892    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2893    { Imm8,
2894      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2895      RegXMM } },
2896  { "comiss", 2, 0xf2f, None, CpuSSE,
2897    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2898    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2899      RegXMM } },
2900  { "cvtpi2ps", 2, 0xf2a, None, CpuSSE,
2901    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2902    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2903      RegXMM } },
2904  { "cvtps2pi", 2, 0xf2d, None, CpuSSE,
2905    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2906    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2907      RegMMX } },
2908  { "cvtsi2ss", 2, 0xf30f2a, None, CpuSSE,
2909    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2910    { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2911      RegXMM } },
2912  { "cvtss2si", 2, 0xf30f2d, None, CpuSSE,
2913    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2914    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2915      Reg32|Reg64 } },
2916  { "cvttps2pi", 2, 0xf2c, None, CpuSSE,
2917    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2918    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2919      RegMMX } },
2920  { "cvttss2si", 2, 0xf30f2c, None, CpuSSE,
2921    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2922    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2923      Reg32|Reg64 } },
2924  { "divps", 2, 0xf5e, None, CpuSSE,
2925    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2926    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2927      RegXMM } },
2928  { "divss", 2, 0xf30f5e, None, CpuSSE,
2929    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2930    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2931      RegXMM } },
2932  { "ldmxcsr", 1, 0xfae, 0x2, CpuSSE,
2933    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2934    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2935  { "maskmovq", 2, 0xff7, None, CpuMMX2,
2936    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2937    { RegMMX,
2938      RegMMX } },
2939  { "maxps", 2, 0xf5f, None, CpuSSE,
2940    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2941    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2942      RegXMM } },
2943  { "maxss", 2, 0xf30f5f, None, CpuSSE,
2944    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2945    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2946      RegXMM } },
2947  { "minps", 2, 0xf5d, None, CpuSSE,
2948    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2949    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2950      RegXMM } },
2951  { "minss", 2, 0xf30f5d, None, CpuSSE,
2952    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2953    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2954      RegXMM } },
2955  { "movaps", 2, 0xf28, None, CpuSSE,
2956    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2957    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2958      RegXMM } },
2959  { "movaps", 2, 0xf29, None, CpuSSE,
2960    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2961    { RegXMM,
2962      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
2963  { "movhlps", 2, 0xf12, None, CpuSSE,
2964    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2965    { RegXMM,
2966      RegXMM } },
2967  { "movhps", 2, 0xf16, None, CpuSSE,
2968    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2969    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2970      RegXMM } },
2971  { "movhps", 2, 0xf17, None, CpuSSE,
2972    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2973    { RegXMM,
2974      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2975  { "movlhps", 2, 0xf16, None, CpuSSE,
2976    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2977    { RegXMM,
2978      RegXMM } },
2979  { "movlps", 2, 0xf12, None, CpuSSE,
2980    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2981    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2982      RegXMM } },
2983  { "movlps", 2, 0xf13, None, CpuSSE,
2984    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2985    { RegXMM,
2986      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2987  { "movmskps", 2, 0xf50, None, CpuSSE,
2988    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2989    { RegXMM,
2990      Reg32|Reg64 } },
2991  { "movntps", 2, 0xf2b, None, CpuSSE,
2992    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2993    { RegXMM,
2994      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2995  { "movntq", 2, 0xfe7, None, CpuMMX2,
2996    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2997    { RegMMX,
2998      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2999  { "movntdq", 2, 0x660fe7, None, CpuSSE2,
3000    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3001    { RegXMM,
3002      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3003  { "movss", 2, 0xf30f10, None, CpuSSE,
3004    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3005    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3006      RegXMM } },
3007  { "movss", 2, 0xf30f11, None, CpuSSE,
3008    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3009    { RegXMM,
3010      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3011  { "movups", 2, 0xf10, None, CpuSSE,
3012    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3013    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3014      RegXMM } },
3015  { "movups", 2, 0xf11, None, CpuSSE,
3016    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3017    { RegXMM,
3018      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3019  { "mulps", 2, 0xf59, None, CpuSSE,
3020    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3021    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3022      RegXMM } },
3023  { "mulss", 2, 0xf30f59, None, CpuSSE,
3024    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3025    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3026      RegXMM } },
3027  { "orps", 2, 0xf56, None, CpuSSE,
3028    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3029    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3030      RegXMM } },
3031  { "pavgb", 2, 0xfe0, None, CpuMMX2,
3032    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3033    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3034      RegMMX } },
3035  { "pavgb", 2, 0x660fe0, None, CpuSSE2,
3036    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3037    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3038      RegXMM } },
3039  { "pavgw", 2, 0xfe3, None, CpuMMX2,
3040    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3041    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3042      RegMMX } },
3043  { "pavgw", 2, 0x660fe3, None, CpuSSE2,
3044    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3045    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3046      RegXMM } },
3047  { "pextrw", 3, 0xfc5, None, CpuMMX2,
3048    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3049    { Imm8,
3050      RegMMX,
3051      Reg32|Reg64 } },
3052  { "pextrw", 3, 0x660fc5, None, CpuSSE2,
3053    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3054    { Imm8,
3055      RegXMM,
3056      Reg32|Reg64 } },
3057  { "pextrw", 3, 0x660f3a15, None, CpuSSE4_1,
3058    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3059    { Imm8,
3060      RegXMM,
3061      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3062  { "pinsrw", 3, 0xfc4, None, CpuMMX2,
3063    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3064    { Imm8,
3065      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3066      RegMMX } },
3067  { "pinsrw", 3, 0x660fc4, None, CpuSSE2,
3068    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3069    { Imm8,
3070      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3071      RegXMM } },
3072  { "pmaxsw", 2, 0xfee, None, CpuMMX2,
3073    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3074    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3075      RegMMX } },
3076  { "pmaxsw", 2, 0x660fee, None, CpuSSE2,
3077    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3078    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3079      RegXMM } },
3080  { "pmaxub", 2, 0xfde, None, CpuMMX2,
3081    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3082    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3083      RegMMX } },
3084  { "pmaxub", 2, 0x660fde, None, CpuSSE2,
3085    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3086    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3087      RegXMM } },
3088  { "pminsw", 2, 0xfea, None, CpuMMX2,
3089    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3090    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3091      RegMMX } },
3092  { "pminsw", 2, 0x660fea, None, CpuSSE2,
3093    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3094    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3095      RegXMM } },
3096  { "pminub", 2, 0xfda, None, CpuMMX2,
3097    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3098    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3099      RegMMX } },
3100  { "pminub", 2, 0x660fda, None, CpuSSE2,
3101    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3102    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3103      RegXMM } },
3104  { "pmovmskb", 2, 0xfd7, None, CpuMMX2,
3105    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3106    { RegMMX,
3107      Reg32|Reg64 } },
3108  { "pmovmskb", 2, 0x660fd7, None, CpuSSE2,
3109    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3110    { RegXMM,
3111      Reg32|Reg64 } },
3112  { "pmulhuw", 2, 0xfe4, None, CpuMMX2,
3113    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3114    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3115      RegMMX } },
3116  { "pmulhuw", 2, 0x660fe4, None, CpuSSE2,
3117    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3118    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3119      RegXMM } },
3120  { "prefetchnta", 1, 0xf18, 0x0, CpuMMX2,
3121    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3122    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3123  { "prefetcht0", 1, 0xf18, 0x1, CpuMMX2,
3124    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3125    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3126  { "prefetcht1", 1, 0xf18, 0x2, CpuMMX2,
3127    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3128    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3129  { "prefetcht2", 1, 0xf18, 0x3, CpuMMX2,
3130    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3131    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3132  { "psadbw", 2, 0xff6, None, CpuMMX2,
3133    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3134    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3135      RegMMX } },
3136  { "psadbw", 2, 0x660ff6, None, CpuSSE2,
3137    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3138    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3139      RegXMM } },
3140  { "pshufw", 3, 0xf70, None, CpuMMX2,
3141    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3142    { Imm8,
3143      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3144      RegMMX } },
3145  { "rcpps", 2, 0xf53, None, CpuSSE,
3146    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3147    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3148      RegXMM } },
3149  { "rcpss", 2, 0xf30f53, None, CpuSSE,
3150    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3151    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3152      RegXMM } },
3153  { "rsqrtps", 2, 0xf52, None, CpuSSE,
3154    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3155    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3156      RegXMM } },
3157  { "rsqrtss", 2, 0xf30f52, None, CpuSSE,
3158    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3159    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3160      RegXMM } },
3161  { "sfence", 0, 0xfae, 0xf8, CpuMMX2,
3162    IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3163    { 0 } },
3164  { "shufps", 3, 0xfc6, None, CpuSSE,
3165    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3166    { Imm8,
3167      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3168      RegXMM } },
3169  { "sqrtps", 2, 0xf51, None, CpuSSE,
3170    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3171    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3172      RegXMM } },
3173  { "sqrtss", 2, 0xf30f51, None, CpuSSE,
3174    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3175    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3176      RegXMM } },
3177  { "stmxcsr", 1, 0xfae, 0x3, CpuSSE,
3178    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3179    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3180  { "subps", 2, 0xf5c, None, CpuSSE,
3181    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3182    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3183      RegXMM } },
3184  { "subss", 2, 0xf30f5c, None, CpuSSE,
3185    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3186    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3187      RegXMM } },
3188  { "ucomiss", 2, 0xf2e, None, CpuSSE,
3189    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3190    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3191      RegXMM } },
3192  { "unpckhps", 2, 0xf15, None, CpuSSE,
3193    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3194    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3195      RegXMM } },
3196  { "unpcklps", 2, 0xf14, None, CpuSSE,
3197    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3198    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3199      RegXMM } },
3200  { "xorps", 2, 0xf57, None, CpuSSE,
3201    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3202    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3203      RegXMM } },
3204  { "addpd", 2, 0x660f58, None, CpuSSE2,
3205    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3206    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3207      RegXMM } },
3208  { "addsd", 2, 0xf20f58, None, CpuSSE2,
3209    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3210    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3211      RegXMM } },
3212  { "andnpd", 2, 0x660f55, None, CpuSSE2,
3213    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3214    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3215      RegXMM } },
3216  { "andpd", 2, 0x660f54, None, CpuSSE2,
3217    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3218    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3219      RegXMM } },
3220  { "cmpeqpd", 2, 0x660fc2, 0x0, CpuSSE2,
3221    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3222    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3223      RegXMM } },
3224  { "cmpeqsd", 2, 0xf20fc2, 0x0, CpuSSE2,
3225    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3226    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3227      RegXMM } },
3228  { "cmplepd", 2, 0x660fc2, 0x2, CpuSSE2,
3229    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3230    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3231      RegXMM } },
3232  { "cmplesd", 2, 0xf20fc2, 0x2, CpuSSE2,
3233    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3234    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3235      RegXMM } },
3236  { "cmpltpd", 2, 0x660fc2, 0x1, CpuSSE2,
3237    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3238    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3239      RegXMM } },
3240  { "cmpltsd", 2, 0xf20fc2, 0x1, CpuSSE2,
3241    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3242    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3243      RegXMM } },
3244  { "cmpneqpd", 2, 0x660fc2, 0x4, CpuSSE2,
3245    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3246    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3247      RegXMM } },
3248  { "cmpneqsd", 2, 0xf20fc2, 0x4, CpuSSE2,
3249    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3250    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3251      RegXMM } },
3252  { "cmpnlepd", 2, 0x660fc2, 0x6, CpuSSE2,
3253    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3254    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3255      RegXMM } },
3256  { "cmpnlesd", 2, 0xf20fc2, 0x6, CpuSSE2,
3257    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3258    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3259      RegXMM } },
3260  { "cmpnltpd", 2, 0x660fc2, 0x5, CpuSSE2,
3261    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3262    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3263      RegXMM } },
3264  { "cmpnltsd", 2, 0xf20fc2, 0x5, CpuSSE2,
3265    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3266    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3267      RegXMM } },
3268  { "cmpordpd", 2, 0x660fc2, 0x7, CpuSSE2,
3269    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3270    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3271      RegXMM } },
3272  { "cmpordsd", 2, 0xf20fc2, 0x7, CpuSSE2,
3273    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3274    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3275      RegXMM } },
3276  { "cmpunordpd", 2, 0x660fc2, 0x3, CpuSSE2,
3277    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3278    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3279      RegXMM } },
3280  { "cmpunordsd", 2, 0xf20fc2, 0x3, CpuSSE2,
3281    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3282    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3283      RegXMM } },
3284  { "cmppd", 3, 0x660fc2, None, CpuSSE2,
3285    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3286    { Imm8,
3287      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3288      RegXMM } },
3289  { "cmpsd", 0, 0xa7, None, 0,
3290    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3291    { 0 } },
3292  { "cmpsd", 2, 0xa7, None, 0,
3293    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3294    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3295      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
3296  { "cmpsd", 3, 0xf20fc2, None, CpuSSE2,
3297    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3298    { Imm8,
3299      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3300      RegXMM } },
3301  { "comisd", 2, 0x660f2f, None, CpuSSE2,
3302    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3303    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3304      RegXMM } },
3305  { "cvtpi2pd", 2, 0x660f2a, None, CpuSSE2,
3306    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3307    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3308      RegXMM } },
3309  { "cvtsi2sd", 2, 0xf20f2a, None, CpuSSE2,
3310    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3311    { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3312      RegXMM } },
3313  { "divpd", 2, 0x660f5e, None, CpuSSE2,
3314    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3315    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3316      RegXMM } },
3317  { "divsd", 2, 0xf20f5e, None, CpuSSE2,
3318    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3319    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3320      RegXMM } },
3321  { "maxpd", 2, 0x660f5f, None, CpuSSE2,
3322    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3323    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3324      RegXMM } },
3325  { "maxsd", 2, 0xf20f5f, None, CpuSSE2,
3326    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3327    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3328      RegXMM } },
3329  { "minpd", 2, 0x660f5d, None, CpuSSE2,
3330    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3331    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3332      RegXMM } },
3333  { "minsd", 2, 0xf20f5d, None, CpuSSE2,
3334    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3335    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3336      RegXMM } },
3337  { "movapd", 2, 0x660f28, None, CpuSSE2,
3338    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3339    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3340      RegXMM } },
3341  { "movapd", 2, 0x660f29, None, CpuSSE2,
3342    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3343    { RegXMM,
3344      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3345  { "movhpd", 2, 0x660f16, None, CpuSSE2,
3346    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3347    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3348      RegXMM } },
3349  { "movhpd", 2, 0x660f17, None, CpuSSE2,
3350    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3351    { RegXMM,
3352      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3353  { "movlpd", 2, 0x660f12, None, CpuSSE2,
3354    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3355    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3356      RegXMM } },
3357  { "movlpd", 2, 0x660f13, None, CpuSSE2,
3358    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3359    { RegXMM,
3360      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3361  { "movmskpd", 2, 0x660f50, None, CpuSSE2,
3362    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3363    { RegXMM,
3364      Reg32|Reg64 } },
3365  { "movntpd", 2, 0x660f2b, None, CpuSSE2,
3366    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3367    { RegXMM,
3368      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3369  { "movsd", 0, 0xa5, None, 0,
3370    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3371    { 0 } },
3372  { "movsd", 2, 0xa5, None, 0,
3373    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3374    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3375      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
3376  { "movsd", 2, 0xf20f10, None, CpuSSE2,
3377    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3378    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3379      RegXMM } },
3380  { "movsd", 2, 0xf20f11, None, CpuSSE2,
3381    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3382    { RegXMM,
3383      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3384  { "movupd", 2, 0x660f10, None, CpuSSE2,
3385    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3386    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3387      RegXMM } },
3388  { "movupd", 2, 0x660f11, None, CpuSSE2,
3389    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3390    { RegXMM,
3391      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3392  { "mulpd", 2, 0x660f59, None, CpuSSE2,
3393    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3394    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3395      RegXMM } },
3396  { "mulsd", 2, 0xf20f59, None, CpuSSE2,
3397    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3398    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3399      RegXMM } },
3400  { "orpd", 2, 0x660f56, None, CpuSSE2,
3401    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3402    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3403      RegXMM } },
3404  { "shufpd", 3, 0x660fc6, None, CpuSSE2,
3405    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3406    { Imm8,
3407      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3408      RegXMM } },
3409  { "sqrtpd", 2, 0x660f51, None, CpuSSE2,
3410    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3411    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3412      RegXMM } },
3413  { "sqrtsd", 2, 0xf20f51, None, CpuSSE2,
3414    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3415    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3416      RegXMM } },
3417  { "subpd", 2, 0x660f5c, None, CpuSSE2,
3418    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3419    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3420      RegXMM } },
3421  { "subsd", 2, 0xf20f5c, None, CpuSSE2,
3422    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3423    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3424      RegXMM } },
3425  { "ucomisd", 2, 0x660f2e, None, CpuSSE2,
3426    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3427    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3428      RegXMM } },
3429  { "unpckhpd", 2, 0x660f15, None, CpuSSE2,
3430    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3431    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3432      RegXMM } },
3433  { "unpcklpd", 2, 0x660f14, None, CpuSSE2,
3434    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3435    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3436      RegXMM } },
3437  { "xorpd", 2, 0x660f57, None, CpuSSE2,
3438    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3439    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3440      RegXMM } },
3441  { "cvtdq2pd", 2, 0xf30fe6, None, CpuSSE2,
3442    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3443    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3444      RegXMM } },
3445  { "cvtpd2dq", 2, 0xf20fe6, None, CpuSSE2,
3446    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3447    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3448      RegXMM } },
3449  { "cvtdq2ps", 2, 0xf5b, None, CpuSSE2,
3450    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3451    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3452      RegXMM } },
3453  { "cvtpd2pi", 2, 0x660f2d, None, CpuSSE2,
3454    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3455    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3456      RegMMX } },
3457  { "cvtpd2ps", 2, 0x660f5a, None, CpuSSE2,
3458    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3459    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3460      RegXMM } },
3461  { "cvtps2pd", 2, 0xf5a, None, CpuSSE2,
3462    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3463    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3464      RegXMM } },
3465  { "cvtps2dq", 2, 0x660f5b, None, CpuSSE2,
3466    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3467    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3468      RegXMM } },
3469  { "cvtsd2si", 2, 0xf20f2d, None, CpuSSE2,
3470    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3471    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3472      Reg32|Reg64 } },
3473  { "cvtsd2ss", 2, 0xf20f5a, None, CpuSSE2,
3474    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3475    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3476      RegXMM } },
3477  { "cvtss2sd", 2, 0xf30f5a, None, CpuSSE2,
3478    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3479    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3480      RegXMM } },
3481  { "cvttpd2pi", 2, 0x660f2c, None, CpuSSE2,
3482    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3483    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3484      RegMMX } },
3485  { "cvttsd2si", 2, 0xf20f2c, None, CpuSSE2,
3486    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3487    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3488      Reg32|Reg64 } },
3489  { "cvttpd2dq", 2, 0x660fe6, None, CpuSSE2,
3490    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3491    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3492      RegXMM } },
3493  { "cvttps2dq", 2, 0xf30f5b, None, CpuSSE2,
3494    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3495    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3496      RegXMM } },
3497  { "maskmovdqu", 2, 0x660ff7, None, CpuSSE2,
3498    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3499    { RegXMM,
3500      RegXMM } },
3501  { "movdqa", 2, 0x660f6f, None, CpuSSE2,
3502    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3503    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3504      RegXMM } },
3505  { "movdqa", 2, 0x660f7f, None, CpuSSE2,
3506    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3507    { RegXMM,
3508      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3509  { "movdqu", 2, 0xf30f6f, None, CpuSSE2,
3510    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3511    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3512      RegXMM } },
3513  { "movdqu", 2, 0xf30f7f, None, CpuSSE2,
3514    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3515    { RegXMM,
3516      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3517  { "movdq2q", 2, 0xf20fd6, None, CpuSSE2,
3518    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3519    { RegXMM,
3520      RegMMX } },
3521  { "movq2dq", 2, 0xf30fd6, None, CpuSSE2,
3522    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3523    { RegMMX,
3524      RegXMM } },
3525  { "pmuludq", 2, 0xff4, None, CpuSSE2,
3526    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3527    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3528      RegMMX } },
3529  { "pmuludq", 2, 0x660ff4, None, CpuSSE2,
3530    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3531    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3532      RegXMM } },
3533  { "pshufd", 3, 0x660f70, None, CpuSSE2,
3534    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3535    { Imm8,
3536      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3537      RegXMM } },
3538  { "pshufhw", 3, 0xf30f70, None, CpuSSE2,
3539    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3540    { Imm8,
3541      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3542      RegXMM } },
3543  { "pshuflw", 3, 0xf20f70, None, CpuSSE2,
3544    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3545    { Imm8,
3546      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3547      RegXMM } },
3548  { "pslldq", 2, 0x660f73, 0x7, CpuSSE2,
3549    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3550    { Imm8,
3551      RegXMM } },
3552  { "psrldq", 2, 0x660f73, 0x3, CpuSSE2,
3553    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3554    { Imm8,
3555      RegXMM } },
3556  { "punpckhqdq", 2, 0x660f6d, None, CpuSSE2,
3557    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3558    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3559      RegXMM } },
3560  { "punpcklqdq", 2, 0x660f6c, None, CpuSSE2,
3561    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3562    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3563      RegXMM } },
3564  { "addsubpd", 2, 0x660fd0, None, CpuSSE3,
3565    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3566    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3567      RegXMM } },
3568  { "addsubps", 2, 0xf20fd0, None, CpuSSE3,
3569    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3570    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3571      RegXMM } },
3572  { "cmpxchg16b", 1, 0xfc7, 0x1, CpuSSE3|Cpu64,
3573    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
3574    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3575  { "fisttp", 1, 0xdf, 0x1, CpuSSE3,
3576    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
3577    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3578  { "fisttp", 1, 0xdd, 0x1, CpuSSE3,
3579    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
3580    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3581  { "fisttpll", 1, 0xdd, 0x1, CpuSSE3,
3582    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3583    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3584  { "haddpd", 2, 0x660f7c, None, CpuSSE3,
3585    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3586    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3587      RegXMM } },
3588  { "haddps", 2, 0xf20f7c, None, CpuSSE3,
3589    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3590    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3591      RegXMM } },
3592  { "hsubpd", 2, 0x660f7d, None, CpuSSE3,
3593    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3594    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3595      RegXMM } },
3596  { "hsubps", 2, 0xf20f7d, None, CpuSSE3,
3597    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3598    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3599      RegXMM } },
3600  { "lddqu", 2, 0xf20ff0, None, CpuSSE3,
3601    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3602    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3603      RegXMM } },
3604  { "monitor", 0, 0xf01, 0xc8, CpuSSE3,
3605    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3606    { 0 } },
3607  { "monitor", 3, 0xf01, 0xc8, CpuSSE3|CpuNo64,
3608    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3609    { Reg16|Reg32,
3610      Reg32,
3611      Reg32 } },
3612  { "monitor", 3, 0xf01, 0xc8, CpuSSE3|Cpu64,
3613    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
3614    { Reg32|Reg64,
3615      Reg64,
3616      Reg64 } },
3617  { "movddup", 2, 0xf20f12, None, CpuSSE3,
3618    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3619    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3620      RegXMM } },
3621  { "movshdup", 2, 0xf30f16, None, CpuSSE3,
3622    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3623    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3624      RegXMM } },
3625  { "movsldup", 2, 0xf30f12, None, CpuSSE3,
3626    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3627    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3628      RegXMM } },
3629  { "mwait", 0, 0xf01, 0xc9, CpuSSE3,
3630    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3631    { 0 } },
3632  { "mwait", 2, 0xf01, 0xc9, CpuSSE3|CpuNo64,
3633    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3634    { Reg32,
3635      Reg32 } },
3636  { "mwait", 2, 0xf01, 0xc9, CpuSSE3|Cpu64,
3637    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
3638    { Reg64,
3639      Reg64 } },
3640  { "invept", 2, 0x660f3880, None, CpuVMX|CpuNo64,
3641    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3642    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3643      Reg32 } },
3644  { "invept", 2, 0x660f3880, None, CpuVMX|Cpu64,
3645    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3646    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3647      Reg64 } },
3648  { "invvpid", 2, 0x660f3881, None, CpuVMX|CpuNo64,
3649    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3650    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3651      Reg32 } },
3652  { "invvpid", 2, 0x660f3881, None, CpuVMX|Cpu64,
3653    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3654    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3655      Reg64 } },
3656  { "invpcid", 2, 0x660f3882, None, CpuNo64,
3657    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3658    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3659      Reg32 } },
3660  { "invpcid", 2, 0x660f3882, None, Cpu64,
3661    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3662    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3663      Reg64 } },
3664  { "vmcall", 0, 0xf01, 0xc1, CpuVMX,
3665    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3666    { 0 } },
3667  { "vmclear", 1, 0x660fc7, 0x6, CpuVMX,
3668    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3669    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3670  { "vmlaunch", 0, 0xf01, 0xc2, CpuVMX,
3671    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3672    { 0 } },
3673  { "vmresume", 0, 0xf01, 0xc3, CpuVMX,
3674    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3675    { 0 } },
3676  { "vmptrld", 1, 0xfc7, 0x6, CpuVMX,
3677    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3678    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3679  { "vmptrst", 1, 0xfc7, 0x7, CpuVMX,
3680    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3681    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3682  { "vmread", 2, 0xf78, None, CpuVMX|CpuNo64,
3683    Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
3684    { Reg32,
3685      Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3686  { "vmread", 2, 0xf78, None, CpuVMX|Cpu64,
3687    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
3688    { Reg64,
3689      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3690  { "vmwrite", 2, 0xf79, None, CpuVMX|CpuNo64,
3691    Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
3692    { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3693      Reg32 } },
3694  { "vmwrite", 2, 0xf79, None, CpuVMX|Cpu64,
3695    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
3696    { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3697      Reg64 } },
3698  { "vmxoff", 0, 0xf01, 0xc4, CpuVMX,
3699    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3700    { 0 } },
3701  { "vmxon", 1, 0xf30fc7, 0x6, CpuVMX,
3702    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3703    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3704  { "phaddw", 2, 0xf3801, None, CpuSSSE3,
3705    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3706    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3707      RegMMX } },
3708  { "phaddw", 2, 0x660f3801, None, CpuSSSE3,
3709    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3710    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3711      RegXMM } },
3712  { "phaddd", 2, 0xf3802, None, CpuSSSE3,
3713    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3714    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3715      RegMMX } },
3716  { "phaddd", 2, 0x660f3802, None, CpuSSSE3,
3717    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3718    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3719      RegXMM } },
3720  { "phaddsw", 2, 0xf3803, None, CpuSSSE3,
3721    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3722    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3723      RegMMX } },
3724  { "phaddsw", 2, 0x660f3803, None, CpuSSSE3,
3725    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3726    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3727      RegXMM } },
3728  { "phsubw", 2, 0xf3805, None, CpuSSSE3,
3729    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3730    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3731      RegMMX } },
3732  { "phsubw", 2, 0x660f3805, None, CpuSSSE3,
3733    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3734    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3735      RegXMM } },
3736  { "phsubd", 2, 0xf3806, None, CpuSSSE3,
3737    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3738    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3739      RegMMX } },
3740  { "phsubd", 2, 0x660f3806, None, CpuSSSE3,
3741    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3742    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3743      RegXMM } },
3744  { "phsubsw", 2, 0xf3807, None, CpuSSSE3,
3745    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3746    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3747      RegMMX } },
3748  { "phsubsw", 2, 0x660f3807, None, CpuSSSE3,
3749    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3750    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3751      RegXMM } },
3752  { "pmaddubsw", 2, 0xf3804, None, CpuSSSE3,
3753    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3754    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3755      RegMMX } },
3756  { "pmaddubsw", 2, 0x660f3804, None, CpuSSSE3,
3757    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3758    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3759      RegXMM } },
3760  { "pmulhrsw", 2, 0xf380b, None, CpuSSSE3,
3761    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3762    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3763      RegMMX } },
3764  { "pmulhrsw", 2, 0x660f380b, None, CpuSSSE3,
3765    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3766    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3767      RegXMM } },
3768  { "pshufb", 2, 0xf3800, None, CpuSSSE3,
3769    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3770    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3771      RegMMX } },
3772  { "pshufb", 2, 0x660f3800, None, CpuSSSE3,
3773    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3774    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3775      RegXMM } },
3776  { "psignb", 2, 0xf3808, None, CpuSSSE3,
3777    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3778    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3779      RegMMX } },
3780  { "psignb", 2, 0x660f3808, None, CpuSSSE3,
3781    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3782    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3783      RegXMM } },
3784  { "psignw", 2, 0xf3809, None, CpuSSSE3,
3785    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3786    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3787      RegMMX } },
3788  { "psignw", 2, 0x660f3809, None, CpuSSSE3,
3789    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3790    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3791      RegXMM } },
3792  { "psignd", 2, 0xf380a, None, CpuSSSE3,
3793    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3794    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3795      RegMMX } },
3796  { "psignd", 2, 0x660f380a, None, CpuSSSE3,
3797    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3798    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3799      RegXMM } },
3800  { "palignr", 3, 0xf3a0f, None, CpuSSSE3,
3801    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3802    { Imm8,
3803      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3804      RegMMX } },
3805  { "palignr", 3, 0x660f3a0f, None, CpuSSSE3,
3806    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3807    { Imm8,
3808      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3809      RegXMM } },
3810  { "pabsb", 2, 0xf381c, None, CpuSSSE3,
3811    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3812    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3813      RegMMX } },
3814  { "pabsb", 2, 0x660f381c, None, CpuSSSE3,
3815    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3816    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3817      RegXMM } },
3818  { "pabsw", 2, 0xf381d, None, CpuSSSE3,
3819    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3820    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3821      RegMMX } },
3822  { "pabsw", 2, 0x660f381d, None, CpuSSSE3,
3823    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3824    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3825      RegXMM } },
3826  { "pabsd", 2, 0xf381e, None, CpuSSSE3,
3827    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3828    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3829      RegMMX } },
3830  { "pabsd", 2, 0x660f381e, None, CpuSSSE3,
3831    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3832    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3833      RegXMM } },
3834  { "blendpd", 3, 0x660f3a0d, None, CpuSSE4_1,
3835    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3836    { Imm8,
3837      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3838      RegXMM } },
3839  { "blendps", 3, 0x660f3a0c, None, CpuSSE4_1,
3840    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3841    { Imm8,
3842      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3843      RegXMM } },
3844  { "blendvpd", 3, 0x660f3815, None, CpuSSE4_1,
3845    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
3846    { RegXMM,
3847      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3848      RegXMM } },
3849  { "blendvps", 3, 0x660f3814, None, CpuSSE4_1,
3850    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
3851    { RegXMM,
3852      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3853      RegXMM } },
3854  { "dppd", 3, 0x660f3a41, None, CpuSSE4_1,
3855    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3856    { Imm8,
3857      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3858      RegXMM } },
3859  { "dpps", 3, 0x660f3a40, None, CpuSSE4_1,
3860    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3861    { Imm8,
3862      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3863      RegXMM } },
3864  { "extractps", 3, 0x660f3a17, None, CpuSSE4_1,
3865    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3866    { Imm8,
3867      RegXMM,
3868      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3869  { "insertps", 3, 0x660f3a21, None, CpuSSE4_1,
3870    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3871    { Imm8,
3872      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3873      RegXMM } },
3874  { "movntdqa", 2, 0x660f382a, None, CpuSSE4_1,
3875    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3876    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3877      RegXMM } },
3878  { "mpsadbw", 3, 0x660f3a42, None, CpuSSE4_1,
3879    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3880    { Imm8,
3881      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3882      RegXMM } },
3883  { "packusdw", 2, 0x660f382b, None, CpuSSE4_1,
3884    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3885    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3886      RegXMM } },
3887  { "pblendvb", 3, 0x660f3810, None, CpuSSE4_1,
3888    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
3889    { RegXMM,
3890      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3891      RegXMM } },
3892  { "pblendw", 3, 0x660f3a0e, None, CpuSSE4_1,
3893    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3894    { Imm8,
3895      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3896      RegXMM } },
3897  { "pcmpeqq", 2, 0x660f3829, None, CpuSSE4_1,
3898    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3899    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3900      RegXMM } },
3901  { "pextrb", 3, 0x660f3a14, None, CpuSSE4_1,
3902    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3903    { Imm8,
3904      RegXMM,
3905      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3906  { "pextrd", 3, 0x660f3a16, None, CpuSSE4_1,
3907    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3908    { Imm8,
3909      RegXMM,
3910      Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3911  { "pextrq", 3, 0x660f3a16, None, CpuSSE4_1|Cpu64,
3912    Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3913    { Imm8,
3914      RegXMM,
3915      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3916  { "phminposuw", 2, 0x660f3841, None, CpuSSE4_1,
3917    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3918    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3919      RegXMM } },
3920  { "pinsrb", 3, 0x660f3a20, None, CpuSSE4_1,
3921    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3922    { Imm8,
3923      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3924      RegXMM } },
3925  { "pinsrd", 3, 0x660f3a22, None, CpuSSE4_1,
3926    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3927    { Imm8,
3928      Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3929      RegXMM } },
3930  { "pinsrq", 3, 0x660f3a22, None, CpuSSE4_1|Cpu64,
3931    Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3932    { Imm8,
3933      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3934      RegXMM } },
3935  { "pmaxsb", 2, 0x660f383c, None, CpuSSE4_1,
3936    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3937    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3938      RegXMM } },
3939  { "pmaxsd", 2, 0x660f383d, None, CpuSSE4_1,
3940    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3941    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3942      RegXMM } },
3943  { "pmaxud", 2, 0x660f383f, None, CpuSSE4_1,
3944    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3945    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3946      RegXMM } },
3947  { "pmaxuw", 2, 0x660f383e, None, CpuSSE4_1,
3948    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3949    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3950      RegXMM } },
3951  { "pminsb", 2, 0x660f3838, None, CpuSSE4_1,
3952    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3953    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3954      RegXMM } },
3955  { "pminsd", 2, 0x660f3839, None, CpuSSE4_1,
3956    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3957    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3958      RegXMM } },
3959  { "pminud", 2, 0x660f383b, None, CpuSSE4_1,
3960    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3961    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3962      RegXMM } },
3963  { "pminuw", 2, 0x660f383a, None, CpuSSE4_1,
3964    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3965    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3966      RegXMM } },
3967  { "pmovsxbw", 2, 0x660f3820, None, CpuSSE4_1,
3968    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3969    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3970      RegXMM } },
3971  { "pmovsxbd", 2, 0x660f3821, None, CpuSSE4_1,
3972    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3973    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3974      RegXMM } },
3975  { "pmovsxbq", 2, 0x660f3822, None, CpuSSE4_1,
3976    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3977    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3978      RegXMM } },
3979  { "pmovsxwd", 2, 0x660f3823, None, CpuSSE4_1,
3980    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3981    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3982      RegXMM } },
3983  { "pmovsxwq", 2, 0x660f3824, None, CpuSSE4_1,
3984    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3985    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3986      RegXMM } },
3987  { "pmovsxdq", 2, 0x660f3825, None, CpuSSE4_1,
3988    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3989    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3990      RegXMM } },
3991  { "pmovzxbw", 2, 0x660f3830, None, CpuSSE4_1,
3992    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3993    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3994      RegXMM } },
3995  { "pmovzxbd", 2, 0x660f3831, None, CpuSSE4_1,
3996    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3997    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3998      RegXMM } },
3999  { "pmovzxbq", 2, 0x660f3832, None, CpuSSE4_1,
4000    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4001    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4002      RegXMM } },
4003  { "pmovzxwd", 2, 0x660f3833, None, CpuSSE4_1,
4004    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4005    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4006      RegXMM } },
4007  { "pmovzxwq", 2, 0x660f3834, None, CpuSSE4_1,
4008    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4009    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4010      RegXMM } },
4011  { "pmovzxdq", 2, 0x660f3835, None, CpuSSE4_1,
4012    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4013    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4014      RegXMM } },
4015  { "pmuldq", 2, 0x660f3828, None, CpuSSE4_1,
4016    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4017    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4018      RegXMM } },
4019  { "pmulld", 2, 0x660f3840, None, CpuSSE4_1,
4020    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4021    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4022      RegXMM } },
4023  { "ptest", 2, 0x660f3817, None, CpuSSE4_1,
4024    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4025    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4026      RegXMM } },
4027  { "roundpd", 3, 0x660f3a09, None, CpuSSE4_1,
4028    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4029    { Imm8,
4030      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4031      RegXMM } },
4032  { "roundps", 3, 0x660f3a08, None, CpuSSE4_1,
4033    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4034    { Imm8,
4035      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4036      RegXMM } },
4037  { "roundsd", 3, 0x660f3a0b, None, CpuSSE4_1,
4038    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4039    { Imm8,
4040      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4041      RegXMM } },
4042  { "roundss", 3, 0x660f3a0a, None, CpuSSE4_1,
4043    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4044    { Imm8,
4045      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4046      RegXMM } },
4047  { "pcmpgtq", 2, 0x660f3837, None, CpuSSE4_2,
4048    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4049    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4050      RegXMM } },
4051  { "pcmpestri", 3, 0x660f3a61, None, CpuSSE4_2,
4052    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4053    { Imm8,
4054      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4055      RegXMM } },
4056  { "pcmpestrm", 3, 0x660f3a60, None, CpuSSE4_2,
4057    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4058    { Imm8,
4059      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4060      RegXMM } },
4061  { "pcmpistri", 3, 0x660f3a63, None, CpuSSE4_2,
4062    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4063    { Imm8,
4064      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4065      RegXMM } },
4066  { "pcmpistrm", 3, 0x660f3a62, None, CpuSSE4_2,
4067    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4068    { Imm8,
4069      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4070      RegXMM } },
4071  { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2,
4072    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
4073    { Reg16|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4074      Reg32 } },
4075  { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2|Cpu64,
4076    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|Rex64,
4077    { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4078      Reg64 } },
4079  { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2,
4080    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4081    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4082      Reg32 } },
4083  { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2|Cpu64,
4084    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
4085    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4086      Reg64 } },
4087  { "prefetch", 1, 0xf0d, 0x0, Cpu3dnow,
4088    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4089    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4090  { "prefetchw", 1, 0xf0d, 0x1, Cpu3dnow,
4091    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4092    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4093  { "femms", 0, 0xf0e, None, Cpu3dnow,
4094    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4095    { 0 } },
4096  { "pavgusb", 2, 0xf0f, 0xbf, Cpu3dnow,
4097    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4098    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4099      RegMMX } },
4100  { "pf2id", 2, 0xf0f, 0x1d, Cpu3dnow,
4101    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4102    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4103      RegMMX } },
4104  { "pf2iw", 2, 0xf0f, 0x1c, Cpu3dnowA,
4105    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4106    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4107      RegMMX } },
4108  { "pfacc", 2, 0xf0f, 0xae, Cpu3dnow,
4109    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4110    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4111      RegMMX } },
4112  { "pfadd", 2, 0xf0f, 0x9e, Cpu3dnow,
4113    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4114    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4115      RegMMX } },
4116  { "pfcmpeq", 2, 0xf0f, 0xb0, Cpu3dnow,
4117    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4118    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4119      RegMMX } },
4120  { "pfcmpge", 2, 0xf0f, 0x90, Cpu3dnow,
4121    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4122    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4123      RegMMX } },
4124  { "pfcmpgt", 2, 0xf0f, 0xa0, Cpu3dnow,
4125    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4126    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4127      RegMMX } },
4128  { "pfmax", 2, 0xf0f, 0xa4, Cpu3dnow,
4129    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4130    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4131      RegMMX } },
4132  { "pfmin", 2, 0xf0f, 0x94, Cpu3dnow,
4133    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4134    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4135      RegMMX } },
4136  { "pfmul", 2, 0xf0f, 0xb4, Cpu3dnow,
4137    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4138    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4139      RegMMX } },
4140  { "pfnacc", 2, 0xf0f, 0x8a, Cpu3dnowA,
4141    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4142    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4143      RegMMX } },
4144  { "pfpnacc", 2, 0xf0f, 0x8e, Cpu3dnowA,
4145    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4146    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4147      RegMMX } },
4148  { "pfrcp", 2, 0xf0f, 0x96, Cpu3dnow,
4149    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4150    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4151      RegMMX } },
4152  { "pfrcpit1", 2, 0xf0f, 0xa6, Cpu3dnow,
4153    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4154    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4155      RegMMX } },
4156  { "pfrcpit2", 2, 0xf0f, 0xb6, Cpu3dnow,
4157    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4158    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4159      RegMMX } },
4160  { "pfrsqit1", 2, 0xf0f, 0xa7, Cpu3dnow,
4161    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4162    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4163      RegMMX } },
4164  { "pfrsqrt", 2, 0xf0f, 0x97, Cpu3dnow,
4165    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4166    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4167      RegMMX } },
4168  { "pfsub", 2, 0xf0f, 0x9a, Cpu3dnow,
4169    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4170    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4171      RegMMX } },
4172  { "pfsubr", 2, 0xf0f, 0xaa, Cpu3dnow,
4173    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4174    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4175      RegMMX } },
4176  { "pi2fd", 2, 0xf0f, 0xd, Cpu3dnow,
4177    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4178    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4179      RegMMX } },
4180  { "pi2fw", 2, 0xf0f, 0xc, Cpu3dnowA,
4181    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4182    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4183      RegMMX } },
4184  { "pmulhrw", 2, 0xf0f, 0xb7, Cpu3dnow,
4185    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4186    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4187      RegMMX } },
4188  { "pswapd", 2, 0xf0f, 0xbb, Cpu3dnowA,
4189    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4190    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4191      RegMMX } },
4192  { "syscall", 0, 0xf05, None, CpuK6,
4193    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4194    { 0 } },
4195  { "sysret", 0, 0xf07, None, CpuK6,
4196    DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
4197    { 0 } },
4198  { "swapgs", 0, 0xf01, 0xf8, Cpu64,
4199    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4200    { 0 } },
4201  { "rdtscp", 0, 0xf01, 0xf9, CpuSledgehammer,
4202    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4203    { 0 } },
4204  { "clgi", 0, 0xf01, 0xdd, CpuSVME,
4205    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4206    { 0 } },
4207  { "invlpga", 0, 0xf01, 0xdf, CpuSVME,
4208    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4209    { 0 } },
4210  { "invlpga", 2, 0xf01, 0xdf, CpuSVME,
4211    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4212    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4213      Reg32 } },
4214  { "skinit", 0, 0xf01, 0xde, CpuSVME,
4215    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4216    { 0 } },
4217  { "skinit", 1, 0xf01, 0xde, CpuSVME,
4218    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4219    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4220  { "stgi", 0, 0xf01, 0xdc, CpuSVME,
4221    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4222    { 0 } },
4223  { "vmload", 0, 0xf01, 0xda, CpuSVME,
4224    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4225    { 0 } },
4226  { "vmload", 1, 0xf01, 0xda, CpuSVME,
4227    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4228    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4229  { "vmmcall", 0, 0xf01, 0xd9, CpuSVME,
4230    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4231    { 0 } },
4232  { "vmrun", 0, 0xf01, 0xd8, CpuSVME,
4233    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4234    { 0 } },
4235  { "vmrun", 1, 0xf01, 0xd8, CpuSVME,
4236    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4237    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4238  { "vmsave", 0, 0xf01, 0xdb, CpuSVME,
4239    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4240    { 0 } },
4241  { "vmsave", 1, 0xf01, 0xdb, CpuSVME,
4242    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4243    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4244  { "movntsd", 2, 0xf20f2b, None, CpuSSE4a,
4245    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4246    { RegXMM,
4247      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4248  { "movntss", 2, 0xf30f2b, None, CpuSSE4a,
4249    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4250    { RegXMM,
4251      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4252  { "extrq", 3, 0x660f78, 0x0, CpuSSE4a,
4253    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4254    { Imm8,
4255      Imm8,
4256      RegXMM } },
4257  { "extrq", 2, 0x660f79, None, CpuSSE4a,
4258    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4259    { RegXMM,
4260      RegXMM } },
4261  { "insertq", 2, 0xf20f79, None, CpuSSE4a,
4262    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4263    { RegXMM,
4264      RegXMM } },
4265  { "insertq", 4, 0xf20f78, None, CpuSSE4a,
4266    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4267    { Imm8,
4268      Imm8,
4269      RegXMM,
4270      RegXMM } },
4271  { "popcnt", 2, 0xf30fb8, None, CpuABM|CpuSSE4_2,
4272    Modrm|No_bSuf|No_sSuf|No_xSuf,
4273    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4274      Reg16|Reg32|Reg64 } },
4275  { "lzcnt", 2, 0xf30fbd, None, CpuABM,
4276    Modrm|No_bSuf|No_sSuf|No_xSuf,
4277    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4278      Reg16|Reg32|Reg64 } },
4279  { "xstore-rng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
4280    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4281    { 0 } },
4282  { "xcrypt-ecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock,
4283    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4284    { 0 } },
4285  { "xcrypt-cbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock,
4286    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4287    { 0 } },
4288  { "xcrypt-ctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock,
4289    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4290    { 0 } },
4291  { "xcrypt-cfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock,
4292    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4293    { 0 } },
4294  { "xcrypt-ofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock,
4295    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4296    { 0 } },
4297  { "montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock,
4298    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4299    { 0 } },
4300  { "xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock,
4301    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4302    { 0 } },
4303  { "xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock,
4304    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4305    { 0 } },
4306  { "xstorerng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
4307    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4308    { 0 } },
4309  { "xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock,
4310    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4311    { 0 } },
4312  { "xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock,
4313    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4314    { 0 } },
4315  { "xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock,
4316    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4317    { 0 } },
4318  { "xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock,
4319    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4320    { 0 } },
4321  { "xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock,
4322    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4323    { 0 } },
4324  { "xstore", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
4325    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4326    { 0 } },
4327  { "xgetbv", 0, 0xf01, 0xd0, CpuXSAVE,
4328    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4329    { 0 } },
4330  { "xsetbv", 0, 0xf01, 0xd1, CpuXSAVE,
4331    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4332    { 0 } },
4333  { "xsave", 1, 0xfae, 0x4, CpuXSAVE,
4334    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
4335    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4336  { "xsaveopt", 1, 0xfae, 0x6, CpuXSAVE,
4337    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
4338    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4339  { "xrstor", 1, 0xfae, 0x5, CpuXSAVE,
4340    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
4341    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4342  /* Intel AES extensions */
4343  {"aesdec", 2, 0x660f38de, None, CpuAES,
4344    Modrm|IgnoreSize|NoSuf,
4345    { RegXMM|LLongMem,
4346      RegXMM } },
4347  {"aesdeclast", 2, 0x660f38df, None, CpuAES,
4348    Modrm|IgnoreSize|NoSuf,
4349    { RegXMM|LLongMem,
4350      RegXMM } },
4351  {"aesenc", 2, 0x660f38dc, None, CpuAES,
4352    Modrm|IgnoreSize|NoSuf,
4353    { RegXMM|LLongMem,
4354      RegXMM } },
4355  {"aesenclast", 2, 0x660f38dd, None, CpuAES,
4356    Modrm|IgnoreSize|NoSuf,
4357    { RegXMM|LLongMem,
4358      RegXMM } },
4359  {"aesimc", 2, 0x660f38db, None, CpuAES,
4360    Modrm|IgnoreSize|NoSuf,
4361    { RegXMM|LLongMem,
4362      RegXMM } },
4363  {"aeskeygenassist", 3, 0x660f3adf, None, CpuAES,
4364    Modrm|IgnoreSize|NoSuf,
4365    { Imm8, RegXMM|LLongMem,
4366      RegXMM } },
4367
4368  /* Intel Carry-less Multiplication extensions */
4369  {"pclmulqdq", 3, 0x660f3a44, None, CpuPCLMUL,
4370    Modrm|IgnoreSize|NoSuf,
4371    { Imm8, RegXMM|LLongMem,
4372      RegXMM } },
4373  {"pclmullqlqdq", 2, 0x660f3a44, 0x0, CpuPCLMUL,
4374    Modrm|IgnoreSize|NoSuf|ImmExt,
4375    { RegXMM|LLongMem,
4376      RegXMM } },
4377  {"pclmulhqlqdq", 2, 0x660f3a44, 0x1, CpuPCLMUL,
4378    Modrm|IgnoreSize|NoSuf|ImmExt,
4379    { RegXMM|LLongMem,
4380      RegXMM } },
4381  {"pclmullqhqdq", 2, 0x660f3a44, 0x10, CpuPCLMUL,
4382    Modrm|IgnoreSize|NoSuf|ImmExt,
4383    { RegXMM|LLongMem,
4384      RegXMM } },
4385  {"pclmulhqhqdq", 2, 0x660f3a44, 0x11, CpuPCLMUL,
4386    Modrm|IgnoreSize|NoSuf|ImmExt,
4387    { RegXMM|LLongMem,
4388      RegXMM } },
4389
4390  /* Intel Random Number Generator extensions */
4391  {"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd,
4392    Modrm|NoSuf,
4393    { Reg16|Reg32|Reg64 } },
4394  {"rdseed", 1, 0x0fc7, 0x7, CpuRdRnd,
4395    Modrm|NoSuf,
4396    { Reg16|Reg32|Reg64 } },
4397
4398  /* Intel Supervisor Mode Access Prevention extensions */
4399  {"clac", 0, 0x0f01, 0xca, CpuSMAP,
4400    NoSuf|ImmExt, { 0, 0, 0 } },
4401  {"stac", 0, 0x0f01, 0xcb, CpuSMAP,
4402    NoSuf|ImmExt, { 0, 0, 0 } },
4403
4404  /* Read/write fs/gs segment base registers */
4405  {"rdfsbase", 1, 0xf30fae, 0x0, CpuFSGSBase|Cpu64,
4406    Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
4407    { Reg32|Reg64 } },
4408  {"rdgsbase", 1, 0xf30fae, 0x1, CpuFSGSBase|Cpu64,
4409    Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
4410    { Reg32|Reg64 } },
4411  {"wrfsbase", 1, 0xf30fae, 0x2, CpuFSGSBase|Cpu64,
4412    Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
4413    { Reg32|Reg64 } },
4414  {"wrgsbase", 1, 0xf30fae, 0x3, CpuFSGSBase|Cpu64,
4415    Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
4416    { Reg32|Reg64 } },
4417
4418  { NULL, 0, 0, 0, 0, 0, { 0 } }
4419};
4420
4421/* i386 register table.  */
4422
4423const reg_entry i386_regtab[] =
4424{
4425  { "st", FloatReg|FloatAcc, 0, 0 },
4426  { "al", Reg8|Acc, 0, 0 },
4427  { "cl", Reg8|ShiftCount, 0, 1 },
4428  { "dl", Reg8, 0, 2 },
4429  { "bl", Reg8, 0, 3 },
4430  { "ah", Reg8, 0, 4 },
4431  { "ch", Reg8, 0, 5 },
4432  { "dh", Reg8, 0, 6 },
4433  { "bh", Reg8, 0, 7 },
4434  { "axl", Reg8|Acc, RegRex64, 0 },
4435  { "cxl", Reg8, RegRex64, 1 },
4436  { "dxl", Reg8, RegRex64, 2 },
4437  { "bxl", Reg8, RegRex64, 3 },
4438  { "spl", Reg8, RegRex64, 4 },
4439  { "bpl", Reg8, RegRex64, 5 },
4440  { "sil", Reg8, RegRex64, 6 },
4441  { "dil", Reg8, RegRex64, 7 },
4442  { "r8b", Reg8, RegRex|RegRex64, 0 },
4443  { "r9b", Reg8, RegRex|RegRex64, 1 },
4444  { "r10b", Reg8, RegRex|RegRex64, 2 },
4445  { "r11b", Reg8, RegRex|RegRex64, 3 },
4446  { "r12b", Reg8, RegRex|RegRex64, 4 },
4447  { "r13b", Reg8, RegRex|RegRex64, 5 },
4448  { "r14b", Reg8, RegRex|RegRex64, 6 },
4449  { "r15b", Reg8, RegRex|RegRex64, 7 },
4450  { "ax", Reg16|Acc, 0, 0 },
4451  { "cx", Reg16, 0, 1 },
4452  { "dx", Reg16|InOutPortReg, 0, 2 },
4453  { "bx", Reg16|BaseIndex, 0, 3 },
4454  { "sp", Reg16, 0, 4 },
4455  { "bp", Reg16|BaseIndex, 0, 5 },
4456  { "si", Reg16|BaseIndex, 0, 6 },
4457  { "di", Reg16|BaseIndex, 0, 7 },
4458  { "r8w", Reg16, RegRex, 0 },
4459  { "r9w", Reg16, RegRex, 1 },
4460  { "r10w", Reg16, RegRex, 2 },
4461  { "r11w", Reg16, RegRex, 3 },
4462  { "r12w", Reg16, RegRex, 4 },
4463  { "r13w", Reg16, RegRex, 5 },
4464  { "r14w", Reg16, RegRex, 6 },
4465  { "r15w", Reg16, RegRex, 7 },
4466  { "eax", Reg32|BaseIndex|Acc, 0, 0 },
4467  { "ecx", Reg32|BaseIndex, 0, 1 },
4468  { "edx", Reg32|BaseIndex, 0, 2 },
4469  { "ebx", Reg32|BaseIndex, 0, 3 },
4470  { "esp", Reg32, 0, 4 },
4471  { "ebp", Reg32|BaseIndex, 0, 5 },
4472  { "esi", Reg32|BaseIndex, 0, 6 },
4473  { "edi", Reg32|BaseIndex, 0, 7 },
4474  { "r8d", Reg32|BaseIndex, RegRex, 0 },
4475  { "r9d", Reg32|BaseIndex, RegRex, 1 },
4476  { "r10d", Reg32|BaseIndex, RegRex, 2 },
4477  { "r11d", Reg32|BaseIndex, RegRex, 3 },
4478  { "r12d", Reg32|BaseIndex, RegRex, 4 },
4479  { "r13d", Reg32|BaseIndex, RegRex, 5 },
4480  { "r14d", Reg32|BaseIndex, RegRex, 6 },
4481  { "r15d", Reg32|BaseIndex, RegRex, 7 },
4482  { "rax", Reg64|BaseIndex|Acc, 0, 0 },
4483  { "rcx", Reg64|BaseIndex, 0, 1 },
4484  { "rdx", Reg64|BaseIndex, 0, 2 },
4485  { "rbx", Reg64|BaseIndex, 0, 3 },
4486  { "rsp", Reg64, 0, 4 },
4487  { "rbp", Reg64|BaseIndex, 0, 5 },
4488  { "rsi", Reg64|BaseIndex, 0, 6 },
4489  { "rdi", Reg64|BaseIndex, 0, 7 },
4490  { "r8", Reg64|BaseIndex, RegRex, 0 },
4491  { "r9", Reg64|BaseIndex, RegRex, 1 },
4492  { "r10", Reg64|BaseIndex, RegRex, 2 },
4493  { "r11", Reg64|BaseIndex, RegRex, 3 },
4494  { "r12", Reg64|BaseIndex, RegRex, 4 },
4495  { "r13", Reg64|BaseIndex, RegRex, 5 },
4496  { "r14", Reg64|BaseIndex, RegRex, 6 },
4497  { "r15", Reg64|BaseIndex, RegRex, 7 },
4498  { "es", SReg2, 0, 0 },
4499  { "cs", SReg2, 0, 1 },
4500  { "ss", SReg2, 0, 2 },
4501  { "ds", SReg2, 0, 3 },
4502  { "fs", SReg3, 0, 4 },
4503  { "gs", SReg3, 0, 5 },
4504  { "cr0", Control, 0, 0 },
4505  { "cr1", Control, 0, 1 },
4506  { "cr2", Control, 0, 2 },
4507  { "cr3", Control, 0, 3 },
4508  { "cr4", Control, 0, 4 },
4509  { "cr5", Control, 0, 5 },
4510  { "cr6", Control, 0, 6 },
4511  { "cr7", Control, 0, 7 },
4512  { "cr8", Control, RegRex, 0 },
4513  { "cr9", Control, RegRex, 1 },
4514  { "cr10", Control, RegRex, 2 },
4515  { "cr11", Control, RegRex, 3 },
4516  { "cr12", Control, RegRex, 4 },
4517  { "cr13", Control, RegRex, 5 },
4518  { "cr14", Control, RegRex, 6 },
4519  { "cr15", Control, RegRex, 7 },
4520  { "db0", Debug, 0, 0 },
4521  { "db1", Debug, 0, 1 },
4522  { "db2", Debug, 0, 2 },
4523  { "db3", Debug, 0, 3 },
4524  { "db4", Debug, 0, 4 },
4525  { "db5", Debug, 0, 5 },
4526  { "db6", Debug, 0, 6 },
4527  { "db7", Debug, 0, 7 },
4528  { "db8", Debug, RegRex, 0 },
4529  { "db9", Debug, RegRex, 1 },
4530  { "db10", Debug, RegRex, 2 },
4531  { "db11", Debug, RegRex, 3 },
4532  { "db12", Debug, RegRex, 4 },
4533  { "db13", Debug, RegRex, 5 },
4534  { "db14", Debug, RegRex, 6 },
4535  { "db15", Debug, RegRex, 7 },
4536  { "dr0", Debug, 0, 0 },
4537  { "dr1", Debug, 0, 1 },
4538  { "dr2", Debug, 0, 2 },
4539  { "dr3", Debug, 0, 3 },
4540  { "dr4", Debug, 0, 4 },
4541  { "dr5", Debug, 0, 5 },
4542  { "dr6", Debug, 0, 6 },
4543  { "dr7", Debug, 0, 7 },
4544  { "dr8", Debug, RegRex, 0 },
4545  { "dr9", Debug, RegRex, 1 },
4546  { "dr10", Debug, RegRex, 2 },
4547  { "dr11", Debug, RegRex, 3 },
4548  { "dr12", Debug, RegRex, 4 },
4549  { "dr13", Debug, RegRex, 5 },
4550  { "dr14", Debug, RegRex, 6 },
4551  { "dr15", Debug, RegRex, 7 },
4552  { "tr0", Test, 0, 0 },
4553  { "tr1", Test, 0, 1 },
4554  { "tr2", Test, 0, 2 },
4555  { "tr3", Test, 0, 3 },
4556  { "tr4", Test, 0, 4 },
4557  { "tr5", Test, 0, 5 },
4558  { "tr6", Test, 0, 6 },
4559  { "tr7", Test, 0, 7 },
4560  { "mm0", RegMMX, 0, 0 },
4561  { "mm1", RegMMX, 0, 1 },
4562  { "mm2", RegMMX, 0, 2 },
4563  { "mm3", RegMMX, 0, 3 },
4564  { "mm4", RegMMX, 0, 4 },
4565  { "mm5", RegMMX, 0, 5 },
4566  { "mm6", RegMMX, 0, 6 },
4567  { "mm7", RegMMX, 0, 7 },
4568  { "xmm0", RegXMM, 0, 0 },
4569  { "xmm1", RegXMM, 0, 1 },
4570  { "xmm2", RegXMM, 0, 2 },
4571  { "xmm3", RegXMM, 0, 3 },
4572  { "xmm4", RegXMM, 0, 4 },
4573  { "xmm5", RegXMM, 0, 5 },
4574  { "xmm6", RegXMM, 0, 6 },
4575  { "xmm7", RegXMM, 0, 7 },
4576  { "xmm8", RegXMM, RegRex, 0 },
4577  { "xmm9", RegXMM, RegRex, 1 },
4578  { "xmm10", RegXMM, RegRex, 2 },
4579  { "xmm11", RegXMM, RegRex, 3 },
4580  { "xmm12", RegXMM, RegRex, 4 },
4581  { "xmm13", RegXMM, RegRex, 5 },
4582  { "xmm14", RegXMM, RegRex, 6 },
4583  { "xmm15", RegXMM, RegRex, 7 },
4584  { "rip", BaseIndex, 0, 0 },
4585  { "st(0)", FloatReg|FloatAcc, 0, 0 },
4586  { "st(1)", FloatReg, 0, 1 },
4587  { "st(2)", FloatReg, 0, 2 },
4588  { "st(3)", FloatReg, 0, 3 },
4589  { "st(4)", FloatReg, 0, 4 },
4590  { "st(5)", FloatReg, 0, 5 },
4591  { "st(6)", FloatReg, 0, 6 },
4592  { "st(7)", FloatReg, 0, 7 },
4593};
4594
4595const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);
4596