1@c Copyright 2002, 2003, 2005
2@c Free Software Foundation, Inc.
3@c   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4@c This is part of the GAS manual.
5@c For copying conditions, see the file as.texinfo.
6
7@ifset GENERIC
8@page
9@node IA-64-Dependent
10@chapter IA-64 Dependent Features
11@end ifset
12
13@ifclear GENERIC
14@node Machine Dependencies
15@chapter IA-64 Dependent Features
16@end ifclear
17
18@cindex IA-64 support
19@menu
20* IA-64 Options::              Options
21* IA-64 Syntax::               Syntax
22@c * IA-64 Floating Point::       Floating Point		// to be written
23@c * IA-64 Directives::           IA-64 Machine Directives	// to be written
24* IA-64 Opcodes::              Opcodes
25@end menu
26
27@node IA-64 Options
28@section Options
29@cindex IA-64 options
30@cindex options for IA-64
31
32@table @option
33@cindex @code{-mconstant-gp} command line option, IA-64
34
35@item -mconstant-gp
36This option instructs the assembler to mark the resulting object file
37as using the ``constant GP'' model.  With this model, it is assumed
38that the entire program uses a single global pointer (GP) value.  Note
39that this option does not in any fashion affect the machine code
40emitted by the assembler.  All it does is turn on the EF_IA_64_CONS_GP
41flag in the ELF file header.
42
43@item -mauto-pic
44This option instructs the assembler to mark the resulting object file
45as using the ``constant GP without function descriptor'' data model.
46This model is like the ``constant GP'' model, except that it
47additionally does away with function descriptors.  What this means is
48that the address of a function refers directly to the function's code
49entry-point.  Normally, such an address would refer to a function
50descriptor, which contains both the code entry-point and the GP-value
51needed by the function.  Note that this option does not in any fashion
52affect the machine code emitted by the assembler.  All it does is
53turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.
54
55@item -milp32
56@item -milp64
57@item -mlp64
58@item -mp64
59These options select the data model.  The assembler defaults to @code{-mlp64}
60(LP64 data model).
61
62@item -mle
63@item -mbe
64These options select the byte order.  The @code{-mle} option selects little-endian
65byte order (default) and @code{-mbe} selects big-endian byte order.  Note that
66IA-64 machine code always uses little-endian byte order.
67
68@item -mtune=itanium1
69@item -mtune=itanium2
70Tune for a particular IA-64 CPU, @var{itanium1} or @var{itanium2}. The
71default is @var{itanium2}.
72
73@item -munwind-check=warning
74@item -munwind-check=error
75These options control what the assembler will do when performing
76consistency checks on unwind directives.  @code{-munwind-check=warning}
77will make the assembler issue a warning when an unwind directive check
78fails.  This is the default.  @code{-munwind-check=error} will make the
79assembler issue an error when an unwind directive check fails.
80
81@item -mhint.b=ok
82@item -mhint.b=warning
83@item -mhint.b=error
84These options control what the assembler will do when the @samp{hint.b}
85instruction is used.  @code{-mhint.b=ok} will make the assembler accept
86@samp{hint.b}.  @code{-mint.b=warning} will make the assembler issue a
87warning when @samp{hint.b} is used.  @code{-mhint.b=error} will make
88the assembler treat @samp{hint.b} as an error, which is the default.
89
90@item -x
91@item -xexplicit
92These options turn on dependency violation checking.
93
94@item -xauto
95This option instructs the assembler to automatically insert stop bits where necessary
96to remove dependency violations.  This is the default mode.
97
98@item -xnone
99This option turns off dependency violation checking.
100
101@item -xdebug
102This turns on debug output intended to help tracking down bugs in the dependency
103violation checker.
104
105@item -xdebugn
106This is a shortcut for -xnone -xdebug.
107
108@item -xdebugx
109This is a shortcut for -xexplicit -xdebug.
110
111@end table
112
113@cindex IA-64 Syntax
114@node IA-64 Syntax
115@section Syntax
116The assembler syntax closely follows the IA-64 Assembly Language
117Reference Guide.
118
119@menu
120* IA-64-Chars::                Special Characters
121* IA-64-Regs::                 Register Names
122* IA-64-Bits::                 Bit Names
123@c * IA-64-Relocs::               Relocations		// to be written
124@end menu
125
126@node IA-64-Chars
127@subsection Special Characters
128
129@cindex line comment character, IA-64
130@cindex IA-64 line comment character
131@samp{//} is the line comment token.
132
133@cindex line separator, IA-64
134@cindex statement separator, IA-64
135@cindex IA-64 line separator
136@samp{;} can be used instead of a newline to separate statements.
137
138@node IA-64-Regs
139@subsection Register Names
140@cindex IA-64 registers
141@cindex register names, IA-64
142
143The 128 integer registers are referred to as @samp{r@var{n}}.
144The 128 floating-point registers are referred to as @samp{f@var{n}}.
145The 128 application registers are referred to as @samp{ar@var{n}}.
146The 128 control registers are referred to as @samp{cr@var{n}}.
147The 64 one-bit predicate registers are referred to as @samp{p@var{n}}.
148The 8 branch registers are referred to as @samp{b@var{n}}.
149In addition, the assembler defines a number of aliases:
150@samp{gp} (@samp{r1}), @samp{sp} (@samp{r12}), @samp{rp} (@samp{b0}),
151@samp{ret0} (@samp{r8}), @samp{ret1} (@samp{r9}), @samp{ret2} (@samp{r10}),
152@samp{ret3} (@samp{r9}), @samp{farg@var{n}} (@samp{f8+@var{n}}), and
153@samp{fret@var{n}} (@samp{f8+@var{n}}).
154
155For convenience, the assembler also defines aliases for all named application
156and control registers.  For example, @samp{ar.bsp} refers to the register
157backing store pointer (@samp{ar17}).  Similarly, @samp{cr.eoi} refers to
158the end-of-interrupt register (@samp{cr67}).
159
160@node IA-64-Bits
161@subsection IA-64 Processor-Status-Register (PSR) Bit Names
162@cindex IA-64 Processor-status-Register bit names
163@cindex PSR bits
164@cindex bit names, IA-64
165
166The assembler defines bit masks for each of the bits in the IA-64
167processor status register.  For example, @samp{psr.ic} corresponds to
168a value of 0x2000.  These masks are primarily intended for use with
169the @samp{ssm}/@samp{sum} and @samp{rsm}/@samp{rum}
170instructions, but they can be used anywhere else where an integer
171constant is expected.
172
173@node IA-64 Opcodes
174@section Opcodes
175For detailed information on the IA-64 machine instruction set, see the
176@c Attempt to work around a very overfull hbox.
177@iftex
178IA-64 Assembly Language Reference Guide available at
179@smallfonts
180@example
181http://developer.intel.com/design/itanium/arch_spec.htm
182@end example
183@textfonts
184@end iftex
185@ifnottex
186@uref{http://developer.intel.com/design/itanium/arch_spec.htm,IA-64 Architecture Handbook}.
187@end ifnottex
188