1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/10.3/usr.sbin/bhyve/pci_emul.c 293408 2016-01-08 02:54:21Z araujo $ 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: releng/10.3/usr.sbin/bhyve/pci_emul.c 293408 2016-01-08 02:54:21Z araujo $"); 31 32#include <sys/param.h> 33#include <sys/linker_set.h> 34#include <sys/errno.h> 35 36#include <ctype.h> 37#include <pthread.h> 38#include <stdio.h> 39#include <stdlib.h> 40#include <string.h> 41#include <strings.h> 42#include <assert.h> 43#include <stdbool.h> 44 45#include <machine/vmm.h> 46#include <vmmapi.h> 47 48#include "acpi.h" 49#include "bhyverun.h" 50#include "inout.h" 51#include "ioapic.h" 52#include "mem.h" 53#include "pci_emul.h" 54#include "pci_irq.h" 55#include "pci_lpc.h" 56 57#define CONF1_ADDR_PORT 0x0cf8 58#define CONF1_DATA_PORT 0x0cfc 59 60#define CONF1_ENABLE 0x80000000ul 61 62#define MAXBUSES (PCI_BUSMAX + 1) 63#define MAXSLOTS (PCI_SLOTMAX + 1) 64#define MAXFUNCS (PCI_FUNCMAX + 1) 65 66struct funcinfo { 67 char *fi_name; 68 char *fi_param; 69 struct pci_devinst *fi_devi; 70}; 71 72struct intxinfo { 73 int ii_count; 74 int ii_pirq_pin; 75 int ii_ioapic_irq; 76}; 77 78struct slotinfo { 79 struct intxinfo si_intpins[4]; 80 struct funcinfo si_funcs[MAXFUNCS]; 81}; 82 83struct businfo { 84 uint16_t iobase, iolimit; /* I/O window */ 85 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 86 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 87 struct slotinfo slotinfo[MAXSLOTS]; 88}; 89 90static struct businfo *pci_businfo[MAXBUSES]; 91 92SET_DECLARE(pci_devemu_set, struct pci_devemu); 93 94static uint64_t pci_emul_iobase; 95static uint64_t pci_emul_membase32; 96static uint64_t pci_emul_membase64; 97 98#define PCI_EMUL_IOBASE 0x2000 99#define PCI_EMUL_IOLIMIT 0x10000 100 101#define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 102#define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 103SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 104 105#define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 106 107#define PCI_EMUL_MEMBASE64 0xD000000000UL 108#define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 109 110static struct pci_devemu *pci_emul_finddev(char *name); 111static void pci_lintr_route(struct pci_devinst *pi); 112static void pci_lintr_update(struct pci_devinst *pi); 113static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, 114 int func, int coff, int bytes, uint32_t *val); 115 116static __inline void 117CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 118{ 119 120 if (bytes == 1) 121 pci_set_cfgdata8(pi, coff, val); 122 else if (bytes == 2) 123 pci_set_cfgdata16(pi, coff, val); 124 else 125 pci_set_cfgdata32(pi, coff, val); 126} 127 128static __inline uint32_t 129CFGREAD(struct pci_devinst *pi, int coff, int bytes) 130{ 131 132 if (bytes == 1) 133 return (pci_get_cfgdata8(pi, coff)); 134 else if (bytes == 2) 135 return (pci_get_cfgdata16(pi, coff)); 136 else 137 return (pci_get_cfgdata32(pi, coff)); 138} 139 140/* 141 * I/O access 142 */ 143 144/* 145 * Slot options are in the form: 146 * 147 * <bus>:<slot>:<func>,<emul>[,<config>] 148 * <slot>[:<func>],<emul>[,<config>] 149 * 150 * slot is 0..31 151 * func is 0..7 152 * emul is a string describing the type of PCI device e.g. virtio-net 153 * config is an optional string, depending on the device, that can be 154 * used for configuration. 155 * Examples are: 156 * 1,virtio-net,tap0 157 * 3:0,dummy 158 */ 159static void 160pci_parse_slot_usage(char *aopt) 161{ 162 163 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 164} 165 166int 167pci_parse_slot(char *opt) 168{ 169 struct businfo *bi; 170 struct slotinfo *si; 171 char *emul, *config, *str, *cp; 172 int error, bnum, snum, fnum; 173 174 error = -1; 175 str = strdup(opt); 176 177 emul = config = NULL; 178 if ((cp = strchr(str, ',')) != NULL) { 179 *cp = '\0'; 180 emul = cp + 1; 181 if ((cp = strchr(emul, ',')) != NULL) { 182 *cp = '\0'; 183 config = cp + 1; 184 } 185 } else { 186 pci_parse_slot_usage(opt); 187 goto done; 188 } 189 190 /* <bus>:<slot>:<func> */ 191 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 192 bnum = 0; 193 /* <slot>:<func> */ 194 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 195 fnum = 0; 196 /* <slot> */ 197 if (sscanf(str, "%d", &snum) != 1) { 198 snum = -1; 199 } 200 } 201 } 202 203 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 204 fnum < 0 || fnum >= MAXFUNCS) { 205 pci_parse_slot_usage(opt); 206 goto done; 207 } 208 209 if (pci_businfo[bnum] == NULL) 210 pci_businfo[bnum] = calloc(1, sizeof(struct businfo)); 211 212 bi = pci_businfo[bnum]; 213 si = &bi->slotinfo[snum]; 214 215 if (si->si_funcs[fnum].fi_name != NULL) { 216 fprintf(stderr, "pci slot %d:%d already occupied!\n", 217 snum, fnum); 218 goto done; 219 } 220 221 if (pci_emul_finddev(emul) == NULL) { 222 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 223 snum, fnum, emul); 224 goto done; 225 } 226 227 error = 0; 228 si->si_funcs[fnum].fi_name = emul; 229 si->si_funcs[fnum].fi_param = config; 230 231done: 232 if (error) 233 free(str); 234 235 return (error); 236} 237 238static int 239pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 240{ 241 242 if (offset < pi->pi_msix.pba_offset) 243 return (0); 244 245 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 246 return (0); 247 } 248 249 return (1); 250} 251 252int 253pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 254 uint64_t value) 255{ 256 int msix_entry_offset; 257 int tab_index; 258 char *dest; 259 260 /* support only 4 or 8 byte writes */ 261 if (size != 4 && size != 8) 262 return (-1); 263 264 /* 265 * Return if table index is beyond what device supports 266 */ 267 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 268 if (tab_index >= pi->pi_msix.table_count) 269 return (-1); 270 271 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 272 273 /* support only aligned writes */ 274 if ((msix_entry_offset % size) != 0) 275 return (-1); 276 277 dest = (char *)(pi->pi_msix.table + tab_index); 278 dest += msix_entry_offset; 279 280 if (size == 4) 281 *((uint32_t *)dest) = value; 282 else 283 *((uint64_t *)dest) = value; 284 285 return (0); 286} 287 288uint64_t 289pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 290{ 291 char *dest; 292 int msix_entry_offset; 293 int tab_index; 294 uint64_t retval = ~0; 295 296 /* 297 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 298 * table but we also allow 1 byte access to accommodate reads from 299 * ddb. 300 */ 301 if (size != 1 && size != 4 && size != 8) 302 return (retval); 303 304 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 305 306 /* support only aligned reads */ 307 if ((msix_entry_offset % size) != 0) { 308 return (retval); 309 } 310 311 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 312 313 if (tab_index < pi->pi_msix.table_count) { 314 /* valid MSI-X Table access */ 315 dest = (char *)(pi->pi_msix.table + tab_index); 316 dest += msix_entry_offset; 317 318 if (size == 1) 319 retval = *((uint8_t *)dest); 320 else if (size == 4) 321 retval = *((uint32_t *)dest); 322 else 323 retval = *((uint64_t *)dest); 324 } else if (pci_valid_pba_offset(pi, offset)) { 325 /* return 0 for PBA access */ 326 retval = 0; 327 } 328 329 return (retval); 330} 331 332int 333pci_msix_table_bar(struct pci_devinst *pi) 334{ 335 336 if (pi->pi_msix.table != NULL) 337 return (pi->pi_msix.table_bar); 338 else 339 return (-1); 340} 341 342int 343pci_msix_pba_bar(struct pci_devinst *pi) 344{ 345 346 if (pi->pi_msix.table != NULL) 347 return (pi->pi_msix.pba_bar); 348 else 349 return (-1); 350} 351 352static int 353pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 354 uint32_t *eax, void *arg) 355{ 356 struct pci_devinst *pdi = arg; 357 struct pci_devemu *pe = pdi->pi_d; 358 uint64_t offset; 359 int i; 360 361 for (i = 0; i <= PCI_BARMAX; i++) { 362 if (pdi->pi_bar[i].type == PCIBAR_IO && 363 port >= pdi->pi_bar[i].addr && 364 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 365 offset = port - pdi->pi_bar[i].addr; 366 if (in) 367 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 368 offset, bytes); 369 else 370 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 371 bytes, *eax); 372 return (0); 373 } 374 } 375 return (-1); 376} 377 378static int 379pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 380 int size, uint64_t *val, void *arg1, long arg2) 381{ 382 struct pci_devinst *pdi = arg1; 383 struct pci_devemu *pe = pdi->pi_d; 384 uint64_t offset; 385 int bidx = (int) arg2; 386 387 assert(bidx <= PCI_BARMAX); 388 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 389 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 390 assert(addr >= pdi->pi_bar[bidx].addr && 391 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 392 393 offset = addr - pdi->pi_bar[bidx].addr; 394 395 if (dir == MEM_F_WRITE) { 396 if (size == 8) { 397 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 398 4, *val & 0xffffffff); 399 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4, 400 4, *val >> 32); 401 } else { 402 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 403 size, *val); 404 } 405 } else { 406 if (size == 8) { 407 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 408 offset, 4); 409 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 410 offset + 4, 4) << 32; 411 } else { 412 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 413 offset, size); 414 } 415 } 416 417 return (0); 418} 419 420 421static int 422pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 423 uint64_t *addr) 424{ 425 uint64_t base; 426 427 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 428 429 base = roundup2(*baseptr, size); 430 431 if (base + size <= limit) { 432 *addr = base; 433 *baseptr = base + size; 434 return (0); 435 } else 436 return (-1); 437} 438 439int 440pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 441 uint64_t size) 442{ 443 444 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 445} 446 447/* 448 * Register (or unregister) the MMIO or I/O region associated with the BAR 449 * register 'idx' of an emulated pci device. 450 */ 451static void 452modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 453{ 454 int error; 455 struct inout_port iop; 456 struct mem_range mr; 457 458 switch (pi->pi_bar[idx].type) { 459 case PCIBAR_IO: 460 bzero(&iop, sizeof(struct inout_port)); 461 iop.name = pi->pi_name; 462 iop.port = pi->pi_bar[idx].addr; 463 iop.size = pi->pi_bar[idx].size; 464 if (registration) { 465 iop.flags = IOPORT_F_INOUT; 466 iop.handler = pci_emul_io_handler; 467 iop.arg = pi; 468 error = register_inout(&iop); 469 } else 470 error = unregister_inout(&iop); 471 break; 472 case PCIBAR_MEM32: 473 case PCIBAR_MEM64: 474 bzero(&mr, sizeof(struct mem_range)); 475 mr.name = pi->pi_name; 476 mr.base = pi->pi_bar[idx].addr; 477 mr.size = pi->pi_bar[idx].size; 478 if (registration) { 479 mr.flags = MEM_F_RW; 480 mr.handler = pci_emul_mem_handler; 481 mr.arg1 = pi; 482 mr.arg2 = idx; 483 error = register_mem(&mr); 484 } else 485 error = unregister_mem(&mr); 486 break; 487 default: 488 error = EINVAL; 489 break; 490 } 491 assert(error == 0); 492} 493 494static void 495unregister_bar(struct pci_devinst *pi, int idx) 496{ 497 498 modify_bar_registration(pi, idx, 0); 499} 500 501static void 502register_bar(struct pci_devinst *pi, int idx) 503{ 504 505 modify_bar_registration(pi, idx, 1); 506} 507 508/* Are we decoding i/o port accesses for the emulated pci device? */ 509static int 510porten(struct pci_devinst *pi) 511{ 512 uint16_t cmd; 513 514 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 515 516 return (cmd & PCIM_CMD_PORTEN); 517} 518 519/* Are we decoding memory accesses for the emulated pci device? */ 520static int 521memen(struct pci_devinst *pi) 522{ 523 uint16_t cmd; 524 525 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 526 527 return (cmd & PCIM_CMD_MEMEN); 528} 529 530/* 531 * Update the MMIO or I/O address that is decoded by the BAR register. 532 * 533 * If the pci device has enabled the address space decoding then intercept 534 * the address range decoded by the BAR register. 535 */ 536static void 537update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 538{ 539 int decode; 540 541 if (pi->pi_bar[idx].type == PCIBAR_IO) 542 decode = porten(pi); 543 else 544 decode = memen(pi); 545 546 if (decode) 547 unregister_bar(pi, idx); 548 549 switch (type) { 550 case PCIBAR_IO: 551 case PCIBAR_MEM32: 552 pi->pi_bar[idx].addr = addr; 553 break; 554 case PCIBAR_MEM64: 555 pi->pi_bar[idx].addr &= ~0xffffffffUL; 556 pi->pi_bar[idx].addr |= addr; 557 break; 558 case PCIBAR_MEMHI64: 559 pi->pi_bar[idx].addr &= 0xffffffff; 560 pi->pi_bar[idx].addr |= addr; 561 break; 562 default: 563 assert(0); 564 } 565 566 if (decode) 567 register_bar(pi, idx); 568} 569 570int 571pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 572 enum pcibar_type type, uint64_t size) 573{ 574 int error; 575 uint64_t *baseptr, limit, addr, mask, lobits, bar; 576 577 assert(idx >= 0 && idx <= PCI_BARMAX); 578 579 if ((size & (size - 1)) != 0) 580 size = 1UL << flsl(size); /* round up to a power of 2 */ 581 582 /* Enforce minimum BAR sizes required by the PCI standard */ 583 if (type == PCIBAR_IO) { 584 if (size < 4) 585 size = 4; 586 } else { 587 if (size < 16) 588 size = 16; 589 } 590 591 switch (type) { 592 case PCIBAR_NONE: 593 baseptr = NULL; 594 addr = mask = lobits = 0; 595 break; 596 case PCIBAR_IO: 597 baseptr = &pci_emul_iobase; 598 limit = PCI_EMUL_IOLIMIT; 599 mask = PCIM_BAR_IO_BASE; 600 lobits = PCIM_BAR_IO_SPACE; 601 break; 602 case PCIBAR_MEM64: 603 /* 604 * XXX 605 * Some drivers do not work well if the 64-bit BAR is allocated 606 * above 4GB. Allow for this by allocating small requests under 607 * 4GB unless then allocation size is larger than some arbitrary 608 * number (32MB currently). 609 */ 610 if (size > 32 * 1024 * 1024) { 611 /* 612 * XXX special case for device requiring peer-peer DMA 613 */ 614 if (size == 0x100000000UL) 615 baseptr = &hostbase; 616 else 617 baseptr = &pci_emul_membase64; 618 limit = PCI_EMUL_MEMLIMIT64; 619 mask = PCIM_BAR_MEM_BASE; 620 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 621 PCIM_BAR_MEM_PREFETCH; 622 break; 623 } else { 624 baseptr = &pci_emul_membase32; 625 limit = PCI_EMUL_MEMLIMIT32; 626 mask = PCIM_BAR_MEM_BASE; 627 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 628 } 629 break; 630 case PCIBAR_MEM32: 631 baseptr = &pci_emul_membase32; 632 limit = PCI_EMUL_MEMLIMIT32; 633 mask = PCIM_BAR_MEM_BASE; 634 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 635 break; 636 default: 637 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 638 assert(0); 639 } 640 641 if (baseptr != NULL) { 642 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 643 if (error != 0) 644 return (error); 645 } 646 647 pdi->pi_bar[idx].type = type; 648 pdi->pi_bar[idx].addr = addr; 649 pdi->pi_bar[idx].size = size; 650 651 /* Initialize the BAR register in config space */ 652 bar = (addr & mask) | lobits; 653 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 654 655 if (type == PCIBAR_MEM64) { 656 assert(idx + 1 <= PCI_BARMAX); 657 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 658 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 659 } 660 661 register_bar(pdi, idx); 662 663 return (0); 664} 665 666#define CAP_START_OFFSET 0x40 667static int 668pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 669{ 670 int i, capoff, reallen; 671 uint16_t sts; 672 673 assert(caplen > 0); 674 675 reallen = roundup2(caplen, 4); /* dword aligned */ 676 677 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 678 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 679 capoff = CAP_START_OFFSET; 680 else 681 capoff = pi->pi_capend + 1; 682 683 /* Check if we have enough space */ 684 if (capoff + reallen > PCI_REGMAX + 1) 685 return (-1); 686 687 /* Set the previous capability pointer */ 688 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 689 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 690 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 691 } else 692 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 693 694 /* Copy the capability */ 695 for (i = 0; i < caplen; i++) 696 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 697 698 /* Set the next capability pointer */ 699 pci_set_cfgdata8(pi, capoff + 1, 0); 700 701 pi->pi_prevcap = capoff; 702 pi->pi_capend = capoff + reallen - 1; 703 return (0); 704} 705 706static struct pci_devemu * 707pci_emul_finddev(char *name) 708{ 709 struct pci_devemu **pdpp, *pdp; 710 711 SET_FOREACH(pdpp, pci_devemu_set) { 712 pdp = *pdpp; 713 if (!strcmp(pdp->pe_emu, name)) { 714 return (pdp); 715 } 716 } 717 718 return (NULL); 719} 720 721static int 722pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 723 int func, struct funcinfo *fi) 724{ 725 struct pci_devinst *pdi; 726 int err; 727 728 pdi = calloc(1, sizeof(struct pci_devinst)); 729 730 pdi->pi_vmctx = ctx; 731 pdi->pi_bus = bus; 732 pdi->pi_slot = slot; 733 pdi->pi_func = func; 734 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 735 pdi->pi_lintr.pin = 0; 736 pdi->pi_lintr.state = IDLE; 737 pdi->pi_lintr.pirq_pin = 0; 738 pdi->pi_lintr.ioapic_irq = 0; 739 pdi->pi_d = pde; 740 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 741 742 /* Disable legacy interrupts */ 743 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 744 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 745 746 pci_set_cfgdata8(pdi, PCIR_COMMAND, 747 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 748 749 err = (*pde->pe_init)(ctx, pdi, fi->fi_param); 750 if (err == 0) 751 fi->fi_devi = pdi; 752 else 753 free(pdi); 754 755 return (err); 756} 757 758void 759pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 760{ 761 int mmc; 762 763 CTASSERT(sizeof(struct msicap) == 14); 764 765 /* Number of msi messages must be a power of 2 between 1 and 32 */ 766 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 767 mmc = ffs(msgnum) - 1; 768 769 bzero(msicap, sizeof(struct msicap)); 770 msicap->capid = PCIY_MSI; 771 msicap->nextptr = nextptr; 772 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 773} 774 775int 776pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 777{ 778 struct msicap msicap; 779 780 pci_populate_msicap(&msicap, msgnum, 0); 781 782 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 783} 784 785static void 786pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 787 uint32_t msix_tab_size) 788{ 789 CTASSERT(sizeof(struct msixcap) == 12); 790 791 assert(msix_tab_size % 4096 == 0); 792 793 bzero(msixcap, sizeof(struct msixcap)); 794 msixcap->capid = PCIY_MSIX; 795 796 /* 797 * Message Control Register, all fields set to 798 * zero except for the Table Size. 799 * Note: Table size N is encoded as N-1 800 */ 801 msixcap->msgctrl = msgnum - 1; 802 803 /* 804 * MSI-X BAR setup: 805 * - MSI-X table start at offset 0 806 * - PBA table starts at a 4K aligned offset after the MSI-X table 807 */ 808 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 809 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 810} 811 812static void 813pci_msix_table_init(struct pci_devinst *pi, int table_entries) 814{ 815 int i, table_size; 816 817 assert(table_entries > 0); 818 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 819 820 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 821 pi->pi_msix.table = calloc(1, table_size); 822 823 /* set mask bit of vector control register */ 824 for (i = 0; i < table_entries; i++) 825 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 826} 827 828int 829pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 830{ 831 uint32_t tab_size; 832 struct msixcap msixcap; 833 834 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 835 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 836 837 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 838 839 /* Align table size to nearest 4K */ 840 tab_size = roundup2(tab_size, 4096); 841 842 pi->pi_msix.table_bar = barnum; 843 pi->pi_msix.pba_bar = barnum; 844 pi->pi_msix.table_offset = 0; 845 pi->pi_msix.table_count = msgnum; 846 pi->pi_msix.pba_offset = tab_size; 847 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 848 849 pci_msix_table_init(pi, msgnum); 850 851 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 852 853 /* allocate memory for MSI-X Table and PBA */ 854 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 855 tab_size + pi->pi_msix.pba_size); 856 857 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 858 sizeof(msixcap))); 859} 860 861void 862msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 863 int bytes, uint32_t val) 864{ 865 uint16_t msgctrl, rwmask; 866 int off; 867 868 off = offset - capoff; 869 /* Message Control Register */ 870 if (off == 2 && bytes == 2) { 871 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 872 msgctrl = pci_get_cfgdata16(pi, offset); 873 msgctrl &= ~rwmask; 874 msgctrl |= val & rwmask; 875 val = msgctrl; 876 877 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 878 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 879 pci_lintr_update(pi); 880 } 881 882 CFGWRITE(pi, offset, val, bytes); 883} 884 885void 886msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 887 int bytes, uint32_t val) 888{ 889 uint16_t msgctrl, rwmask, msgdata, mme; 890 uint32_t addrlo; 891 892 /* 893 * If guest is writing to the message control register make sure 894 * we do not overwrite read-only fields. 895 */ 896 if ((offset - capoff) == 2 && bytes == 2) { 897 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 898 msgctrl = pci_get_cfgdata16(pi, offset); 899 msgctrl &= ~rwmask; 900 msgctrl |= val & rwmask; 901 val = msgctrl; 902 903 addrlo = pci_get_cfgdata32(pi, capoff + 4); 904 if (msgctrl & PCIM_MSICTRL_64BIT) 905 msgdata = pci_get_cfgdata16(pi, capoff + 12); 906 else 907 msgdata = pci_get_cfgdata16(pi, capoff + 8); 908 909 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 910 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 911 if (pi->pi_msi.enabled) { 912 pi->pi_msi.addr = addrlo; 913 pi->pi_msi.msg_data = msgdata; 914 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 915 } else { 916 pi->pi_msi.maxmsgnum = 0; 917 } 918 pci_lintr_update(pi); 919 } 920 921 CFGWRITE(pi, offset, val, bytes); 922} 923 924void 925pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 926 int bytes, uint32_t val) 927{ 928 929 /* XXX don't write to the readonly parts */ 930 CFGWRITE(pi, offset, val, bytes); 931} 932 933#define PCIECAP_VERSION 0x2 934int 935pci_emul_add_pciecap(struct pci_devinst *pi, int type) 936{ 937 int err; 938 struct pciecap pciecap; 939 940 CTASSERT(sizeof(struct pciecap) == 60); 941 942 if (type != PCIEM_TYPE_ROOT_PORT) 943 return (-1); 944 945 bzero(&pciecap, sizeof(pciecap)); 946 947 pciecap.capid = PCIY_EXPRESS; 948 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; 949 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 950 pciecap.link_status = 0x11; /* gen1, x1 */ 951 952 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 953 return (err); 954} 955 956/* 957 * This function assumes that 'coff' is in the capabilities region of the 958 * config space. 959 */ 960static void 961pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 962{ 963 int capid; 964 uint8_t capoff, nextoff; 965 966 /* Do not allow un-aligned writes */ 967 if ((offset & (bytes - 1)) != 0) 968 return; 969 970 /* Find the capability that we want to update */ 971 capoff = CAP_START_OFFSET; 972 while (1) { 973 nextoff = pci_get_cfgdata8(pi, capoff + 1); 974 if (nextoff == 0) 975 break; 976 if (offset >= capoff && offset < nextoff) 977 break; 978 979 capoff = nextoff; 980 } 981 assert(offset >= capoff); 982 983 /* 984 * Capability ID and Next Capability Pointer are readonly. 985 * However, some o/s's do 4-byte writes that include these. 986 * For this case, trim the write back to 2 bytes and adjust 987 * the data. 988 */ 989 if (offset == capoff || offset == capoff + 1) { 990 if (offset == capoff && bytes == 4) { 991 bytes = 2; 992 offset += 2; 993 val >>= 16; 994 } else 995 return; 996 } 997 998 capid = pci_get_cfgdata8(pi, capoff); 999 switch (capid) { 1000 case PCIY_MSI: 1001 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1002 break; 1003 case PCIY_MSIX: 1004 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1005 break; 1006 case PCIY_EXPRESS: 1007 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1008 break; 1009 default: 1010 break; 1011 } 1012} 1013 1014static int 1015pci_emul_iscap(struct pci_devinst *pi, int offset) 1016{ 1017 uint16_t sts; 1018 1019 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1020 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1021 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1022 return (1); 1023 } 1024 return (0); 1025} 1026 1027static int 1028pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1029 int size, uint64_t *val, void *arg1, long arg2) 1030{ 1031 /* 1032 * Ignore writes; return 0xff's for reads. The mem read code 1033 * will take care of truncating to the correct size. 1034 */ 1035 if (dir == MEM_F_READ) { 1036 *val = 0xffffffffffffffff; 1037 } 1038 1039 return (0); 1040} 1041 1042static int 1043pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1044 int bytes, uint64_t *val, void *arg1, long arg2) 1045{ 1046 int bus, slot, func, coff, in; 1047 1048 coff = addr & 0xfff; 1049 func = (addr >> 12) & 0x7; 1050 slot = (addr >> 15) & 0x1f; 1051 bus = (addr >> 20) & 0xff; 1052 in = (dir == MEM_F_READ); 1053 if (in) 1054 *val = ~0UL; 1055 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val); 1056 return (0); 1057} 1058 1059uint64_t 1060pci_ecfg_base(void) 1061{ 1062 1063 return (PCI_EMUL_ECFG_BASE); 1064} 1065 1066#define BUSIO_ROUNDUP 32 1067#define BUSMEM_ROUNDUP (1024 * 1024) 1068 1069int 1070init_pci(struct vmctx *ctx) 1071{ 1072 struct mem_range mr; 1073 struct pci_devemu *pde; 1074 struct businfo *bi; 1075 struct slotinfo *si; 1076 struct funcinfo *fi; 1077 size_t lowmem; 1078 int bus, slot, func; 1079 int error; 1080 1081 pci_emul_iobase = PCI_EMUL_IOBASE; 1082 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1083 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1084 1085 for (bus = 0; bus < MAXBUSES; bus++) { 1086 if ((bi = pci_businfo[bus]) == NULL) 1087 continue; 1088 /* 1089 * Keep track of the i/o and memory resources allocated to 1090 * this bus. 1091 */ 1092 bi->iobase = pci_emul_iobase; 1093 bi->membase32 = pci_emul_membase32; 1094 bi->membase64 = pci_emul_membase64; 1095 1096 for (slot = 0; slot < MAXSLOTS; slot++) { 1097 si = &bi->slotinfo[slot]; 1098 for (func = 0; func < MAXFUNCS; func++) { 1099 fi = &si->si_funcs[func]; 1100 if (fi->fi_name == NULL) 1101 continue; 1102 pde = pci_emul_finddev(fi->fi_name); 1103 assert(pde != NULL); 1104 error = pci_emul_init(ctx, pde, bus, slot, 1105 func, fi); 1106 if (error) 1107 return (error); 1108 } 1109 } 1110 1111 /* 1112 * Add some slop to the I/O and memory resources decoded by 1113 * this bus to give a guest some flexibility if it wants to 1114 * reprogram the BARs. 1115 */ 1116 pci_emul_iobase += BUSIO_ROUNDUP; 1117 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1118 bi->iolimit = pci_emul_iobase; 1119 1120 pci_emul_membase32 += BUSMEM_ROUNDUP; 1121 pci_emul_membase32 = roundup2(pci_emul_membase32, 1122 BUSMEM_ROUNDUP); 1123 bi->memlimit32 = pci_emul_membase32; 1124 1125 pci_emul_membase64 += BUSMEM_ROUNDUP; 1126 pci_emul_membase64 = roundup2(pci_emul_membase64, 1127 BUSMEM_ROUNDUP); 1128 bi->memlimit64 = pci_emul_membase64; 1129 } 1130 1131 /* 1132 * PCI backends are initialized before routing INTx interrupts 1133 * so that LPC devices are able to reserve ISA IRQs before 1134 * routing PIRQ pins. 1135 */ 1136 for (bus = 0; bus < MAXBUSES; bus++) { 1137 if ((bi = pci_businfo[bus]) == NULL) 1138 continue; 1139 1140 for (slot = 0; slot < MAXSLOTS; slot++) { 1141 si = &bi->slotinfo[slot]; 1142 for (func = 0; func < MAXFUNCS; func++) { 1143 fi = &si->si_funcs[func]; 1144 if (fi->fi_devi == NULL) 1145 continue; 1146 pci_lintr_route(fi->fi_devi); 1147 } 1148 } 1149 } 1150 lpc_pirq_routed(); 1151 1152 /* 1153 * The guest physical memory map looks like the following: 1154 * [0, lowmem) guest system memory 1155 * [lowmem, lowmem_limit) memory hole (may be absent) 1156 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation) 1157 * [0xE0000000, 0xF0000000) PCI extended config window 1158 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1159 * [4GB, 4GB + highmem) 1160 */ 1161 1162 /* 1163 * Accesses to memory addresses that are not allocated to system 1164 * memory or PCI devices return 0xff's. 1165 */ 1166 lowmem = vm_get_lowmem_size(ctx); 1167 bzero(&mr, sizeof(struct mem_range)); 1168 mr.name = "PCI hole"; 1169 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1170 mr.base = lowmem; 1171 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1172 mr.handler = pci_emul_fallback_handler; 1173 error = register_mem_fallback(&mr); 1174 assert(error == 0); 1175 1176 /* PCI extended config space */ 1177 bzero(&mr, sizeof(struct mem_range)); 1178 mr.name = "PCI ECFG"; 1179 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1180 mr.base = PCI_EMUL_ECFG_BASE; 1181 mr.size = PCI_EMUL_ECFG_SIZE; 1182 mr.handler = pci_emul_ecfg_handler; 1183 error = register_mem(&mr); 1184 assert(error == 0); 1185 1186 return (0); 1187} 1188 1189static void 1190pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1191 void *arg) 1192{ 1193 1194 dsdt_line(" Package ()"); 1195 dsdt_line(" {"); 1196 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1197 dsdt_line(" 0x%02X,", pin - 1); 1198 dsdt_line(" Zero,"); 1199 dsdt_line(" 0x%X", ioapic_irq); 1200 dsdt_line(" },"); 1201} 1202 1203static void 1204pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1205 void *arg) 1206{ 1207 char *name; 1208 1209 name = lpc_pirq_name(pirq_pin); 1210 if (name == NULL) 1211 return; 1212 dsdt_line(" Package ()"); 1213 dsdt_line(" {"); 1214 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1215 dsdt_line(" 0x%02X,", pin - 1); 1216 dsdt_line(" %s,", name); 1217 dsdt_line(" 0x00"); 1218 dsdt_line(" },"); 1219 free(name); 1220} 1221 1222/* 1223 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1224 * corresponding to each PCI bus. 1225 */ 1226static void 1227pci_bus_write_dsdt(int bus) 1228{ 1229 struct businfo *bi; 1230 struct slotinfo *si; 1231 struct pci_devinst *pi; 1232 int count, func, slot; 1233 1234 /* 1235 * If there are no devices on this 'bus' then just return. 1236 */ 1237 if ((bi = pci_businfo[bus]) == NULL) { 1238 /* 1239 * Bus 0 is special because it decodes the I/O ports used 1240 * for PCI config space access even if there are no devices 1241 * on it. 1242 */ 1243 if (bus != 0) 1244 return; 1245 } 1246 1247 dsdt_line(" Device (PC%02X)", bus); 1248 dsdt_line(" {"); 1249 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1250 dsdt_line(" Name (_ADR, Zero)"); 1251 1252 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1253 dsdt_line(" {"); 1254 dsdt_line(" Return (0x%08X)", bus); 1255 dsdt_line(" }"); 1256 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1257 dsdt_line(" {"); 1258 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1259 "MaxFixed, PosDecode,"); 1260 dsdt_line(" 0x0000, // Granularity"); 1261 dsdt_line(" 0x%04X, // Range Minimum", bus); 1262 dsdt_line(" 0x%04X, // Range Maximum", bus); 1263 dsdt_line(" 0x0000, // Translation Offset"); 1264 dsdt_line(" 0x0001, // Length"); 1265 dsdt_line(" ,, )"); 1266 1267 if (bus == 0) { 1268 dsdt_indent(3); 1269 dsdt_fixed_ioport(0xCF8, 8); 1270 dsdt_unindent(3); 1271 1272 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1273 "PosDecode, EntireRange,"); 1274 dsdt_line(" 0x0000, // Granularity"); 1275 dsdt_line(" 0x0000, // Range Minimum"); 1276 dsdt_line(" 0x0CF7, // Range Maximum"); 1277 dsdt_line(" 0x0000, // Translation Offset"); 1278 dsdt_line(" 0x0CF8, // Length"); 1279 dsdt_line(" ,, , TypeStatic)"); 1280 1281 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1282 "PosDecode, EntireRange,"); 1283 dsdt_line(" 0x0000, // Granularity"); 1284 dsdt_line(" 0x0D00, // Range Minimum"); 1285 dsdt_line(" 0x%04X, // Range Maximum", 1286 PCI_EMUL_IOBASE - 1); 1287 dsdt_line(" 0x0000, // Translation Offset"); 1288 dsdt_line(" 0x%04X, // Length", 1289 PCI_EMUL_IOBASE - 0x0D00); 1290 dsdt_line(" ,, , TypeStatic)"); 1291 1292 if (bi == NULL) { 1293 dsdt_line(" })"); 1294 goto done; 1295 } 1296 } 1297 assert(bi != NULL); 1298 1299 /* i/o window */ 1300 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1301 "PosDecode, EntireRange,"); 1302 dsdt_line(" 0x0000, // Granularity"); 1303 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1304 dsdt_line(" 0x%04X, // Range Maximum", 1305 bi->iolimit - 1); 1306 dsdt_line(" 0x0000, // Translation Offset"); 1307 dsdt_line(" 0x%04X, // Length", 1308 bi->iolimit - bi->iobase); 1309 dsdt_line(" ,, , TypeStatic)"); 1310 1311 /* mmio window (32-bit) */ 1312 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1313 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1314 dsdt_line(" 0x00000000, // Granularity"); 1315 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1316 dsdt_line(" 0x%08X, // Range Maximum\n", 1317 bi->memlimit32 - 1); 1318 dsdt_line(" 0x00000000, // Translation Offset"); 1319 dsdt_line(" 0x%08X, // Length\n", 1320 bi->memlimit32 - bi->membase32); 1321 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1322 1323 /* mmio window (64-bit) */ 1324 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1325 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1326 dsdt_line(" 0x0000000000000000, // Granularity"); 1327 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1328 dsdt_line(" 0x%016lX, // Range Maximum\n", 1329 bi->memlimit64 - 1); 1330 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1331 dsdt_line(" 0x%016lX, // Length\n", 1332 bi->memlimit64 - bi->membase64); 1333 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1334 dsdt_line(" })"); 1335 1336 count = pci_count_lintr(bus); 1337 if (count != 0) { 1338 dsdt_indent(2); 1339 dsdt_line("Name (PPRT, Package ()"); 1340 dsdt_line("{"); 1341 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1342 dsdt_line("})"); 1343 dsdt_line("Name (APRT, Package ()"); 1344 dsdt_line("{"); 1345 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1346 dsdt_line("})"); 1347 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1348 dsdt_line("{"); 1349 dsdt_line(" If (PICM)"); 1350 dsdt_line(" {"); 1351 dsdt_line(" Return (APRT)"); 1352 dsdt_line(" }"); 1353 dsdt_line(" Else"); 1354 dsdt_line(" {"); 1355 dsdt_line(" Return (PPRT)"); 1356 dsdt_line(" }"); 1357 dsdt_line("}"); 1358 dsdt_unindent(2); 1359 } 1360 1361 dsdt_indent(2); 1362 for (slot = 0; slot < MAXSLOTS; slot++) { 1363 si = &bi->slotinfo[slot]; 1364 for (func = 0; func < MAXFUNCS; func++) { 1365 pi = si->si_funcs[func].fi_devi; 1366 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1367 pi->pi_d->pe_write_dsdt(pi); 1368 } 1369 } 1370 dsdt_unindent(2); 1371done: 1372 dsdt_line(" }"); 1373} 1374 1375void 1376pci_write_dsdt(void) 1377{ 1378 int bus; 1379 1380 dsdt_indent(1); 1381 dsdt_line("Name (PICM, 0x00)"); 1382 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1383 dsdt_line("{"); 1384 dsdt_line(" Store (Arg0, PICM)"); 1385 dsdt_line("}"); 1386 dsdt_line(""); 1387 dsdt_line("Scope (_SB)"); 1388 dsdt_line("{"); 1389 for (bus = 0; bus < MAXBUSES; bus++) 1390 pci_bus_write_dsdt(bus); 1391 dsdt_line("}"); 1392 dsdt_unindent(1); 1393} 1394 1395int 1396pci_bus_configured(int bus) 1397{ 1398 assert(bus >= 0 && bus < MAXBUSES); 1399 return (pci_businfo[bus] != NULL); 1400} 1401 1402int 1403pci_msi_enabled(struct pci_devinst *pi) 1404{ 1405 return (pi->pi_msi.enabled); 1406} 1407 1408int 1409pci_msi_maxmsgnum(struct pci_devinst *pi) 1410{ 1411 if (pi->pi_msi.enabled) 1412 return (pi->pi_msi.maxmsgnum); 1413 else 1414 return (0); 1415} 1416 1417int 1418pci_msix_enabled(struct pci_devinst *pi) 1419{ 1420 1421 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1422} 1423 1424void 1425pci_generate_msix(struct pci_devinst *pi, int index) 1426{ 1427 struct msix_table_entry *mte; 1428 1429 if (!pci_msix_enabled(pi)) 1430 return; 1431 1432 if (pi->pi_msix.function_mask) 1433 return; 1434 1435 if (index >= pi->pi_msix.table_count) 1436 return; 1437 1438 mte = &pi->pi_msix.table[index]; 1439 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1440 /* XXX Set PBA bit if interrupt is disabled */ 1441 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1442 } 1443} 1444 1445void 1446pci_generate_msi(struct pci_devinst *pi, int index) 1447{ 1448 1449 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1450 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1451 pi->pi_msi.msg_data + index); 1452 } 1453} 1454 1455static bool 1456pci_lintr_permitted(struct pci_devinst *pi) 1457{ 1458 uint16_t cmd; 1459 1460 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1461 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1462 (cmd & PCIM_CMD_INTxDIS))); 1463} 1464 1465void 1466pci_lintr_request(struct pci_devinst *pi) 1467{ 1468 struct businfo *bi; 1469 struct slotinfo *si; 1470 int bestpin, bestcount, pin; 1471 1472 bi = pci_businfo[pi->pi_bus]; 1473 assert(bi != NULL); 1474 1475 /* 1476 * Just allocate a pin from our slot. The pin will be 1477 * assigned IRQs later when interrupts are routed. 1478 */ 1479 si = &bi->slotinfo[pi->pi_slot]; 1480 bestpin = 0; 1481 bestcount = si->si_intpins[0].ii_count; 1482 for (pin = 1; pin < 4; pin++) { 1483 if (si->si_intpins[pin].ii_count < bestcount) { 1484 bestpin = pin; 1485 bestcount = si->si_intpins[pin].ii_count; 1486 } 1487 } 1488 1489 si->si_intpins[bestpin].ii_count++; 1490 pi->pi_lintr.pin = bestpin + 1; 1491 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1492} 1493 1494static void 1495pci_lintr_route(struct pci_devinst *pi) 1496{ 1497 struct businfo *bi; 1498 struct intxinfo *ii; 1499 1500 if (pi->pi_lintr.pin == 0) 1501 return; 1502 1503 bi = pci_businfo[pi->pi_bus]; 1504 assert(bi != NULL); 1505 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1506 1507 /* 1508 * Attempt to allocate an I/O APIC pin for this intpin if one 1509 * is not yet assigned. 1510 */ 1511 if (ii->ii_ioapic_irq == 0) 1512 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(); 1513 assert(ii->ii_ioapic_irq > 0); 1514 1515 /* 1516 * Attempt to allocate a PIRQ pin for this intpin if one is 1517 * not yet assigned. 1518 */ 1519 if (ii->ii_pirq_pin == 0) 1520 ii->ii_pirq_pin = pirq_alloc_pin(pi->pi_vmctx); 1521 assert(ii->ii_pirq_pin > 0); 1522 1523 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1524 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1525 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1526} 1527 1528void 1529pci_lintr_assert(struct pci_devinst *pi) 1530{ 1531 1532 assert(pi->pi_lintr.pin > 0); 1533 1534 pthread_mutex_lock(&pi->pi_lintr.lock); 1535 if (pi->pi_lintr.state == IDLE) { 1536 if (pci_lintr_permitted(pi)) { 1537 pi->pi_lintr.state = ASSERTED; 1538 pci_irq_assert(pi); 1539 } else 1540 pi->pi_lintr.state = PENDING; 1541 } 1542 pthread_mutex_unlock(&pi->pi_lintr.lock); 1543} 1544 1545void 1546pci_lintr_deassert(struct pci_devinst *pi) 1547{ 1548 1549 assert(pi->pi_lintr.pin > 0); 1550 1551 pthread_mutex_lock(&pi->pi_lintr.lock); 1552 if (pi->pi_lintr.state == ASSERTED) { 1553 pi->pi_lintr.state = IDLE; 1554 pci_irq_deassert(pi); 1555 } else if (pi->pi_lintr.state == PENDING) 1556 pi->pi_lintr.state = IDLE; 1557 pthread_mutex_unlock(&pi->pi_lintr.lock); 1558} 1559 1560static void 1561pci_lintr_update(struct pci_devinst *pi) 1562{ 1563 1564 pthread_mutex_lock(&pi->pi_lintr.lock); 1565 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1566 pci_irq_deassert(pi); 1567 pi->pi_lintr.state = PENDING; 1568 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1569 pi->pi_lintr.state = ASSERTED; 1570 pci_irq_assert(pi); 1571 } 1572 pthread_mutex_unlock(&pi->pi_lintr.lock); 1573} 1574 1575int 1576pci_count_lintr(int bus) 1577{ 1578 int count, slot, pin; 1579 struct slotinfo *slotinfo; 1580 1581 count = 0; 1582 if (pci_businfo[bus] != NULL) { 1583 for (slot = 0; slot < MAXSLOTS; slot++) { 1584 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1585 for (pin = 0; pin < 4; pin++) { 1586 if (slotinfo->si_intpins[pin].ii_count != 0) 1587 count++; 1588 } 1589 } 1590 } 1591 return (count); 1592} 1593 1594void 1595pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1596{ 1597 struct businfo *bi; 1598 struct slotinfo *si; 1599 struct intxinfo *ii; 1600 int slot, pin; 1601 1602 if ((bi = pci_businfo[bus]) == NULL) 1603 return; 1604 1605 for (slot = 0; slot < MAXSLOTS; slot++) { 1606 si = &bi->slotinfo[slot]; 1607 for (pin = 0; pin < 4; pin++) { 1608 ii = &si->si_intpins[pin]; 1609 if (ii->ii_count != 0) 1610 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1611 ii->ii_ioapic_irq, arg); 1612 } 1613 } 1614} 1615 1616/* 1617 * Return 1 if the emulated device in 'slot' is a multi-function device. 1618 * Return 0 otherwise. 1619 */ 1620static int 1621pci_emul_is_mfdev(int bus, int slot) 1622{ 1623 struct businfo *bi; 1624 struct slotinfo *si; 1625 int f, numfuncs; 1626 1627 numfuncs = 0; 1628 if ((bi = pci_businfo[bus]) != NULL) { 1629 si = &bi->slotinfo[slot]; 1630 for (f = 0; f < MAXFUNCS; f++) { 1631 if (si->si_funcs[f].fi_devi != NULL) { 1632 numfuncs++; 1633 } 1634 } 1635 } 1636 return (numfuncs > 1); 1637} 1638 1639/* 1640 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1641 * whether or not is a multi-function being emulated in the pci 'slot'. 1642 */ 1643static void 1644pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1645{ 1646 int mfdev; 1647 1648 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1649 mfdev = pci_emul_is_mfdev(bus, slot); 1650 switch (bytes) { 1651 case 1: 1652 case 2: 1653 *rv &= ~PCIM_MFDEV; 1654 if (mfdev) { 1655 *rv |= PCIM_MFDEV; 1656 } 1657 break; 1658 case 4: 1659 *rv &= ~(PCIM_MFDEV << 16); 1660 if (mfdev) { 1661 *rv |= (PCIM_MFDEV << 16); 1662 } 1663 break; 1664 } 1665 } 1666} 1667 1668static void 1669pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 1670{ 1671 int i, rshift; 1672 uint32_t cmd, cmd2, changed, old, readonly; 1673 1674 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1675 1676 /* 1677 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 1678 * 1679 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 1680 * 'write 1 to clear'. However these bits are not set to '1' by 1681 * any device emulation so it is simpler to treat them as readonly. 1682 */ 1683 rshift = (coff & 0x3) * 8; 1684 readonly = 0xFFFFF880 >> rshift; 1685 1686 old = CFGREAD(pi, coff, bytes); 1687 new &= ~readonly; 1688 new |= (old & readonly); 1689 CFGWRITE(pi, coff, new, bytes); /* update config */ 1690 1691 cmd2 = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */ 1692 changed = cmd ^ cmd2; 1693 1694 /* 1695 * If the MMIO or I/O address space decoding has changed then 1696 * register/unregister all BARs that decode that address space. 1697 */ 1698 for (i = 0; i <= PCI_BARMAX; i++) { 1699 switch (pi->pi_bar[i].type) { 1700 case PCIBAR_NONE: 1701 case PCIBAR_MEMHI64: 1702 break; 1703 case PCIBAR_IO: 1704 /* I/O address space decoding changed? */ 1705 if (changed & PCIM_CMD_PORTEN) { 1706 if (porten(pi)) 1707 register_bar(pi, i); 1708 else 1709 unregister_bar(pi, i); 1710 } 1711 break; 1712 case PCIBAR_MEM32: 1713 case PCIBAR_MEM64: 1714 /* MMIO address space decoding changed? */ 1715 if (changed & PCIM_CMD_MEMEN) { 1716 if (memen(pi)) 1717 register_bar(pi, i); 1718 else 1719 unregister_bar(pi, i); 1720 } 1721 break; 1722 default: 1723 assert(0); 1724 } 1725 } 1726 1727 /* 1728 * If INTx has been unmasked and is pending, assert the 1729 * interrupt. 1730 */ 1731 pci_lintr_update(pi); 1732} 1733 1734static void 1735pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, 1736 int coff, int bytes, uint32_t *eax) 1737{ 1738 struct businfo *bi; 1739 struct slotinfo *si; 1740 struct pci_devinst *pi; 1741 struct pci_devemu *pe; 1742 int idx, needcfg; 1743 uint64_t addr, bar, mask; 1744 1745 if ((bi = pci_businfo[bus]) != NULL) { 1746 si = &bi->slotinfo[slot]; 1747 pi = si->si_funcs[func].fi_devi; 1748 } else 1749 pi = NULL; 1750 1751 /* 1752 * Just return if there is no device at this slot:func or if the 1753 * the guest is doing an un-aligned access. 1754 */ 1755 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 1756 (coff & (bytes - 1)) != 0) { 1757 if (in) 1758 *eax = 0xffffffff; 1759 return; 1760 } 1761 1762 /* 1763 * Ignore all writes beyond the standard config space and return all 1764 * ones on reads. 1765 */ 1766 if (coff >= PCI_REGMAX + 1) { 1767 if (in) { 1768 *eax = 0xffffffff; 1769 /* 1770 * Extended capabilities begin at offset 256 in config 1771 * space. Absence of extended capabilities is signaled 1772 * with all 0s in the extended capability header at 1773 * offset 256. 1774 */ 1775 if (coff <= PCI_REGMAX + 4) 1776 *eax = 0x00000000; 1777 } 1778 return; 1779 } 1780 1781 pe = pi->pi_d; 1782 1783 /* 1784 * Config read 1785 */ 1786 if (in) { 1787 /* Let the device emulation override the default handler */ 1788 if (pe->pe_cfgread != NULL) { 1789 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes, 1790 eax); 1791 } else { 1792 needcfg = 1; 1793 } 1794 1795 if (needcfg) 1796 *eax = CFGREAD(pi, coff, bytes); 1797 1798 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 1799 } else { 1800 /* Let the device emulation override the default handler */ 1801 if (pe->pe_cfgwrite != NULL && 1802 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1803 return; 1804 1805 /* 1806 * Special handling for write to BAR registers 1807 */ 1808 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1809 /* 1810 * Ignore writes to BAR registers that are not 1811 * 4-byte aligned. 1812 */ 1813 if (bytes != 4 || (coff & 0x3) != 0) 1814 return; 1815 idx = (coff - PCIR_BAR(0)) / 4; 1816 mask = ~(pi->pi_bar[idx].size - 1); 1817 switch (pi->pi_bar[idx].type) { 1818 case PCIBAR_NONE: 1819 pi->pi_bar[idx].addr = bar = 0; 1820 break; 1821 case PCIBAR_IO: 1822 addr = *eax & mask; 1823 addr &= 0xffff; 1824 bar = addr | PCIM_BAR_IO_SPACE; 1825 /* 1826 * Register the new BAR value for interception 1827 */ 1828 if (addr != pi->pi_bar[idx].addr) { 1829 update_bar_address(pi, addr, idx, 1830 PCIBAR_IO); 1831 } 1832 break; 1833 case PCIBAR_MEM32: 1834 addr = bar = *eax & mask; 1835 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1836 if (addr != pi->pi_bar[idx].addr) { 1837 update_bar_address(pi, addr, idx, 1838 PCIBAR_MEM32); 1839 } 1840 break; 1841 case PCIBAR_MEM64: 1842 addr = bar = *eax & mask; 1843 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1844 PCIM_BAR_MEM_PREFETCH; 1845 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1846 update_bar_address(pi, addr, idx, 1847 PCIBAR_MEM64); 1848 } 1849 break; 1850 case PCIBAR_MEMHI64: 1851 mask = ~(pi->pi_bar[idx - 1].size - 1); 1852 addr = ((uint64_t)*eax << 32) & mask; 1853 bar = addr >> 32; 1854 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1855 update_bar_address(pi, addr, idx - 1, 1856 PCIBAR_MEMHI64); 1857 } 1858 break; 1859 default: 1860 assert(0); 1861 } 1862 pci_set_cfgdata32(pi, coff, bar); 1863 1864 } else if (pci_emul_iscap(pi, coff)) { 1865 pci_emul_capwrite(pi, coff, bytes, *eax); 1866 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 1867 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 1868 } else { 1869 CFGWRITE(pi, coff, *eax, bytes); 1870 } 1871 } 1872} 1873 1874static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 1875 1876static int 1877pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1878 uint32_t *eax, void *arg) 1879{ 1880 uint32_t x; 1881 1882 if (bytes != 4) { 1883 if (in) 1884 *eax = (bytes == 2) ? 0xffff : 0xff; 1885 return (0); 1886 } 1887 1888 if (in) { 1889 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 1890 if (cfgenable) 1891 x |= CONF1_ENABLE; 1892 *eax = x; 1893 } else { 1894 x = *eax; 1895 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 1896 cfgoff = x & PCI_REGMAX; 1897 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1898 cfgslot = (x >> 11) & PCI_SLOTMAX; 1899 cfgbus = (x >> 16) & PCI_BUSMAX; 1900 } 1901 1902 return (0); 1903} 1904INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1905 1906static int 1907pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1908 uint32_t *eax, void *arg) 1909{ 1910 int coff; 1911 1912 assert(bytes == 1 || bytes == 2 || bytes == 4); 1913 1914 coff = cfgoff + (port - CONF1_DATA_PORT); 1915 if (cfgenable) { 1916 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes, 1917 eax); 1918 } else { 1919 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 1920 if (in) 1921 *eax = 0xffffffff; 1922 } 1923 return (0); 1924} 1925 1926INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1927INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1928INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1929INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1930 1931#define PCI_EMUL_TEST 1932#ifdef PCI_EMUL_TEST 1933/* 1934 * Define a dummy test device 1935 */ 1936#define DIOSZ 8 1937#define DMEMSZ 4096 1938struct pci_emul_dsoftc { 1939 uint8_t ioregs[DIOSZ]; 1940 uint8_t memregs[2][DMEMSZ]; 1941}; 1942 1943#define PCI_EMUL_MSI_MSGS 4 1944#define PCI_EMUL_MSIX_MSGS 16 1945 1946static int 1947pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1948{ 1949 int error; 1950 struct pci_emul_dsoftc *sc; 1951 1952 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 1953 1954 pi->pi_arg = sc; 1955 1956 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1957 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1958 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1959 1960 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1961 assert(error == 0); 1962 1963 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1964 assert(error == 0); 1965 1966 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 1967 assert(error == 0); 1968 1969 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 1970 assert(error == 0); 1971 1972 return (0); 1973} 1974 1975static void 1976pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1977 uint64_t offset, int size, uint64_t value) 1978{ 1979 int i; 1980 struct pci_emul_dsoftc *sc = pi->pi_arg; 1981 1982 if (baridx == 0) { 1983 if (offset + size > DIOSZ) { 1984 printf("diow: iow too large, offset %ld size %d\n", 1985 offset, size); 1986 return; 1987 } 1988 1989 if (size == 1) { 1990 sc->ioregs[offset] = value & 0xff; 1991 } else if (size == 2) { 1992 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 1993 } else if (size == 4) { 1994 *(uint32_t *)&sc->ioregs[offset] = value; 1995 } else { 1996 printf("diow: iow unknown size %d\n", size); 1997 } 1998 1999 /* 2000 * Special magic value to generate an interrupt 2001 */ 2002 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2003 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2004 2005 if (value == 0xabcdef) { 2006 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2007 pci_generate_msi(pi, i); 2008 } 2009 } 2010 2011 if (baridx == 1 || baridx == 2) { 2012 if (offset + size > DMEMSZ) { 2013 printf("diow: memw too large, offset %ld size %d\n", 2014 offset, size); 2015 return; 2016 } 2017 2018 i = baridx - 1; /* 'memregs' index */ 2019 2020 if (size == 1) { 2021 sc->memregs[i][offset] = value; 2022 } else if (size == 2) { 2023 *(uint16_t *)&sc->memregs[i][offset] = value; 2024 } else if (size == 4) { 2025 *(uint32_t *)&sc->memregs[i][offset] = value; 2026 } else if (size == 8) { 2027 *(uint64_t *)&sc->memregs[i][offset] = value; 2028 } else { 2029 printf("diow: memw unknown size %d\n", size); 2030 } 2031 2032 /* 2033 * magic interrupt ?? 2034 */ 2035 } 2036 2037 if (baridx > 2) { 2038 printf("diow: unknown bar idx %d\n", baridx); 2039 } 2040} 2041 2042static uint64_t 2043pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2044 uint64_t offset, int size) 2045{ 2046 struct pci_emul_dsoftc *sc = pi->pi_arg; 2047 uint32_t value; 2048 int i; 2049 2050 if (baridx == 0) { 2051 if (offset + size > DIOSZ) { 2052 printf("dior: ior too large, offset %ld size %d\n", 2053 offset, size); 2054 return (0); 2055 } 2056 2057 if (size == 1) { 2058 value = sc->ioregs[offset]; 2059 } else if (size == 2) { 2060 value = *(uint16_t *) &sc->ioregs[offset]; 2061 } else if (size == 4) { 2062 value = *(uint32_t *) &sc->ioregs[offset]; 2063 } else { 2064 printf("dior: ior unknown size %d\n", size); 2065 } 2066 } 2067 2068 if (baridx == 1 || baridx == 2) { 2069 if (offset + size > DMEMSZ) { 2070 printf("dior: memr too large, offset %ld size %d\n", 2071 offset, size); 2072 return (0); 2073 } 2074 2075 i = baridx - 1; /* 'memregs' index */ 2076 2077 if (size == 1) { 2078 value = sc->memregs[i][offset]; 2079 } else if (size == 2) { 2080 value = *(uint16_t *) &sc->memregs[i][offset]; 2081 } else if (size == 4) { 2082 value = *(uint32_t *) &sc->memregs[i][offset]; 2083 } else if (size == 8) { 2084 value = *(uint64_t *) &sc->memregs[i][offset]; 2085 } else { 2086 printf("dior: ior unknown size %d\n", size); 2087 } 2088 } 2089 2090 2091 if (baridx > 2) { 2092 printf("dior: unknown bar idx %d\n", baridx); 2093 return (0); 2094 } 2095 2096 return (value); 2097} 2098 2099struct pci_devemu pci_dummy = { 2100 .pe_emu = "dummy", 2101 .pe_init = pci_emul_dinit, 2102 .pe_barwrite = pci_emul_diow, 2103 .pe_barread = pci_emul_dior 2104}; 2105PCI_EMUL_SET(pci_dummy); 2106 2107#endif /* PCI_EMUL_TEST */ 2108