schizo.c revision 227843
1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4220038Smarius * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 227843 2011-11-22 21:28:20Z marius $"); 36183423Smarius 37183423Smarius/* 38220038Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 39220038Smarius * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55208097Smarius#include <sys/sysctl.h> 56185133Smarius#include <sys/time.h> 57183423Smarius#include <sys/timetc.h> 58183423Smarius 59183423Smarius#include <dev/ofw/ofw_bus.h> 60183423Smarius#include <dev/ofw/ofw_pci.h> 61183423Smarius#include <dev/ofw/openfirm.h> 62183423Smarius 63183423Smarius#include <machine/bus.h> 64183423Smarius#include <machine/bus_common.h> 65183423Smarius#include <machine/bus_private.h> 66183423Smarius#include <machine/fsr.h> 67183423Smarius#include <machine/iommureg.h> 68183423Smarius#include <machine/iommuvar.h> 69183423Smarius#include <machine/resource.h> 70183423Smarius 71183423Smarius#include <dev/pci/pcireg.h> 72183423Smarius#include <dev/pci/pcivar.h> 73183423Smarius 74183423Smarius#include <sparc64/pci/ofw_pci.h> 75183423Smarius#include <sparc64/pci/schizoreg.h> 76183423Smarius#include <sparc64/pci/schizovar.h> 77183423Smarius 78183423Smarius#include "pcib_if.h" 79183423Smarius 80183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 81183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82183423Smarius driver_filter_t); 83220038Smariusstatic void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 84220038Smarius bus_dmasync_op_t op); 85220038Smariusstatic void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 86220038Smarius bus_dmasync_op_t op); 87183423Smariusstatic void schizo_intr_enable(void *); 88183423Smariusstatic void schizo_intr_disable(void *); 89183423Smariusstatic void schizo_intr_assign(void *); 90183423Smariusstatic void schizo_intr_clear(void *); 91185133Smariusstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 92183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 93183423Smarius bus_addr_t *, bus_addr_t *); 94183423Smariusstatic timecounter_get_t schizo_get_timecount; 95183423Smarius 96183423Smarius/* Interrupt handlers */ 97183423Smariusstatic driver_filter_t schizo_pci_bus; 98183423Smariusstatic driver_filter_t schizo_ue; 99183423Smariusstatic driver_filter_t schizo_ce; 100183423Smariusstatic driver_filter_t schizo_host_bus; 101185133Smariusstatic driver_filter_t schizo_cdma; 102183423Smarius 103183423Smarius/* IOMMU support */ 104183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 105183423Smarius 106183423Smarius/* 107183423Smarius * Methods 108183423Smarius */ 109183423Smariusstatic device_probe_t schizo_probe; 110183423Smariusstatic device_attach_t schizo_attach; 111183423Smariusstatic bus_read_ivar_t schizo_read_ivar; 112183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 113183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 114183423Smariusstatic bus_activate_resource_t schizo_activate_resource; 115225931Smariusstatic bus_adjust_resource_t schizo_adjust_resource; 116183423Smariusstatic bus_get_dma_tag_t schizo_get_dma_tag; 117183423Smariusstatic pcib_maxslots_t schizo_maxslots; 118183423Smariusstatic pcib_read_config_t schizo_read_config; 119183423Smariusstatic pcib_write_config_t schizo_write_config; 120183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 121183423Smariusstatic ofw_bus_get_node_t schizo_get_node; 122220038Smariusstatic ofw_pci_setup_device_t schizo_setup_device; 123183423Smarius 124183423Smariusstatic device_method_t schizo_methods[] = { 125183423Smarius /* Device interface */ 126183423Smarius DEVMETHOD(device_probe, schizo_probe), 127183423Smarius DEVMETHOD(device_attach, schizo_attach), 128183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 129183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 130183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 131183423Smarius 132183423Smarius /* Bus interface */ 133183423Smarius DEVMETHOD(bus_read_ivar, schizo_read_ivar), 134183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 135220038Smarius DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 136183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 137225931Smarius DEVMETHOD(bus_activate_resource, schizo_activate_resource), 138225931Smarius DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 139225931Smarius DEVMETHOD(bus_adjust_resource, schizo_adjust_resource), 140225931Smarius DEVMETHOD(bus_release_resource, bus_generic_release_resource), 141183423Smarius DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 142183423Smarius 143183423Smarius /* pcib interface */ 144183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 145183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 146183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 147183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 148183423Smarius 149183423Smarius /* ofw_bus interface */ 150183423Smarius DEVMETHOD(ofw_bus_get_node, schizo_get_node), 151183423Smarius 152225931Smarius /* ofw_pci interface */ 153220038Smarius DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 154220038Smarius 155227843Smarius DEVMETHOD_END 156183423Smarius}; 157183423Smarius 158183423Smariusstatic devclass_t schizo_devclass; 159183423Smarius 160183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 161183423Smarius sizeof(struct schizo_softc)); 162215349SmariusEARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 163215349Smarius BUS_PASS_BUS); 164183423Smarius 165183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 166183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 167183423Smarius 168183423Smariusstatic const struct intr_controller schizo_ic = { 169183423Smarius schizo_intr_enable, 170183423Smarius schizo_intr_disable, 171183423Smarius schizo_intr_assign, 172183423Smarius schizo_intr_clear 173183423Smarius}; 174183423Smarius 175183423Smariusstruct schizo_icarg { 176183423Smarius struct schizo_softc *sica_sc; 177183423Smarius bus_addr_t sica_map; 178183423Smarius bus_addr_t sica_clr; 179183423Smarius}; 180183423Smarius 181183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 182183423Smarius 183220038Smarius#define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 184220038Smarius bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 185206018Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 186183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 187206018Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 188183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 189183423Smarius 190220038Smarius#ifndef SCHIZO_DEBUG 191220038Smarius#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 192220038Smarius SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 193220038Smarius#else 194220038Smarius#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 195220038Smarius device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 196220038Smarius (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 197220038Smarius (unsigned long long)(v)); \ 198220038Smarius SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 199220038Smarius } while (0) 200220038Smarius#endif 201220038Smarius 202206018Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 203183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 204206018Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 205183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 206206018Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 207183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 208206018Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 209183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 210206018Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 211183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 212206018Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 213183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 214206018Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 215183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 216206018Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 217183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 218183423Smarius 219220038Smarius#define SCHIZO_PCI_SET(sc, offs, v) \ 220220038Smarius SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 221220038Smarius#define SCHIZO_CTRL_SET(sc, offs, v) \ 222220038Smarius SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 223220038Smarius 224183423Smariusstruct schizo_desc { 225183423Smarius const char *sd_string; 226183423Smarius int sd_mode; 227183423Smarius const char *sd_name; 228183423Smarius}; 229183423Smarius 230185133Smariusstatic const struct schizo_desc const schizo_compats[] = { 231183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 232220038Smarius#if 0 233220038Smarius { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 234220038Smarius#endif 235183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 236183423Smarius { NULL, 0, NULL } 237183423Smarius}; 238183423Smarius 239183423Smariusstatic const struct schizo_desc * 240183423Smariusschizo_get_desc(device_t dev) 241183423Smarius{ 242183423Smarius const struct schizo_desc *desc; 243183423Smarius const char *compat; 244183423Smarius 245183423Smarius compat = ofw_bus_get_compat(dev); 246183423Smarius if (compat == NULL) 247183423Smarius return (NULL); 248183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 249183423Smarius if (strcmp(desc->sd_string, compat) == 0) 250183423Smarius return (desc); 251183423Smarius return (NULL); 252183423Smarius} 253183423Smarius 254183423Smariusstatic int 255183423Smariusschizo_probe(device_t dev) 256183423Smarius{ 257183423Smarius const char *dtype; 258183423Smarius 259183423Smarius dtype = ofw_bus_get_type(dev); 260197164Smarius if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 261183423Smarius schizo_get_desc(dev) != NULL) { 262183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 263183423Smarius return (0); 264183423Smarius } 265183423Smarius return (ENXIO); 266183423Smarius} 267183423Smarius 268183423Smariusstatic int 269183423Smariusschizo_attach(device_t dev) 270183423Smarius{ 271183423Smarius struct ofw_pci_ranges *range; 272183423Smarius const struct schizo_desc *desc; 273183423Smarius struct schizo_softc *asc, *sc, *osc; 274183423Smarius struct timecounter *tc; 275183423Smarius uint64_t ino_bitmap, reg; 276183423Smarius phandle_t node; 277183423Smarius uint32_t prop, prop_array[2]; 278201199Smarius int i, j, mode, rid, tsbsize; 279183423Smarius 280183423Smarius sc = device_get_softc(dev); 281183423Smarius node = ofw_bus_get_node(dev); 282183423Smarius desc = schizo_get_desc(dev); 283183423Smarius mode = desc->sd_mode; 284183423Smarius 285183423Smarius sc->sc_dev = dev; 286183423Smarius sc->sc_node = node; 287183423Smarius sc->sc_mode = mode; 288185133Smarius sc->sc_flags = 0; 289183423Smarius 290183423Smarius /* 291183423Smarius * The Schizo has three register banks: 292183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 293183423Smarius * shared with the UPA64s interrupt mapping register banks 294183423Smarius * (1) shared Schizo controller configuration and status registers 295183423Smarius * (2) per-PBM PCI configuration space 296183423Smarius * 297183423Smarius * The Tomatillo has four register banks: 298183423Smarius * (0) per-PBM PCI configuration and status registers 299183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 300183423Smarius * machines having the `jbusppm' device shared with its Estar 301183423Smarius * register bank for bus A 302183423Smarius * (2) per-PBM PCI configuration space 303183423Smarius * (3) per-PBM interrupt concentrator registers 304183423Smarius */ 305183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 306183423Smarius 20) & 1; 307201199Smarius for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 308201199Smarius i++) { 309201199Smarius rid = i; 310201199Smarius sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 311183423Smarius SYS_RES_MEMORY, &rid, 312183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 313201199Smarius i == STX_PCI) || i == STX_CTRL)) || 314183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 315201199Smarius i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 316201199Smarius if (sc->sc_mem_res[i] == NULL) 317183423Smarius panic("%s: could not allocate register bank %d", 318201199Smarius __func__, i); 319183423Smarius } 320183423Smarius 321183423Smarius /* 322183423Smarius * Match other Schizos that are already configured against 323183423Smarius * the controller base physical address. This will be the 324183423Smarius * same for a pair of devices that share register space. 325183423Smarius */ 326183423Smarius osc = NULL; 327183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 328183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 329183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 330183423Smarius /* Found partner. */ 331183423Smarius osc = asc; 332183423Smarius break; 333183423Smarius } 334183423Smarius } 335183423Smarius if (osc == NULL) { 336183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 337183423Smarius M_NOWAIT | M_ZERO); 338183423Smarius if (sc->sc_mtx == NULL) 339183423Smarius panic("%s: could not malloc mutex", __func__); 340183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 341183423Smarius } else { 342185133Smarius if (sc->sc_mode != SCHIZO_MODE_SCZ) 343185133Smarius panic("%s: no partner expected", __func__); 344183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 345183423Smarius panic("%s: mutex not initialized", __func__); 346183423Smarius sc->sc_mtx = osc->sc_mtx; 347183423Smarius } 348183423Smarius 349183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 350183423Smarius panic("%s: could not determine IGN", __func__); 351201199Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 352201199Smarius -1) 353183423Smarius panic("%s: could not determine version", __func__); 354220038Smarius if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 355220038Smarius &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 356220038Smarius panic("%s: could not determine module-revision", __func__); 357183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 358183423Smarius prop = 33000000; 359183423Smarius 360220038Smarius if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 361220038Smarius XMS_PCI_CTRL_X_MODE) != 0) { 362220038Smarius if (sc->sc_mrev < 1) 363220038Smarius panic("PCI-X mode unsupported"); 364220038Smarius sc->sc_flags |= SCHIZO_FLAGS_XMODE; 365220038Smarius } 366183423Smarius 367220038Smarius device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 368220038Smarius if (mode == SCHIZO_MODE_XMS) 369220038Smarius printf("module-revision %d, ", sc->sc_mrev); 370220038Smarius printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 371220038Smarius 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 372220038Smarius "-X" : "", prop / 1000 / 1000); 373220038Smarius 374183423Smarius /* Set up the PCI interrupt retry timer. */ 375220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 376183423Smarius 377183423Smarius /* Set up the PCI control register. */ 378183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 379220038Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 380220038Smarius STX_PCI_CTRL_ARB_MASK); 381183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 382220038Smarius STX_PCI_CTRL_ERR_IEN; 383183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 384183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 385220038Smarius if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 386220038Smarius reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 387220038Smarius else 388220038Smarius reg |= STX_PCI_CTRL_ARB_MASK; 389183423Smarius if (mode == SCHIZO_MODE_TOM) { 390183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 391183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 392183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 393183423Smarius else 394183423Smarius reg |= STX_PCI_CTRL_PTO; 395220038Smarius } else if (mode == SCHIZO_MODE_XMS) { 396220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 397220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 398220038Smarius reg |= XMS_PCI_CTRL_X_ERRINT_EN; 399183423Smarius } 400220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 401183423Smarius 402183423Smarius /* Set up the PCI diagnostic register. */ 403183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 404183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 405183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 406220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 407183423Smarius 408183423Smarius /* 409208097Smarius * Enable DMA write parity error interrupts of version >= 7 (i.e. 410220038Smarius * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 411220038Smarius * no effect though). 412208097Smarius */ 413220038Smarius if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 414220038Smarius mode == SCHIZO_MODE_XMS) { 415208097Smarius reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 416208097Smarius reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 417220038Smarius SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 418208097Smarius } 419208097Smarius 420208097Smarius /* 421183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 422183423Smarius * Jalapeno bug). 423183423Smarius */ 424183423Smarius if (mode == SCHIZO_MODE_TOM) 425220038Smarius SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 426183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 427183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 428183423Smarius 429183423Smarius /* 430183423Smarius * Hunt through all the interrupt mapping regs and register 431186290Smarius * the interrupt controller for our interrupt vectors. We do 432186290Smarius * this early in order to be able to catch stray interrupts. 433186290Smarius * This is complicated by the fact that a pair of Schizo PBMs 434186290Smarius * shares one IGN. 435183423Smarius */ 436201199Smarius i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 437183423Smarius sizeof(prop_array)); 438205254Smarius if (i != -1) 439205254Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 440205254Smarius else { 441205254Smarius /* 442205254Smarius * If the ino-bitmap property is missing, just provide the 443205254Smarius * default set of interrupts for this controller and let 444205254Smarius * schizo_setup_intr() take care of child interrupts. 445205254Smarius */ 446205254Smarius if (sc->sc_half == 0) 447205254Smarius ino_bitmap = (1ULL << STX_UE_INO) | 448205254Smarius (1ULL << STX_CE_INO) | 449205254Smarius (1ULL << STX_PCIERR_A_INO) | 450205254Smarius (1ULL << STX_BUS_INO); 451205254Smarius else 452205254Smarius ino_bitmap = 1ULL << STX_PCIERR_B_INO; 453205254Smarius } 454201199Smarius for (i = 0; i <= STX_MAX_INO; i++) { 455201199Smarius if ((ino_bitmap & (1ULL << i)) == 0) 456183423Smarius continue; 457201199Smarius if (i == STX_FB0_INO || i == STX_FB1_INO) 458183423Smarius /* Leave for upa(4). */ 459183423Smarius continue; 460201199Smarius j = schizo_intr_register(sc, i); 461201199Smarius if (j != 0) 462186290Smarius device_printf(dev, "could not register interrupt " 463201199Smarius "controller for INO %d (%d)\n", i, j); 464183423Smarius } 465183423Smarius 466183423Smarius /* 467183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 468183423Smarius * mode as timecounter. Unfortunately, this is broken with at 469183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 470183423Smarius * 1500, which apparently actually count some different event at 471183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 472183423Smarius * power mode). Besides, one counter seems to be shared by a 473183423Smarius * "pair" of Tomatillos, too. 474183423Smarius */ 475183423Smarius if (sc->sc_half == 0) { 476220038Smarius SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 477183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 478183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 479183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 480183423Smarius if (tc == NULL) 481183423Smarius panic("%s: could not malloc timecounter", __func__); 482183423Smarius tc->tc_get_timecount = schizo_get_timecount; 483183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 484183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 485183423Smarius sizeof(prop)) == -1) 486183423Smarius panic("%s: could not determine clock frequency", 487183423Smarius __func__); 488183423Smarius tc->tc_frequency = prop; 489183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 490183423Smarius if (mode == SCHIZO_MODE_SCZ) 491183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 492183423Smarius else 493183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 494183423Smarius tc->tc_priv = sc; 495183423Smarius tc_init(tc); 496183423Smarius } 497183423Smarius 498190108Smarius /* 499190108Smarius * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 500190108Smarius * one per PBM. Schizo and XMITS additionally have a streaming 501190108Smarius * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 502225891Smarius * affected by several errata though. However, except for context 503225891Smarius * flushes, taking advantage of it should be okay even with those. 504190108Smarius */ 505220038Smarius memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 506220038Smarius sizeof(sc->sc_dma_methods)); 507220038Smarius sc->sc_is.sis_sc = sc; 508220038Smarius sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 509220038Smarius sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 510220038Smarius sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 511225891Smarius if (OF_getproplen(node, "no-streaming-cache") < 0) 512220038Smarius sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 513183423Smarius 514183423Smarius#define TSBCASE(x) \ 515183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 516183423Smarius tsbsize = (x); \ 517183423Smarius break; \ 518183423Smarius 519201199Smarius i = OF_getprop(node, "virtual-dma", (void *)prop_array, 520183423Smarius sizeof(prop_array)); 521201199Smarius if (i == -1 || i != sizeof(prop_array)) 522183423Smarius schizo_iommu_init(sc, 7, -1); 523183423Smarius else { 524183423Smarius switch (prop_array[1]) { 525183423Smarius TSBCASE(1); 526183423Smarius TSBCASE(2); 527183423Smarius TSBCASE(3); 528183423Smarius TSBCASE(4); 529183423Smarius TSBCASE(5); 530183423Smarius TSBCASE(6); 531183423Smarius TSBCASE(7); 532183423Smarius TSBCASE(8); 533183423Smarius default: 534183423Smarius panic("%s: unsupported DVMA size 0x%x", 535183423Smarius __func__, prop_array[1]); 536183423Smarius /* NOTREACHED */ 537183423Smarius } 538183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 539183423Smarius } 540185133Smarius 541183423Smarius#undef TSBCASE 542183423Smarius 543183423Smarius /* Initialize memory and I/O rmans. */ 544183423Smarius sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 545183423Smarius sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 546183423Smarius if (rman_init(&sc->sc_pci_io_rman) != 0 || 547183423Smarius rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 548183423Smarius panic("%s: failed to set up I/O rman", __func__); 549183423Smarius sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 550183423Smarius sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 551183423Smarius if (rman_init(&sc->sc_pci_mem_rman) != 0 || 552183423Smarius rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 553183423Smarius panic("%s: failed to set up memory rman", __func__); 554183423Smarius 555201199Smarius i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 556183423Smarius /* 557183423Smarius * Make sure that the expected ranges are present. The 558183423Smarius * OFW_PCI_CS_MEM64 one is not currently used though. 559183423Smarius */ 560201199Smarius if (i != STX_NRANGE) 561183423Smarius panic("%s: unsupported number of ranges", __func__); 562183423Smarius /* 563183423Smarius * Find the addresses of the various bus spaces. 564183423Smarius * There should not be multiple ones of one kind. 565183423Smarius * The physical start addresses of the ranges are the configuration, 566183423Smarius * memory and I/O handles. 567183423Smarius */ 568201199Smarius for (i = 0; i < STX_NRANGE; i++) { 569201199Smarius j = OFW_PCI_RANGE_CS(&range[i]); 570201199Smarius if (sc->sc_pci_bh[j] != 0) 571201199Smarius panic("%s: duplicate range for space %d", 572201199Smarius __func__, j); 573201199Smarius sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 574183423Smarius } 575183423Smarius free(range, M_OFWPROP); 576183423Smarius 577183423Smarius /* Register the softc, this is needed for paired Schizos. */ 578183423Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 579183423Smarius 580183423Smarius /* Allocate our tags. */ 581225931Smarius sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 582225931Smarius sc->sc_mem_res[STX_PCI]), PCI_IO_BUS_SPACE, NULL); 583225931Smarius if (sc->sc_pci_iot == NULL) 584225931Smarius panic("%s: could not allocate PCI I/O tag", __func__); 585225931Smarius sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 586225931Smarius sc->sc_mem_res[STX_PCI]), PCI_CONFIG_BUS_SPACE, NULL); 587225931Smarius if (sc->sc_pci_cfgt == NULL) 588225931Smarius panic("%s: could not allocate PCI configuration space tag", 589225931Smarius __func__); 590183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 591220038Smarius sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 592220038Smarius sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 593220038Smarius &sc->sc_pci_dmat) != 0) 594225931Smarius panic("%s: could not create PCI DMA tag", __func__); 595183423Smarius /* Customize the tag. */ 596183423Smarius sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 597220038Smarius sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods; 598183423Smarius 599183423Smarius /* 600183423Smarius * Get the bus range from the firmware. 601183423Smarius * NB: Tomatillos don't support PCI bus reenumeration. 602183423Smarius */ 603201199Smarius i = OF_getprop(node, "bus-range", (void *)prop_array, 604183423Smarius sizeof(prop_array)); 605201199Smarius if (i == -1) 606183423Smarius panic("%s: could not get bus-range", __func__); 607201199Smarius if (i != sizeof(prop_array)) 608201199Smarius panic("%s: broken bus-range (%d)", __func__, i); 609201395Smarius sc->sc_pci_secbus = prop_array[0]; 610201395Smarius sc->sc_pci_subbus = prop_array[1]; 611183423Smarius if (bootverbose) 612183423Smarius device_printf(dev, "bus range %u to %u; PCI bus %d\n", 613201395Smarius sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 614183423Smarius 615183423Smarius /* Clear any pending PCI error bits. */ 616183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 617183423Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 618183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 619220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 620220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 621183423Smarius 622183423Smarius /* 623183423Smarius * Establish handlers for interesting interrupts... 624183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 625183423Smarius * bus error interrupts for one PBM can be routed to the other 626183423Smarius * PBM though we obviously need to use the softc of the former 627183423Smarius * as the argument for the interrupt handler and the softc of 628183423Smarius * the latter as the argument for the interrupt controller. 629183423Smarius */ 630183423Smarius if (sc->sc_half == 0) { 631183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 632183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 633183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 634183423Smarius sica_sc == osc)) 635183423Smarius /* 636183423Smarius * We are the driver for PBM A and either also 637183423Smarius * registered the interrupt controller for us or 638183423Smarius * the driver for PBM B has probed first and 639183423Smarius * registered it for us. 640183423Smarius */ 641183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 642183423Smarius schizo_pci_bus); 643183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 644183423Smarius osc != NULL) 645183423Smarius /* 646183423Smarius * We are the driver for PBM A but registered 647183423Smarius * the interrupt controller for PBM B, i.e. the 648183423Smarius * driver for PBM B attached first but couldn't 649183423Smarius * set up a handler for PBM B. 650183423Smarius */ 651183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 652183423Smarius schizo_pci_bus); 653183423Smarius } else { 654183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 655183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 656183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 657183423Smarius sica_sc == osc)) 658183423Smarius /* 659183423Smarius * We are the driver for PBM B and either also 660183423Smarius * registered the interrupt controller for us or 661183423Smarius * the driver for PBM A has probed first and 662183423Smarius * registered it for us. 663183423Smarius */ 664183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 665183423Smarius schizo_pci_bus); 666183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 667183423Smarius osc != NULL) 668183423Smarius /* 669183423Smarius * We are the driver for PBM B but registered 670183423Smarius * the interrupt controller for PBM A, i.e. the 671183423Smarius * driver for PBM A attached first but couldn't 672183423Smarius * set up a handler for PBM A. 673183423Smarius */ 674183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 675183423Smarius schizo_pci_bus); 676183423Smarius } 677183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 678183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 679183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 680183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 681183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 682183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 683183423Smarius 684183423Smarius /* 685185133Smarius * According to the Schizo Errata I-13, consistent DMA flushing/ 686185133Smarius * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 687201126Smarius * so we can't use it and need to live with the consequences. With 688201126Smarius * Schizo version >= 5, CDMA flushing/syncing is usable but requires 689201126Smarius * the workaround described in Schizo Errata I-23. With Tomatillo 690201126Smarius * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 691201126Smarius * version <= 4 (i.e. revision <= 2.3) bridges additionally require 692201126Smarius * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 693185133Smarius */ 694185133Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 695201199Smarius sc->sc_mode == SCHIZO_MODE_TOM || 696201199Smarius sc->sc_mode == SCHIZO_MODE_XMS) { 697185133Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) { 698220038Smarius sc->sc_dma_methods.dm_dmamap_sync = 699220038Smarius schizo_dmamap_sync; 700220038Smarius sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 701201126Smarius /* 702201126Smarius * Some firmware versions include the CDMA interrupt 703201126Smarius * at RID 4 but most don't. With the latter we add 704201126Smarius * it ourselves at the spare RID 5. 705201126Smarius */ 706201199Smarius i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 707201126Smarius 4)); 708201199Smarius if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 709201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 710201126Smarius &sc->sc_cdma_clr); 711201199Smarius schizo_set_intr(sc, 4, i, schizo_cdma); 712201126Smarius } else { 713201199Smarius i = STX_CDMA_A_INO + sc->sc_half; 714201126Smarius if (bus_set_resource(dev, SYS_RES_IRQ, 5, 715201199Smarius INTMAP_VEC(sc->sc_ign, i), 1) != 0) 716201126Smarius panic("%s: failed to add CDMA " 717201126Smarius "interrupt", __func__); 718201199Smarius j = schizo_intr_register(sc, i); 719201199Smarius if (j != 0) 720201126Smarius panic("%s: could not register " 721201126Smarius "interrupt controller for CDMA " 722201199Smarius "(%d)", __func__, j); 723201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 724201126Smarius &sc->sc_cdma_clr); 725201199Smarius schizo_set_intr(sc, 5, i, schizo_cdma); 726201126Smarius } 727220038Smarius } else { 728220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 729220038Smarius mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 730220038Smarius NULL, MTX_SPIN); 731220038Smarius sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 732220038Smarius sc->sc_half); 733220038Smarius sc->sc_dma_methods.dm_dmamap_sync = 734220038Smarius ichip_dmamap_sync; 735185133Smarius } 736185133Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 737185133Smarius sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 738185133Smarius } 739185133Smarius 740185133Smarius /* 741183423Smarius * Set the latency timer register as this isn't always done by the 742183423Smarius * firmware. 743183423Smarius */ 744183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 745183423Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 746183423Smarius 747183423Smarius ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 748183423Smarius 749208097Smarius#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 750208097Smarius SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 751208097Smarius SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 752208097Smarius (name), CTLFLAG_RD, (arg), 0, (desc)) 753208097Smarius 754208097Smarius SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 755208097Smarius "DMA correctable errors"); 756208097Smarius SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 757208097Smarius "PCI bus non-fatal errors"); 758208097Smarius 759208097Smarius#undef SCHIZO_SYSCTL_ADD_UINT 760208097Smarius 761183423Smarius device_add_child(dev, "pci", -1); 762183423Smarius return (bus_generic_attach(dev)); 763183423Smarius} 764183423Smarius 765183423Smariusstatic void 766183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 767183423Smarius driver_filter_t handler) 768183423Smarius{ 769183423Smarius u_long vec; 770183423Smarius int rid; 771183423Smarius 772183423Smarius rid = index; 773201199Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 774201199Smarius SYS_RES_IRQ, &rid, RF_ACTIVE); 775183423Smarius if (sc->sc_irq_res[index] == NULL || 776201199Smarius INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 777201199Smarius INTIGN(vec) != sc->sc_ign || 778183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 779185133Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 780216961Smarius INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 781185133Smarius &sc->sc_ihand[index]) != 0) 782183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 783183423Smarius} 784183423Smarius 785183423Smariusstatic int 786185133Smariusschizo_intr_register(struct schizo_softc *sc, u_int ino) 787185133Smarius{ 788185133Smarius struct schizo_icarg *sica; 789185133Smarius bus_addr_t intrclr, intrmap; 790185133Smarius int error; 791185133Smarius 792185133Smarius if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 793185133Smarius return (ENXIO); 794185133Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 795185133Smarius if (sica == NULL) 796185133Smarius return (ENOMEM); 797185133Smarius sica->sica_sc = sc; 798185133Smarius sica->sica_map = intrmap; 799185133Smarius sica->sica_clr = intrclr; 800185133Smarius#ifdef SCHIZO_DEBUG 801185133Smarius device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 802185133Smarius ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 803185133Smarius (u_long)intrclr); 804185133Smarius#endif 805185133Smarius error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 806185133Smarius &schizo_ic, sica)); 807185133Smarius if (error != 0) 808185133Smarius free(sica, M_DEVBUF); 809185133Smarius return (error); 810185133Smarius} 811185133Smarius 812185133Smariusstatic int 813201199Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, 814201199Smarius bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 815183423Smarius{ 816183423Smarius bus_addr_t intrclr, intrmap; 817183423Smarius uint64_t mr; 818183423Smarius 819183423Smarius /* 820183423Smarius * XXX we only look for INOs rather than INRs since the firmware 821183423Smarius * may not provide the IGN and the IGN is constant for all devices 822183423Smarius * on that PCI controller. 823183423Smarius */ 824183423Smarius 825183423Smarius if (ino > STX_MAX_INO) { 826183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 827183423Smarius ino); 828183423Smarius return (0); 829183423Smarius } 830183423Smarius 831183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 832183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 833183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 834183423Smarius if (INTINO(mr) != ino) { 835183423Smarius device_printf(sc->sc_dev, 836183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 837183423Smarius (int)INTINO(mr), ino); 838183423Smarius return (0); 839183423Smarius } 840183423Smarius 841183423Smarius if (intrmapptr != NULL) 842183423Smarius *intrmapptr = intrmap; 843183423Smarius if (intrclrptr != NULL) 844183423Smarius *intrclrptr = intrclr; 845183423Smarius return (1); 846183423Smarius} 847183423Smarius 848183423Smarius/* 849183423Smarius * Interrupt handlers 850183423Smarius */ 851183423Smariusstatic int 852183423Smariusschizo_pci_bus(void *arg) 853183423Smarius{ 854183423Smarius struct schizo_softc *sc = arg; 855220038Smarius uint64_t afar, afsr, csr, iommu, xstat; 856183423Smarius uint32_t status; 857208097Smarius u_int fatal; 858183423Smarius 859208097Smarius fatal = 0; 860208097Smarius 861208097Smarius mtx_lock_spin(sc->sc_mtx); 862208097Smarius 863183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 864183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 865183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 866183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 867220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 868220038Smarius xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 869220038Smarius else 870220038Smarius xstat = 0; 871183423Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 872183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 873183423Smarius 874208097Smarius /* 875208097Smarius * IOMMU errors are only fatal on Tomatillo and there also only if 876208097Smarius * target abort was not signaled. 877208097Smarius */ 878208097Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 879208097Smarius (iommu & TOM_PCI_IOMMU_ERR) != 0 && 880208097Smarius ((status & PCIM_STATUS_STABORT) == 0 || 881208097Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 882208097Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 883208097Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 884208097Smarius fatal = 1; 885208097Smarius else if ((status & PCIM_STATUS_STABORT) != 0) 886208097Smarius fatal = 1; 887208097Smarius if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 888208097Smarius PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 889212378Sjhb PCIM_STATUS_MDPERR)) != 0 || 890208097Smarius (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 891208097Smarius STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 892208097Smarius SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 893208097Smarius (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 894208097Smarius STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 895208097Smarius STX_PCI_AFSR_P_UNUS)) != 0) 896208097Smarius fatal = 1; 897220038Smarius if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 898220038Smarius XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 899220038Smarius XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 900220038Smarius XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 901220038Smarius fatal = 1; 902208097Smarius if (fatal == 0) 903208097Smarius sc->sc_stats_pci_non_fatal++; 904183423Smarius 905208097Smarius device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 906220038Smarius "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 907220038Smarius 'A' + sc->sc_half, (unsigned long long)afar, 908220038Smarius (unsigned long long)afsr, (unsigned long long)csr, 909220038Smarius (unsigned long long)iommu, (unsigned long long)xstat, status); 910183423Smarius 911183423Smarius /* Clear the error bits that we caught. */ 912183423Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 913183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 914183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 915183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 916208097Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 917220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 918220038Smarius SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 919208097Smarius 920208097Smarius mtx_unlock_spin(sc->sc_mtx); 921208097Smarius 922208097Smarius if (fatal != 0) 923208097Smarius panic("%s: fatal PCI bus error", 924208097Smarius device_get_nameunit(sc->sc_dev)); 925183423Smarius return (FILTER_HANDLED); 926183423Smarius} 927183423Smarius 928183423Smariusstatic int 929183423Smariusschizo_ue(void *arg) 930183423Smarius{ 931183423Smarius struct schizo_softc *sc = arg; 932183423Smarius uint64_t afar, afsr; 933183423Smarius int i; 934183423Smarius 935183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 936183423Smarius for (i = 0; i < 1000; i++) 937183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 938183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 939183423Smarius break; 940183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 941206020Smarius device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 942183423Smarius (unsigned long long)afsr); 943183423Smarius return (FILTER_HANDLED); 944183423Smarius} 945183423Smarius 946183423Smariusstatic int 947183423Smariusschizo_ce(void *arg) 948183423Smarius{ 949183423Smarius struct schizo_softc *sc = arg; 950183423Smarius uint64_t afar, afsr; 951183423Smarius int i; 952183423Smarius 953183423Smarius mtx_lock_spin(sc->sc_mtx); 954208097Smarius 955183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 956183423Smarius for (i = 0; i < 1000; i++) 957183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 958183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 959183423Smarius break; 960208097Smarius sc->sc_stats_dma_ce++; 961183423Smarius device_printf(sc->sc_dev, 962183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 963183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 964208097Smarius 965183423Smarius /* Clear the error bits that we caught. */ 966183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 967208097Smarius 968183423Smarius mtx_unlock_spin(sc->sc_mtx); 969208097Smarius 970183423Smarius return (FILTER_HANDLED); 971183423Smarius} 972183423Smarius 973183423Smariusstatic int 974183423Smariusschizo_host_bus(void *arg) 975183423Smarius{ 976183423Smarius struct schizo_softc *sc = arg; 977183423Smarius uint64_t errlog; 978183423Smarius 979183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 980206020Smarius panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 981183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 982183423Smarius (unsigned long long)errlog); 983183423Smarius return (FILTER_HANDLED); 984183423Smarius} 985183423Smarius 986185133Smariusstatic int 987185133Smariusschizo_cdma(void *arg) 988185133Smarius{ 989185133Smarius struct schizo_softc *sc = arg; 990185133Smarius 991220038Smarius atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_RECEIVED); 992185133Smarius return (FILTER_HANDLED); 993185133Smarius} 994185133Smarius 995183423Smariusstatic void 996183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 997183423Smarius{ 998183423Smarius 999183423Smarius /* Punch in our copies. */ 1000220038Smarius sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1001220038Smarius sc->sc_is.sis_is.is_bushandle = 1002220038Smarius rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 1003220038Smarius sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 1004220038Smarius sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 1005220038Smarius sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 1006220038Smarius sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 1007220038Smarius sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 1008220038Smarius sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 1009183423Smarius 1010220038Smarius iommu_init(device_get_nameunit(sc->sc_dev), 1011220038Smarius (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 1012183423Smarius} 1013183423Smarius 1014183423Smariusstatic int 1015183423Smariusschizo_maxslots(device_t dev) 1016183423Smarius{ 1017183423Smarius struct schizo_softc *sc; 1018183423Smarius 1019183423Smarius sc = device_get_softc(dev); 1020183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 1021183423Smarius return (sc->sc_half == 0 ? 4 : 6); 1022183423Smarius 1023183423Smarius /* XXX: is this correct? */ 1024183423Smarius return (PCI_SLOTMAX); 1025183423Smarius} 1026183423Smarius 1027183423Smariusstatic uint32_t 1028183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 1029183423Smarius int width) 1030183423Smarius{ 1031183423Smarius struct schizo_softc *sc; 1032183423Smarius bus_space_handle_t bh; 1033183423Smarius u_long offset = 0; 1034183423Smarius uint32_t r, wrd; 1035183423Smarius int i; 1036183423Smarius uint16_t shrt; 1037183423Smarius uint8_t byte; 1038183423Smarius 1039183423Smarius sc = device_get_softc(dev); 1040201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1041201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1042201395Smarius return (-1); 1043183423Smarius 1044183423Smarius /* 1045183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 1046183423Smarius */ 1047183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1048183423Smarius slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1049183423Smarius reg + width > 0x80) 1050183423Smarius return (0); 1051183423Smarius 1052183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1053183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1054183423Smarius switch (width) { 1055183423Smarius case 1: 1056183423Smarius i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1057183423Smarius r = byte; 1058183423Smarius break; 1059183423Smarius case 2: 1060183423Smarius i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1061183423Smarius r = shrt; 1062183423Smarius break; 1063183423Smarius case 4: 1064183423Smarius i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1065183423Smarius r = wrd; 1066183423Smarius break; 1067183423Smarius default: 1068183423Smarius panic("%s: bad width", __func__); 1069183423Smarius /* NOTREACHED */ 1070183423Smarius } 1071183423Smarius 1072183423Smarius if (i) { 1073183423Smarius#ifdef SCHIZO_DEBUG 1074183423Smarius printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1075183423Smarius __func__, bus, slot, func, reg); 1076183423Smarius#endif 1077183423Smarius r = -1; 1078183423Smarius } 1079183423Smarius return (r); 1080183423Smarius} 1081183423Smarius 1082183423Smariusstatic void 1083201199Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1084201199Smarius u_int reg, uint32_t val, int width) 1085183423Smarius{ 1086183423Smarius struct schizo_softc *sc; 1087183423Smarius bus_space_handle_t bh; 1088183423Smarius u_long offset = 0; 1089183423Smarius 1090183423Smarius sc = device_get_softc(dev); 1091201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1092201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1093201395Smarius return; 1094201395Smarius 1095183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1096183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1097183423Smarius switch (width) { 1098183423Smarius case 1: 1099183423Smarius bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1100183423Smarius break; 1101183423Smarius case 2: 1102183423Smarius bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1103183423Smarius break; 1104183423Smarius case 4: 1105183423Smarius bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1106183423Smarius break; 1107183423Smarius default: 1108183423Smarius panic("%s: bad width", __func__); 1109183423Smarius /* NOTREACHED */ 1110183423Smarius } 1111183423Smarius} 1112183423Smarius 1113183423Smariusstatic int 1114183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 1115183423Smarius{ 1116183423Smarius struct schizo_softc *sc; 1117183423Smarius struct ofw_pci_register reg; 1118183423Smarius ofw_pci_intr_t pintr, mintr; 1119183423Smarius uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1120183423Smarius 1121183423Smarius sc = device_get_softc(bridge); 1122183423Smarius pintr = pin; 1123201199Smarius if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1124201199Smarius ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1125209298Snwhitehorn NULL, maskbuf)) 1126183423Smarius return (mintr); 1127183423Smarius 1128183423Smarius device_printf(bridge, "could not route pin %d for device %d.%d\n", 1129183423Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 1130183423Smarius return (PCI_INVALID_IRQ); 1131183423Smarius} 1132183423Smarius 1133183423Smariusstatic int 1134183423Smariusschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1135183423Smarius{ 1136183423Smarius struct schizo_softc *sc; 1137183423Smarius 1138183423Smarius sc = device_get_softc(dev); 1139183423Smarius switch (which) { 1140183423Smarius case PCIB_IVAR_DOMAIN: 1141183423Smarius *result = device_get_unit(dev); 1142183423Smarius return (0); 1143183423Smarius case PCIB_IVAR_BUS: 1144183423Smarius *result = sc->sc_pci_secbus; 1145183423Smarius return (0); 1146183423Smarius } 1147183423Smarius return (ENOENT); 1148183423Smarius} 1149183423Smarius 1150220038Smariusstatic void 1151220038Smariusschizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1152185133Smarius{ 1153185133Smarius struct timeval cur, end; 1154220038Smarius struct schizo_iommu_state *sis = dt->dt_cookie; 1155220038Smarius struct schizo_softc *sc = sis->sis_sc; 1156220038Smarius int res; 1157185133Smarius 1158220038Smarius if ((map->dm_flags & DMF_STREAMED) != 0) { 1159220038Smarius iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1160220038Smarius return; 1161220038Smarius } 1162220038Smarius 1163220038Smarius if ((map->dm_flags & DMF_LOADED) == 0) 1164220038Smarius return; 1165220038Smarius 1166220038Smarius if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1167220038Smarius /* 1168225931Smarius * Note that in order to allow this function to be called from 1169220038Smarius * filters we would need to use a spin mutex for serialization 1170220038Smarius * but given that these disable interrupts we have to emulate 1171220038Smarius * one. 1172220038Smarius */ 1173220038Smarius for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1174220038Smarius SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1175220038Smarius ; 1176220038Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1177185133Smarius microuptime(&cur); 1178220038Smarius end.tv_sec = 1; 1179220038Smarius end.tv_usec = 0; 1180220038Smarius timevaladd(&end, &cur); 1181220038Smarius for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1182220038Smarius SCHIZO_CDMA_STATE_RECEIVED, SCHIZO_CDMA_STATE_IDLE)) == 1183220038Smarius 0 && timevalcmp(&cur, &end, <=);) 1184220038Smarius microuptime(&cur); 1185220038Smarius if (res == 0) 1186220038Smarius panic("%s: DMA does not sync", __func__); 1187220038Smarius } 1188220038Smarius 1189220038Smarius if ((op & BUS_DMASYNC_PREWRITE) != 0) 1190220038Smarius membar(Sync); 1191185133Smarius} 1192185133Smarius 1193183423Smarius#define VIS_BLOCKSIZE 64 1194183423Smarius 1195220038Smariusstatic void 1196220038Smariusichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1197183423Smarius{ 1198183423Smarius static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1199185133Smarius struct timeval cur, end; 1200220038Smarius struct schizo_iommu_state *sis = dt->dt_cookie; 1201220038Smarius struct schizo_softc *sc = sis->sis_sc; 1202184428Smarius register_t reg, s; 1203183423Smarius 1204220038Smarius if ((map->dm_flags & DMF_STREAMED) != 0) { 1205220038Smarius iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1206220038Smarius return; 1207220038Smarius } 1208220038Smarius 1209220038Smarius if ((map->dm_flags & DMF_LOADED) == 0) 1210220038Smarius return; 1211220038Smarius 1212220038Smarius if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1213220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 1214220038Smarius mtx_lock_spin(&sc->sc_sync_mtx); 1215220038Smarius SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1216220038Smarius sc->sc_sync_val); 1217185133Smarius microuptime(&cur); 1218220038Smarius end.tv_sec = 1; 1219220038Smarius end.tv_usec = 0; 1220220038Smarius timevaladd(&end, &cur); 1221220038Smarius for (; ((reg = SCHIZO_PCI_READ_8(sc, 1222220038Smarius TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1223220038Smarius timevalcmp(&cur, &end, <=);) 1224220038Smarius microuptime(&cur); 1225220038Smarius if ((reg & sc->sc_sync_val) != 0) 1226220038Smarius panic("%s: DMA does not sync", __func__); 1227220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 1228220038Smarius mtx_unlock_spin(&sc->sc_sync_mtx); 1229220038Smarius else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1230220038Smarius s = intr_disable(); 1231220038Smarius reg = rd(fprs); 1232220038Smarius wr(fprs, reg | FPRS_FEF, 0); 1233220038Smarius __asm __volatile("stda %%f0, [%0] %1" 1234220038Smarius : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1235220038Smarius membar(Sync); 1236220038Smarius wr(fprs, reg, 0); 1237220038Smarius intr_restore(s); 1238220038Smarius return; 1239220038Smarius } 1240220038Smarius } 1241183423Smarius 1242220038Smarius if ((op & BUS_DMASYNC_PREWRITE) != 0) 1243184428Smarius membar(Sync); 1244183423Smarius} 1245183423Smarius 1246183423Smariusstatic void 1247183423Smariusschizo_intr_enable(void *arg) 1248183423Smarius{ 1249183423Smarius struct intr_vector *iv = arg; 1250183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1251183423Smarius 1252183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1253183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1254183423Smarius} 1255183423Smarius 1256183423Smariusstatic void 1257183423Smariusschizo_intr_disable(void *arg) 1258183423Smarius{ 1259183423Smarius struct intr_vector *iv = arg; 1260183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1261183423Smarius 1262183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1263183423Smarius} 1264183423Smarius 1265183423Smariusstatic void 1266183423Smariusschizo_intr_assign(void *arg) 1267183423Smarius{ 1268183423Smarius struct intr_vector *iv = arg; 1269183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1270183423Smarius 1271183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1272183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1273183423Smarius} 1274183423Smarius 1275183423Smariusstatic void 1276183423Smariusschizo_intr_clear(void *arg) 1277183423Smarius{ 1278183423Smarius struct intr_vector *iv = arg; 1279183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1280183423Smarius 1281206018Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1282183423Smarius} 1283183423Smarius 1284183423Smariusstatic int 1285183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1286183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1287183423Smarius void **cookiep) 1288183423Smarius{ 1289183423Smarius struct schizo_softc *sc; 1290183423Smarius u_long vec; 1291220038Smarius int error; 1292183423Smarius 1293183423Smarius sc = device_get_softc(dev); 1294183423Smarius /* 1295186290Smarius * Make sure the vector is fully specified. 1296183423Smarius */ 1297183423Smarius vec = rman_get_start(ires); 1298186290Smarius if (INTIGN(vec) != sc->sc_ign) { 1299183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1300183423Smarius return (EINVAL); 1301183423Smarius } 1302183423Smarius 1303186290Smarius if (intr_vectors[vec].iv_ic == &schizo_ic) { 1304186290Smarius /* 1305186290Smarius * Ensure we use the right softc in case the interrupt 1306186290Smarius * is routed to our companion PBM for some odd reason. 1307186290Smarius */ 1308186290Smarius sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1309186290Smarius sica_sc; 1310186290Smarius } else if (intr_vectors[vec].iv_ic == NULL) { 1311186290Smarius /* 1312186290Smarius * Work around broken firmware which misses entries in 1313186290Smarius * the ino-bitmap. 1314186290Smarius */ 1315186290Smarius error = schizo_intr_register(sc, INTINO(vec)); 1316186290Smarius if (error != 0) { 1317186290Smarius device_printf(dev, "could not register interrupt " 1318186290Smarius "controller for vector 0x%lx (%d)\n", vec, error); 1319186290Smarius return (error); 1320186290Smarius } 1321190108Smarius if (bootverbose) 1322190108Smarius device_printf(dev, "belatedly registered as " 1323190108Smarius "interrupt controller for vector 0x%lx\n", vec); 1324186290Smarius } else { 1325186290Smarius device_printf(dev, 1326186290Smarius "invalid interrupt controller for vector 0x%lx\n", vec); 1327186290Smarius return (EINVAL); 1328186290Smarius } 1329183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1330183423Smarius arg, cookiep)); 1331183423Smarius} 1332183423Smarius 1333183423Smariusstatic struct resource * 1334183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1335183423Smarius u_long start, u_long end, u_long count, u_int flags) 1336183423Smarius{ 1337183423Smarius struct schizo_softc *sc; 1338183423Smarius struct resource *rv; 1339183423Smarius struct rman *rm; 1340183423Smarius 1341183423Smarius sc = device_get_softc(bus); 1342225931Smarius switch (type) { 1343225931Smarius case SYS_RES_IRQ: 1344183423Smarius /* 1345183423Smarius * XXX: Don't accept blank ranges for now, only single 1346183423Smarius * interrupts. The other case should not happen with 1347183423Smarius * the MI PCI code... 1348183423Smarius * XXX: This may return a resource that is out of the 1349183423Smarius * range that was specified. Is this correct...? 1350183423Smarius */ 1351183423Smarius if (start != end) 1352183423Smarius panic("%s: XXX: interrupt range", __func__); 1353183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1354225931Smarius return (bus_generic_alloc_resource(bus, child, type, rid, 1355225931Smarius start, end, count, flags)); 1356183423Smarius case SYS_RES_MEMORY: 1357183423Smarius rm = &sc->sc_pci_mem_rman; 1358183423Smarius break; 1359183423Smarius case SYS_RES_IOPORT: 1360183423Smarius rm = &sc->sc_pci_io_rman; 1361183423Smarius break; 1362183423Smarius default: 1363183423Smarius return (NULL); 1364183423Smarius } 1365183423Smarius 1366225931Smarius rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 1367225931Smarius child); 1368183423Smarius if (rv == NULL) 1369183423Smarius return (NULL); 1370183423Smarius rman_set_rid(rv, *rid); 1371183423Smarius 1372225931Smarius if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type, 1373225931Smarius *rid, rv) != 0) { 1374225931Smarius rman_release_resource(rv); 1375225931Smarius return (NULL); 1376183423Smarius } 1377183423Smarius return (rv); 1378183423Smarius} 1379183423Smarius 1380183423Smariusstatic int 1381183423Smariusschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1382183423Smarius struct resource *r) 1383183423Smarius{ 1384225931Smarius struct schizo_softc *sc; 1385225931Smarius struct bus_space_tag *tag; 1386183423Smarius 1387225931Smarius sc = device_get_softc(bus); 1388225931Smarius switch (type) { 1389225931Smarius case SYS_RES_IRQ: 1390225931Smarius return (bus_generic_activate_resource(bus, child, type, rid, 1391225931Smarius r)); 1392225931Smarius case SYS_RES_MEMORY: 1393225931Smarius tag = sparc64_alloc_bus_tag(r, rman_get_bustag( 1394225931Smarius sc->sc_mem_res[STX_PCI]), PCI_MEMORY_BUS_SPACE, NULL); 1395225931Smarius if (tag == NULL) 1396225931Smarius return (ENOMEM); 1397225931Smarius rman_set_bustag(r, tag); 1398225931Smarius rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] + 1399225931Smarius rman_get_start(r)); 1400225931Smarius break; 1401225931Smarius case SYS_RES_IOPORT: 1402225931Smarius rman_set_bustag(r, sc->sc_pci_iot); 1403225931Smarius rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] + 1404225931Smarius rman_get_start(r)); 1405225931Smarius break; 1406183423Smarius } 1407183423Smarius return (rman_activate_resource(r)); 1408183423Smarius} 1409183423Smarius 1410183423Smariusstatic int 1411225931Smariusschizo_adjust_resource(device_t bus, device_t child, int type, 1412225931Smarius struct resource *r, u_long start, u_long end) 1413183423Smarius{ 1414225931Smarius struct schizo_softc *sc; 1415225931Smarius struct rman *rm; 1416183423Smarius 1417225931Smarius sc = device_get_softc(bus); 1418225931Smarius switch (type) { 1419225931Smarius case SYS_RES_IRQ: 1420225931Smarius return (bus_generic_adjust_resource(bus, child, type, r, 1421225931Smarius start, end)); 1422225931Smarius case SYS_RES_MEMORY: 1423225931Smarius rm = &sc->sc_pci_mem_rman; 1424225931Smarius break; 1425225931Smarius case SYS_RES_IOPORT: 1426225931Smarius rm = &sc->sc_pci_io_rman; 1427225931Smarius break; 1428225931Smarius default: 1429225931Smarius return (EINVAL); 1430183423Smarius } 1431225931Smarius if (rman_is_region_manager(r, rm) == 0) 1432225931Smarius return (EINVAL); 1433225931Smarius return (rman_adjust_resource(r, start, end)); 1434183423Smarius} 1435183423Smarius 1436183423Smariusstatic bus_dma_tag_t 1437220038Smariusschizo_get_dma_tag(device_t bus, device_t child __unused) 1438183423Smarius{ 1439183423Smarius struct schizo_softc *sc; 1440183423Smarius 1441183423Smarius sc = device_get_softc(bus); 1442183423Smarius return (sc->sc_pci_dmat); 1443183423Smarius} 1444183423Smarius 1445183423Smariusstatic phandle_t 1446220038Smariusschizo_get_node(device_t bus, device_t child __unused) 1447183423Smarius{ 1448183423Smarius struct schizo_softc *sc; 1449183423Smarius 1450183423Smarius sc = device_get_softc(bus); 1451183423Smarius /* We only have one child, the PCI bus, which needs our own node. */ 1452183423Smarius return (sc->sc_node); 1453183423Smarius} 1454183423Smarius 1455220038Smariusstatic void 1456220038Smariusschizo_setup_device(device_t bus, device_t child) 1457220038Smarius{ 1458220038Smarius struct schizo_softc *sc; 1459220038Smarius uint64_t reg; 1460220038Smarius int capreg; 1461220038Smarius 1462220038Smarius sc = device_get_softc(bus); 1463220038Smarius /* 1464220038Smarius * Disable bus parking in order to work around a bus hang caused by 1465220038Smarius * Casinni/Skyhawk combinations. 1466225931Smarius */ 1467220038Smarius if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1468220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1469220038Smarius STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1470220038Smarius 1471220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) { 1472220038Smarius /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1473220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1474220038Smarius (pci_read_config(child, PCIR_HDRTYPE, 1) & 1475220038Smarius PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1476220038Smarius pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1477220038Smarius pci_write_config(child, capreg + PCIXR_COMMAND, 1478220038Smarius pci_read_config(child, capreg + PCIXR_COMMAND, 1479220038Smarius 2) & 0x7c, 2); 1480220038Smarius /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1481220038Smarius if (sc->sc_mrev >= 4) { 1482220038Smarius reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1483220038Smarius 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1484220038Smarius if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1485220038Smarius XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1486220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1487220038Smarius } 1488220038Smarius } 1489220038Smarius} 1490220038Smarius 1491183423Smariusstatic u_int 1492183423Smariusschizo_get_timecount(struct timecounter *tc) 1493183423Smarius{ 1494183423Smarius struct schizo_softc *sc; 1495183423Smarius 1496183423Smarius sc = tc->tc_priv; 1497223959Smarius return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1498223959Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >> 1499223959Smarius STX_CTRL_PERF_CNT_CNT0_SHIFT); 1500183423Smarius} 1501