schizo.c revision 227843
1283514Sarybchik/*- 2283514Sarybchik * Copyright (c) 1999, 2000 Matthew R. Green 3283514Sarybchik * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4283514Sarybchik * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 5283514Sarybchik * All rights reserved. 6283514Sarybchik * 7283514Sarybchik * Redistribution and use in source and binary forms, with or without 8283514Sarybchik * modification, are permitted provided that the following conditions 9283514Sarybchik * are met: 10283514Sarybchik * 1. Redistributions of source code must retain the above copyright 11283514Sarybchik * notice, this list of conditions and the following disclaimer. 12283514Sarybchik * 2. Redistributions in binary form must reproduce the above copyright 13283514Sarybchik * notice, this list of conditions and the following disclaimer in the 14283514Sarybchik * documentation and/or other materials provided with the distribution. 15283514Sarybchik * 3. The name of the author may not be used to endorse or promote products 16283514Sarybchik * derived from this software without specific prior written permission. 17283514Sarybchik * 18283514Sarybchik * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19283514Sarybchik * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20283514Sarybchik * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21283514Sarybchik * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22283514Sarybchik * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23283514Sarybchik * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24283514Sarybchik * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25283514Sarybchik * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26283514Sarybchik * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27283514Sarybchik * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28283514Sarybchik * SUCH DAMAGE. 29283514Sarybchik * 30283514Sarybchik * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31283514Sarybchik * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32283514Sarybchik */ 33283514Sarybchik 34283514Sarybchik#include <sys/cdefs.h> 35283514Sarybchik__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 227843 2011-11-22 21:28:20Z marius $"); 36283514Sarybchik 37283514Sarybchik/* 38283514Sarybchik * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 39283514Sarybchik * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 40283514Sarybchik */ 41283514Sarybchik 42283514Sarybchik#include "opt_ofw_pci.h" 43283514Sarybchik#include "opt_schizo.h" 44283514Sarybchik 45283514Sarybchik#include <sys/param.h> 46283514Sarybchik#include <sys/systm.h> 47283514Sarybchik#include <sys/bus.h> 48283514Sarybchik#include <sys/kernel.h> 49283514Sarybchik#include <sys/lock.h> 50283514Sarybchik#include <sys/malloc.h> 51283514Sarybchik#include <sys/module.h> 52283514Sarybchik#include <sys/mutex.h> 53283514Sarybchik#include <sys/pcpu.h> 54283514Sarybchik#include <sys/rman.h> 55293974Sarybchik#include <sys/sysctl.h> 56293974Sarybchik#include <sys/time.h> 57293974Sarybchik#include <sys/timetc.h> 58283514Sarybchik 59283514Sarybchik#include <dev/ofw/ofw_bus.h> 60283514Sarybchik#include <dev/ofw/ofw_pci.h> 61283514Sarybchik#include <dev/ofw/openfirm.h> 62283514Sarybchik 63283514Sarybchik#include <machine/bus.h> 64283514Sarybchik#include <machine/bus_common.h> 65283514Sarybchik#include <machine/bus_private.h> 66283514Sarybchik#include <machine/fsr.h> 67283514Sarybchik#include <machine/iommureg.h> 68283514Sarybchik#include <machine/iommuvar.h> 69283514Sarybchik#include <machine/resource.h> 70293974Sarybchik 71293974Sarybchik#include <dev/pci/pcireg.h> 72293974Sarybchik#include <dev/pci/pcivar.h> 73283514Sarybchik 74283514Sarybchik#include <sparc64/pci/ofw_pci.h> 75283514Sarybchik#include <sparc64/pci/schizoreg.h> 76283514Sarybchik#include <sparc64/pci/schizovar.h> 77283514Sarybchik 78293974Sarybchik#include "pcib_if.h" 79293974Sarybchik 80293974Sarybchikstatic const struct schizo_desc *schizo_get_desc(device_t); 81283514Sarybchikstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82283514Sarybchik driver_filter_t); 83283514Sarybchikstatic void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 84283514Sarybchik bus_dmasync_op_t op); 85283514Sarybchikstatic void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 86283514Sarybchik bus_dmasync_op_t op); 87283514Sarybchikstatic void schizo_intr_enable(void *); 88283514Sarybchikstatic void schizo_intr_disable(void *); 89283514Sarybchikstatic void schizo_intr_assign(void *); 90283514Sarybchikstatic void schizo_intr_clear(void *); 91283514Sarybchikstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 92283514Sarybchikstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 93293974Sarybchik bus_addr_t *, bus_addr_t *); 94293974Sarybchikstatic timecounter_get_t schizo_get_timecount; 95293974Sarybchik 96283514Sarybchik/* Interrupt handlers */ 97283514Sarybchikstatic driver_filter_t schizo_pci_bus; 98283514Sarybchikstatic driver_filter_t schizo_ue; 99293974Sarybchikstatic driver_filter_t schizo_ce; 100283514Sarybchikstatic driver_filter_t schizo_host_bus; 101293974Sarybchikstatic driver_filter_t schizo_cdma; 102283514Sarybchik 103283514Sarybchik/* IOMMU support */ 104283514Sarybchikstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 105283514Sarybchik 106283514Sarybchik/* 107293974Sarybchik * Methods 108293974Sarybchik */ 109293974Sarybchikstatic device_probe_t schizo_probe; 110283514Sarybchikstatic device_attach_t schizo_attach; 111283514Sarybchikstatic bus_read_ivar_t schizo_read_ivar; 112283514Sarybchikstatic bus_setup_intr_t schizo_setup_intr; 113283514Sarybchikstatic bus_alloc_resource_t schizo_alloc_resource; 114283514Sarybchikstatic bus_activate_resource_t schizo_activate_resource; 115283514Sarybchikstatic bus_adjust_resource_t schizo_adjust_resource; 116283514Sarybchikstatic bus_get_dma_tag_t schizo_get_dma_tag; 117283514Sarybchikstatic pcib_maxslots_t schizo_maxslots; 118283514Sarybchikstatic pcib_read_config_t schizo_read_config; 119283514Sarybchikstatic pcib_write_config_t schizo_write_config; 120283514Sarybchikstatic pcib_route_interrupt_t schizo_route_interrupt; 121283514Sarybchikstatic ofw_bus_get_node_t schizo_get_node; 122283514Sarybchikstatic ofw_pci_setup_device_t schizo_setup_device; 123283514Sarybchik 124283514Sarybchikstatic device_method_t schizo_methods[] = { 125283514Sarybchik /* Device interface */ 126283514Sarybchik DEVMETHOD(device_probe, schizo_probe), 127283514Sarybchik DEVMETHOD(device_attach, schizo_attach), 128283514Sarybchik DEVMETHOD(device_shutdown, bus_generic_shutdown), 129293974Sarybchik DEVMETHOD(device_suspend, bus_generic_suspend), 130293974Sarybchik DEVMETHOD(device_resume, bus_generic_resume), 131293974Sarybchik 132283514Sarybchik /* Bus interface */ 133283514Sarybchik DEVMETHOD(bus_read_ivar, schizo_read_ivar), 134283514Sarybchik DEVMETHOD(bus_setup_intr, schizo_setup_intr), 135283514Sarybchik DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 136283514Sarybchik DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 137293974Sarybchik DEVMETHOD(bus_activate_resource, schizo_activate_resource), 138293974Sarybchik DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 139283514Sarybchik DEVMETHOD(bus_adjust_resource, schizo_adjust_resource), 140283514Sarybchik DEVMETHOD(bus_release_resource, bus_generic_release_resource), 141283514Sarybchik DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 142293974Sarybchik 143293974Sarybchik /* pcib interface */ 144293974Sarybchik DEVMETHOD(pcib_maxslots, schizo_maxslots), 145293974Sarybchik DEVMETHOD(pcib_read_config, schizo_read_config), 146283514Sarybchik DEVMETHOD(pcib_write_config, schizo_write_config), 147283514Sarybchik DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 148293939Sarybchik 149293939Sarybchik /* ofw_bus interface */ 150293939Sarybchik DEVMETHOD(ofw_bus_get_node, schizo_get_node), 151293939Sarybchik 152293939Sarybchik /* ofw_pci interface */ 153293939Sarybchik DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 154293939Sarybchik 155293958Sarybchik DEVMETHOD_END 156293958Sarybchik}; 157293958Sarybchik 158293958Sarybchikstatic devclass_t schizo_devclass; 159293958Sarybchik 160293958SarybchikDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 161293958Sarybchik sizeof(struct schizo_softc)); 162283514SarybchikEARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 163283514Sarybchik BUS_PASS_BUS); 164283514Sarybchik 165283514Sarybchikstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 166283514Sarybchik SLIST_HEAD_INITIALIZER(schizo_softcs); 167283514Sarybchik 168283514Sarybchikstatic const struct intr_controller schizo_ic = { 169283514Sarybchik schizo_intr_enable, 170283514Sarybchik schizo_intr_disable, 171283514Sarybchik schizo_intr_assign, 172283514Sarybchik schizo_intr_clear 173283514Sarybchik}; 174283514Sarybchik 175283514Sarybchikstruct schizo_icarg { 176283514Sarybchik struct schizo_softc *sica_sc; 177283514Sarybchik bus_addr_t sica_map; 178283514Sarybchik bus_addr_t sica_clr; 179283514Sarybchik}; 180283514Sarybchik 181283514Sarybchik#define SCHIZO_PERF_CNT_QLTY 100 182283514Sarybchik 183293999Sarybchik#define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 184283514Sarybchik bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 185293999Sarybchik#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 186283514Sarybchik bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 187283514Sarybchik#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 188293999Sarybchik bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 189283514Sarybchik 190293999Sarybchik#ifndef SCHIZO_DEBUG 191283514Sarybchik#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 192283514Sarybchik SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 193283514Sarybchik#else 194283514Sarybchik#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 195293974Sarybchik device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 196293974Sarybchik (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 197293974Sarybchik (unsigned long long)(v)); \ 198283514Sarybchik SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 199283514Sarybchik } while (0) 200283514Sarybchik#endif 201283514Sarybchik 202283514Sarybchik#define SCHIZO_PCI_READ_8(sc, offs) \ 203293974Sarybchik SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 204293974Sarybchik#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 205283514Sarybchik SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 206283514Sarybchik#define SCHIZO_CTRL_READ_8(sc, offs) \ 207283514Sarybchik SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 208283514Sarybchik#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 209283514Sarybchik SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 210283514Sarybchik#define SCHIZO_PCICFG_READ_8(sc, offs) \ 211283514Sarybchik SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 212283514Sarybchik#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 213283514Sarybchik SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 214283514Sarybchik#define SCHIZO_ICON_READ_8(sc, offs) \ 215283514Sarybchik SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 216283514Sarybchik#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 217283514Sarybchik SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 218283514Sarybchik 219293974Sarybchik#define SCHIZO_PCI_SET(sc, offs, v) \ 220293974Sarybchik SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 221293974Sarybchik#define SCHIZO_CTRL_SET(sc, offs, v) \ 222283514Sarybchik SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 223283514Sarybchik 224283514Sarybchikstruct schizo_desc { 225283514Sarybchik const char *sd_string; 226283514Sarybchik int sd_mode; 227283514Sarybchik const char *sd_name; 228283514Sarybchik}; 229283514Sarybchik 230283514Sarybchikstatic const struct schizo_desc const schizo_compats[] = { 231283514Sarybchik { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 232283514Sarybchik#if 0 233283514Sarybchik { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 234283514Sarybchik#endif 235283514Sarybchik { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 236283514Sarybchik { NULL, 0, NULL } 237283514Sarybchik}; 238283514Sarybchik 239283514Sarybchikstatic const struct schizo_desc * 240283514Sarybchikschizo_get_desc(device_t dev) 241283514Sarybchik{ 242283514Sarybchik const struct schizo_desc *desc; 243283514Sarybchik const char *compat; 244283514Sarybchik 245283514Sarybchik compat = ofw_bus_get_compat(dev); 246283514Sarybchik if (compat == NULL) 247283514Sarybchik return (NULL); 248283514Sarybchik for (desc = schizo_compats; desc->sd_string != NULL; desc++) 249283514Sarybchik if (strcmp(desc->sd_string, compat) == 0) 250283514Sarybchik return (desc); 251283514Sarybchik return (NULL); 252283514Sarybchik} 253283514Sarybchik 254283514Sarybchikstatic int 255283514Sarybchikschizo_probe(device_t dev) 256283514Sarybchik{ 257283514Sarybchik const char *dtype; 258283514Sarybchik 259283514Sarybchik dtype = ofw_bus_get_type(dev); 260283514Sarybchik if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 261283514Sarybchik schizo_get_desc(dev) != NULL) { 262293999Sarybchik device_set_desc(dev, "Sun Host-PCI bridge"); 263283514Sarybchik return (0); 264293999Sarybchik } 265283514Sarybchik return (ENXIO); 266283514Sarybchik} 267283514Sarybchik 268283514Sarybchikstatic int 269283514Sarybchikschizo_attach(device_t dev) 270283514Sarybchik{ 271283514Sarybchik struct ofw_pci_ranges *range; 272283514Sarybchik const struct schizo_desc *desc; 273283514Sarybchik struct schizo_softc *asc, *sc, *osc; 274283514Sarybchik struct timecounter *tc; 275283514Sarybchik uint64_t ino_bitmap, reg; 276283514Sarybchik phandle_t node; 277283514Sarybchik uint32_t prop, prop_array[2]; 278283514Sarybchik int i, j, mode, rid, tsbsize; 279283514Sarybchik 280283514Sarybchik sc = device_get_softc(dev); 281283514Sarybchik node = ofw_bus_get_node(dev); 282283514Sarybchik desc = schizo_get_desc(dev); 283283514Sarybchik mode = desc->sd_mode; 284283514Sarybchik 285283514Sarybchik sc->sc_dev = dev; 286283514Sarybchik sc->sc_node = node; 287283514Sarybchik sc->sc_mode = mode; 288283514Sarybchik sc->sc_flags = 0; 289283514Sarybchik 290283514Sarybchik /* 291283514Sarybchik * The Schizo has three register banks: 292283514Sarybchik * (0) per-PBM PCI configuration and status registers, but for bus B 293283514Sarybchik * shared with the UPA64s interrupt mapping register banks 294283514Sarybchik * (1) shared Schizo controller configuration and status registers 295283514Sarybchik * (2) per-PBM PCI configuration space 296283514Sarybchik * 297283514Sarybchik * The Tomatillo has four register banks: 298283514Sarybchik * (0) per-PBM PCI configuration and status registers 299283514Sarybchik * (1) per-PBM Tomatillo controller configuration registers, but on 300283514Sarybchik * machines having the `jbusppm' device shared with its Estar 301283514Sarybchik * register bank for bus A 302283514Sarybchik * (2) per-PBM PCI configuration space 303283514Sarybchik * (3) per-PBM interrupt concentrator registers 304283514Sarybchik */ 305283514Sarybchik sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 306283514Sarybchik 20) & 1; 307283514Sarybchik for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 308283514Sarybchik i++) { 309283514Sarybchik rid = i; 310283514Sarybchik sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 311283514Sarybchik SYS_RES_MEMORY, &rid, 312283514Sarybchik (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 313283514Sarybchik i == STX_PCI) || i == STX_CTRL)) || 314283514Sarybchik (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 315283514Sarybchik i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 316283514Sarybchik if (sc->sc_mem_res[i] == NULL) 317283514Sarybchik panic("%s: could not allocate register bank %d", 318283514Sarybchik __func__, i); 319283514Sarybchik } 320283514Sarybchik 321283514Sarybchik /* 322283514Sarybchik * Match other Schizos that are already configured against 323283514Sarybchik * the controller base physical address. This will be the 324283514Sarybchik * same for a pair of devices that share register space. 325283514Sarybchik */ 326283514Sarybchik osc = NULL; 327283514Sarybchik SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 328283514Sarybchik if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 329283514Sarybchik rman_get_start(sc->sc_mem_res[STX_CTRL])) { 330283514Sarybchik /* Found partner. */ 331283514Sarybchik osc = asc; 332283514Sarybchik break; 333283514Sarybchik } 334283514Sarybchik } 335283514Sarybchik if (osc == NULL) { 336283514Sarybchik sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 337283514Sarybchik M_NOWAIT | M_ZERO); 338283514Sarybchik if (sc->sc_mtx == NULL) 339283514Sarybchik panic("%s: could not malloc mutex", __func__); 340283514Sarybchik mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 341283514Sarybchik } else { 342283514Sarybchik if (sc->sc_mode != SCHIZO_MODE_SCZ) 343283514Sarybchik panic("%s: no partner expected", __func__); 344293974Sarybchik if (mtx_initialized(osc->sc_mtx) == 0) 345293974Sarybchik panic("%s: mutex not initialized", __func__); 346293974Sarybchik sc->sc_mtx = osc->sc_mtx; 347283514Sarybchik } 348283514Sarybchik 349283514Sarybchik if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 350294007Sarybchik panic("%s: could not determine IGN", __func__); 351294007Sarybchik if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 352294007Sarybchik -1) 353283514Sarybchik panic("%s: could not determine version", __func__); 354283514Sarybchik if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 355283514Sarybchik &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 356283514Sarybchik panic("%s: could not determine module-revision", __func__); 357293974Sarybchik if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 358293974Sarybchik prop = 33000000; 359293974Sarybchik 360283514Sarybchik if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 361283514Sarybchik XMS_PCI_CTRL_X_MODE) != 0) { 362283514Sarybchik if (sc->sc_mrev < 1) 363283514Sarybchik panic("PCI-X mode unsupported"); 364283514Sarybchik sc->sc_flags |= SCHIZO_FLAGS_XMODE; 365293974Sarybchik } 366293974Sarybchik 367293974Sarybchik device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 368283514Sarybchik if (mode == SCHIZO_MODE_XMS) 369283514Sarybchik printf("module-revision %d, ", sc->sc_mrev); 370283514Sarybchik printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 371283514Sarybchik 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 372283514Sarybchik "-X" : "", prop / 1000 / 1000); 373293999Sarybchik 374283514Sarybchik /* Set up the PCI interrupt retry timer. */ 375283514Sarybchik SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 376283514Sarybchik 377283514Sarybchik /* Set up the PCI control register. */ 378293974Sarybchik reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 379293974Sarybchik reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 380293974Sarybchik STX_PCI_CTRL_ARB_MASK); 381283514Sarybchik reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 382283514Sarybchik STX_PCI_CTRL_ERR_IEN; 383283514Sarybchik if (OF_getproplen(node, "no-bus-parking") < 0) 384283514Sarybchik reg |= STX_PCI_CTRL_ARB_PARK; 385283514Sarybchik if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 386283514Sarybchik reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 387283514Sarybchik else 388283514Sarybchik reg |= STX_PCI_CTRL_ARB_MASK; 389283514Sarybchik if (mode == SCHIZO_MODE_TOM) { 390283514Sarybchik reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 391293992Sarybchik if (sc->sc_ver <= 1) /* revision <= 2.0 */ 392293992Sarybchik reg |= TOM_PCI_CTRL_DTO_IEN; 393293999Sarybchik else 394283514Sarybchik reg |= STX_PCI_CTRL_PTO; 395283514Sarybchik } else if (mode == SCHIZO_MODE_XMS) { 396283514Sarybchik SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 397283514Sarybchik SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 398293974Sarybchik reg |= XMS_PCI_CTRL_X_ERRINT_EN; 399293974Sarybchik } 400293974Sarybchik SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 401283514Sarybchik 402283514Sarybchik /* Set up the PCI diagnostic register. */ 403283514Sarybchik reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 404294386Sarybchik reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 405294386Sarybchik STX_PCI_DIAG_INTRSYNC_DIS); 406294386Sarybchik SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 407294386Sarybchik 408294386Sarybchik /* 409294386Sarybchik * Enable DMA write parity error interrupts of version >= 7 (i.e. 410294386Sarybchik * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 411294386Sarybchik * no effect though). 412294386Sarybchik */ 413294386Sarybchik if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 414294386Sarybchik mode == SCHIZO_MODE_XMS) { 415283514Sarybchik reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 416 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 417 SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 418 } 419 420 /* 421 * On Tomatillo clear the I/O prefetch lengths (workaround for a 422 * Jalapeno bug). 423 */ 424 if (mode == SCHIZO_MODE_TOM) 425 SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 426 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 427 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 428 429 /* 430 * Hunt through all the interrupt mapping regs and register 431 * the interrupt controller for our interrupt vectors. We do 432 * this early in order to be able to catch stray interrupts. 433 * This is complicated by the fact that a pair of Schizo PBMs 434 * shares one IGN. 435 */ 436 i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 437 sizeof(prop_array)); 438 if (i != -1) 439 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 440 else { 441 /* 442 * If the ino-bitmap property is missing, just provide the 443 * default set of interrupts for this controller and let 444 * schizo_setup_intr() take care of child interrupts. 445 */ 446 if (sc->sc_half == 0) 447 ino_bitmap = (1ULL << STX_UE_INO) | 448 (1ULL << STX_CE_INO) | 449 (1ULL << STX_PCIERR_A_INO) | 450 (1ULL << STX_BUS_INO); 451 else 452 ino_bitmap = 1ULL << STX_PCIERR_B_INO; 453 } 454 for (i = 0; i <= STX_MAX_INO; i++) { 455 if ((ino_bitmap & (1ULL << i)) == 0) 456 continue; 457 if (i == STX_FB0_INO || i == STX_FB1_INO) 458 /* Leave for upa(4). */ 459 continue; 460 j = schizo_intr_register(sc, i); 461 if (j != 0) 462 device_printf(dev, "could not register interrupt " 463 "controller for INO %d (%d)\n", i, j); 464 } 465 466 /* 467 * Setup Safari/JBus performance counter 0 in bus cycle counting 468 * mode as timecounter. Unfortunately, this is broken with at 469 * least the version 4 Tomatillos found in Fire V120 and Blade 470 * 1500, which apparently actually count some different event at 471 * ~0.5 and 3MHz respectively instead (also when running in full 472 * power mode). Besides, one counter seems to be shared by a 473 * "pair" of Tomatillos, too. 474 */ 475 if (sc->sc_half == 0) { 476 SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 477 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 478 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 479 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 480 if (tc == NULL) 481 panic("%s: could not malloc timecounter", __func__); 482 tc->tc_get_timecount = schizo_get_timecount; 483 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 484 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 485 sizeof(prop)) == -1) 486 panic("%s: could not determine clock frequency", 487 __func__); 488 tc->tc_frequency = prop; 489 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 490 if (mode == SCHIZO_MODE_SCZ) 491 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 492 else 493 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 494 tc->tc_priv = sc; 495 tc_init(tc); 496 } 497 498 /* 499 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 500 * one per PBM. Schizo and XMITS additionally have a streaming 501 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 502 * affected by several errata though. However, except for context 503 * flushes, taking advantage of it should be okay even with those. 504 */ 505 memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 506 sizeof(sc->sc_dma_methods)); 507 sc->sc_is.sis_sc = sc; 508 sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 509 sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 510 sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 511 if (OF_getproplen(node, "no-streaming-cache") < 0) 512 sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 513 514#define TSBCASE(x) \ 515 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 516 tsbsize = (x); \ 517 break; \ 518 519 i = OF_getprop(node, "virtual-dma", (void *)prop_array, 520 sizeof(prop_array)); 521 if (i == -1 || i != sizeof(prop_array)) 522 schizo_iommu_init(sc, 7, -1); 523 else { 524 switch (prop_array[1]) { 525 TSBCASE(1); 526 TSBCASE(2); 527 TSBCASE(3); 528 TSBCASE(4); 529 TSBCASE(5); 530 TSBCASE(6); 531 TSBCASE(7); 532 TSBCASE(8); 533 default: 534 panic("%s: unsupported DVMA size 0x%x", 535 __func__, prop_array[1]); 536 /* NOTREACHED */ 537 } 538 schizo_iommu_init(sc, tsbsize, prop_array[0]); 539 } 540 541#undef TSBCASE 542 543 /* Initialize memory and I/O rmans. */ 544 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 545 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 546 if (rman_init(&sc->sc_pci_io_rman) != 0 || 547 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 548 panic("%s: failed to set up I/O rman", __func__); 549 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 550 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 551 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 552 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 553 panic("%s: failed to set up memory rman", __func__); 554 555 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 556 /* 557 * Make sure that the expected ranges are present. The 558 * OFW_PCI_CS_MEM64 one is not currently used though. 559 */ 560 if (i != STX_NRANGE) 561 panic("%s: unsupported number of ranges", __func__); 562 /* 563 * Find the addresses of the various bus spaces. 564 * There should not be multiple ones of one kind. 565 * The physical start addresses of the ranges are the configuration, 566 * memory and I/O handles. 567 */ 568 for (i = 0; i < STX_NRANGE; i++) { 569 j = OFW_PCI_RANGE_CS(&range[i]); 570 if (sc->sc_pci_bh[j] != 0) 571 panic("%s: duplicate range for space %d", 572 __func__, j); 573 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 574 } 575 free(range, M_OFWPROP); 576 577 /* Register the softc, this is needed for paired Schizos. */ 578 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 579 580 /* Allocate our tags. */ 581 sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 582 sc->sc_mem_res[STX_PCI]), PCI_IO_BUS_SPACE, NULL); 583 if (sc->sc_pci_iot == NULL) 584 panic("%s: could not allocate PCI I/O tag", __func__); 585 sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 586 sc->sc_mem_res[STX_PCI]), PCI_CONFIG_BUS_SPACE, NULL); 587 if (sc->sc_pci_cfgt == NULL) 588 panic("%s: could not allocate PCI configuration space tag", 589 __func__); 590 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 591 sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 592 sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 593 &sc->sc_pci_dmat) != 0) 594 panic("%s: could not create PCI DMA tag", __func__); 595 /* Customize the tag. */ 596 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 597 sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods; 598 599 /* 600 * Get the bus range from the firmware. 601 * NB: Tomatillos don't support PCI bus reenumeration. 602 */ 603 i = OF_getprop(node, "bus-range", (void *)prop_array, 604 sizeof(prop_array)); 605 if (i == -1) 606 panic("%s: could not get bus-range", __func__); 607 if (i != sizeof(prop_array)) 608 panic("%s: broken bus-range (%d)", __func__, i); 609 sc->sc_pci_secbus = prop_array[0]; 610 sc->sc_pci_subbus = prop_array[1]; 611 if (bootverbose) 612 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 613 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 614 615 /* Clear any pending PCI error bits. */ 616 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 617 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 618 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 619 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 620 SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 621 622 /* 623 * Establish handlers for interesting interrupts... 624 * Someone at Sun clearly was smoking crack; with Schizos PCI 625 * bus error interrupts for one PBM can be routed to the other 626 * PBM though we obviously need to use the softc of the former 627 * as the argument for the interrupt handler and the softc of 628 * the latter as the argument for the interrupt controller. 629 */ 630 if (sc->sc_half == 0) { 631 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 632 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 633 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 634 sica_sc == osc)) 635 /* 636 * We are the driver for PBM A and either also 637 * registered the interrupt controller for us or 638 * the driver for PBM B has probed first and 639 * registered it for us. 640 */ 641 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 642 schizo_pci_bus); 643 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 644 osc != NULL) 645 /* 646 * We are the driver for PBM A but registered 647 * the interrupt controller for PBM B, i.e. the 648 * driver for PBM B attached first but couldn't 649 * set up a handler for PBM B. 650 */ 651 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 652 schizo_pci_bus); 653 } else { 654 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 655 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 656 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 657 sica_sc == osc)) 658 /* 659 * We are the driver for PBM B and either also 660 * registered the interrupt controller for us or 661 * the driver for PBM A has probed first and 662 * registered it for us. 663 */ 664 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 665 schizo_pci_bus); 666 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 667 osc != NULL) 668 /* 669 * We are the driver for PBM B but registered 670 * the interrupt controller for PBM A, i.e. the 671 * driver for PBM A attached first but couldn't 672 * set up a handler for PBM A. 673 */ 674 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 675 schizo_pci_bus); 676 } 677 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 678 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 679 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 680 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 681 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 682 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 683 684 /* 685 * According to the Schizo Errata I-13, consistent DMA flushing/ 686 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 687 * so we can't use it and need to live with the consequences. With 688 * Schizo version >= 5, CDMA flushing/syncing is usable but requires 689 * the workaround described in Schizo Errata I-23. With Tomatillo 690 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 691 * version <= 4 (i.e. revision <= 2.3) bridges additionally require 692 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 693 */ 694 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 695 sc->sc_mode == SCHIZO_MODE_TOM || 696 sc->sc_mode == SCHIZO_MODE_XMS) { 697 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 698 sc->sc_dma_methods.dm_dmamap_sync = 699 schizo_dmamap_sync; 700 sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 701 /* 702 * Some firmware versions include the CDMA interrupt 703 * at RID 4 but most don't. With the latter we add 704 * it ourselves at the spare RID 5. 705 */ 706 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 707 4)); 708 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 709 (void)schizo_get_intrmap(sc, i, NULL, 710 &sc->sc_cdma_clr); 711 schizo_set_intr(sc, 4, i, schizo_cdma); 712 } else { 713 i = STX_CDMA_A_INO + sc->sc_half; 714 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 715 INTMAP_VEC(sc->sc_ign, i), 1) != 0) 716 panic("%s: failed to add CDMA " 717 "interrupt", __func__); 718 j = schizo_intr_register(sc, i); 719 if (j != 0) 720 panic("%s: could not register " 721 "interrupt controller for CDMA " 722 "(%d)", __func__, j); 723 (void)schizo_get_intrmap(sc, i, NULL, 724 &sc->sc_cdma_clr); 725 schizo_set_intr(sc, 5, i, schizo_cdma); 726 } 727 } else { 728 if (sc->sc_mode == SCHIZO_MODE_XMS) 729 mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 730 NULL, MTX_SPIN); 731 sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 732 sc->sc_half); 733 sc->sc_dma_methods.dm_dmamap_sync = 734 ichip_dmamap_sync; 735 } 736 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 737 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 738 } 739 740 /* 741 * Set the latency timer register as this isn't always done by the 742 * firmware. 743 */ 744 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 745 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 746 747 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 748 749#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 750 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 751 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 752 (name), CTLFLAG_RD, (arg), 0, (desc)) 753 754 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 755 "DMA correctable errors"); 756 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 757 "PCI bus non-fatal errors"); 758 759#undef SCHIZO_SYSCTL_ADD_UINT 760 761 device_add_child(dev, "pci", -1); 762 return (bus_generic_attach(dev)); 763} 764 765static void 766schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 767 driver_filter_t handler) 768{ 769 u_long vec; 770 int rid; 771 772 rid = index; 773 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 774 SYS_RES_IRQ, &rid, RF_ACTIVE); 775 if (sc->sc_irq_res[index] == NULL || 776 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 777 INTIGN(vec) != sc->sc_ign || 778 intr_vectors[vec].iv_ic != &schizo_ic || 779 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 780 INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 781 &sc->sc_ihand[index]) != 0) 782 panic("%s: failed to set up interrupt %d", __func__, index); 783} 784 785static int 786schizo_intr_register(struct schizo_softc *sc, u_int ino) 787{ 788 struct schizo_icarg *sica; 789 bus_addr_t intrclr, intrmap; 790 int error; 791 792 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 793 return (ENXIO); 794 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 795 if (sica == NULL) 796 return (ENOMEM); 797 sica->sica_sc = sc; 798 sica->sica_map = intrmap; 799 sica->sica_clr = intrclr; 800#ifdef SCHIZO_DEBUG 801 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 802 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 803 (u_long)intrclr); 804#endif 805 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 806 &schizo_ic, sica)); 807 if (error != 0) 808 free(sica, M_DEVBUF); 809 return (error); 810} 811 812static int 813schizo_get_intrmap(struct schizo_softc *sc, u_int ino, 814 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 815{ 816 bus_addr_t intrclr, intrmap; 817 uint64_t mr; 818 819 /* 820 * XXX we only look for INOs rather than INRs since the firmware 821 * may not provide the IGN and the IGN is constant for all devices 822 * on that PCI controller. 823 */ 824 825 if (ino > STX_MAX_INO) { 826 device_printf(sc->sc_dev, "out of range INO %d requested\n", 827 ino); 828 return (0); 829 } 830 831 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 832 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 833 mr = SCHIZO_PCI_READ_8(sc, intrmap); 834 if (INTINO(mr) != ino) { 835 device_printf(sc->sc_dev, 836 "interrupt map entry does not match INO (%d != %d)\n", 837 (int)INTINO(mr), ino); 838 return (0); 839 } 840 841 if (intrmapptr != NULL) 842 *intrmapptr = intrmap; 843 if (intrclrptr != NULL) 844 *intrclrptr = intrclr; 845 return (1); 846} 847 848/* 849 * Interrupt handlers 850 */ 851static int 852schizo_pci_bus(void *arg) 853{ 854 struct schizo_softc *sc = arg; 855 uint64_t afar, afsr, csr, iommu, xstat; 856 uint32_t status; 857 u_int fatal; 858 859 fatal = 0; 860 861 mtx_lock_spin(sc->sc_mtx); 862 863 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 864 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 865 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 866 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 867 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 868 xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 869 else 870 xstat = 0; 871 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 872 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 873 874 /* 875 * IOMMU errors are only fatal on Tomatillo and there also only if 876 * target abort was not signaled. 877 */ 878 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 879 (iommu & TOM_PCI_IOMMU_ERR) != 0 && 880 ((status & PCIM_STATUS_STABORT) == 0 || 881 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 882 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 883 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 884 fatal = 1; 885 else if ((status & PCIM_STATUS_STABORT) != 0) 886 fatal = 1; 887 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 888 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 889 PCIM_STATUS_MDPERR)) != 0 || 890 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 891 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 892 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 893 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 894 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 895 STX_PCI_AFSR_P_UNUS)) != 0) 896 fatal = 1; 897 if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 898 XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 899 XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 900 XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 901 fatal = 1; 902 if (fatal == 0) 903 sc->sc_stats_pci_non_fatal++; 904 905 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 906 "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 907 'A' + sc->sc_half, (unsigned long long)afar, 908 (unsigned long long)afsr, (unsigned long long)csr, 909 (unsigned long long)iommu, (unsigned long long)xstat, status); 910 911 /* Clear the error bits that we caught. */ 912 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 913 STX_CS_FUNC, PCIR_STATUS, status, 2); 914 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 915 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 916 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 917 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 918 SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 919 920 mtx_unlock_spin(sc->sc_mtx); 921 922 if (fatal != 0) 923 panic("%s: fatal PCI bus error", 924 device_get_nameunit(sc->sc_dev)); 925 return (FILTER_HANDLED); 926} 927 928static int 929schizo_ue(void *arg) 930{ 931 struct schizo_softc *sc = arg; 932 uint64_t afar, afsr; 933 int i; 934 935 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 936 for (i = 0; i < 1000; i++) 937 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 938 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 939 break; 940 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 941 device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 942 (unsigned long long)afsr); 943 return (FILTER_HANDLED); 944} 945 946static int 947schizo_ce(void *arg) 948{ 949 struct schizo_softc *sc = arg; 950 uint64_t afar, afsr; 951 int i; 952 953 mtx_lock_spin(sc->sc_mtx); 954 955 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 956 for (i = 0; i < 1000; i++) 957 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 958 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 959 break; 960 sc->sc_stats_dma_ce++; 961 device_printf(sc->sc_dev, 962 "correctable DMA error AFAR %#llx AFSR %#llx\n", 963 (unsigned long long)afar, (unsigned long long)afsr); 964 965 /* Clear the error bits that we caught. */ 966 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 967 968 mtx_unlock_spin(sc->sc_mtx); 969 970 return (FILTER_HANDLED); 971} 972 973static int 974schizo_host_bus(void *arg) 975{ 976 struct schizo_softc *sc = arg; 977 uint64_t errlog; 978 979 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 980 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 981 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 982 (unsigned long long)errlog); 983 return (FILTER_HANDLED); 984} 985 986static int 987schizo_cdma(void *arg) 988{ 989 struct schizo_softc *sc = arg; 990 991 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_RECEIVED); 992 return (FILTER_HANDLED); 993} 994 995static void 996schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 997{ 998 999 /* Punch in our copies. */ 1000 sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1001 sc->sc_is.sis_is.is_bushandle = 1002 rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 1003 sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 1004 sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 1005 sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 1006 sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 1007 sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 1008 sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 1009 1010 iommu_init(device_get_nameunit(sc->sc_dev), 1011 (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 1012} 1013 1014static int 1015schizo_maxslots(device_t dev) 1016{ 1017 struct schizo_softc *sc; 1018 1019 sc = device_get_softc(dev); 1020 if (sc->sc_mode == SCHIZO_MODE_SCZ) 1021 return (sc->sc_half == 0 ? 4 : 6); 1022 1023 /* XXX: is this correct? */ 1024 return (PCI_SLOTMAX); 1025} 1026 1027static uint32_t 1028schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 1029 int width) 1030{ 1031 struct schizo_softc *sc; 1032 bus_space_handle_t bh; 1033 u_long offset = 0; 1034 uint32_t r, wrd; 1035 int i; 1036 uint16_t shrt; 1037 uint8_t byte; 1038 1039 sc = device_get_softc(dev); 1040 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1041 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1042 return (-1); 1043 1044 /* 1045 * The Schizo bridges contain a dupe of their header at 0x80. 1046 */ 1047 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1048 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1049 reg + width > 0x80) 1050 return (0); 1051 1052 offset = STX_CONF_OFF(bus, slot, func, reg); 1053 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1054 switch (width) { 1055 case 1: 1056 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1057 r = byte; 1058 break; 1059 case 2: 1060 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1061 r = shrt; 1062 break; 1063 case 4: 1064 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1065 r = wrd; 1066 break; 1067 default: 1068 panic("%s: bad width", __func__); 1069 /* NOTREACHED */ 1070 } 1071 1072 if (i) { 1073#ifdef SCHIZO_DEBUG 1074 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1075 __func__, bus, slot, func, reg); 1076#endif 1077 r = -1; 1078 } 1079 return (r); 1080} 1081 1082static void 1083schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1084 u_int reg, uint32_t val, int width) 1085{ 1086 struct schizo_softc *sc; 1087 bus_space_handle_t bh; 1088 u_long offset = 0; 1089 1090 sc = device_get_softc(dev); 1091 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1092 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1093 return; 1094 1095 offset = STX_CONF_OFF(bus, slot, func, reg); 1096 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1097 switch (width) { 1098 case 1: 1099 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1100 break; 1101 case 2: 1102 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1103 break; 1104 case 4: 1105 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1106 break; 1107 default: 1108 panic("%s: bad width", __func__); 1109 /* NOTREACHED */ 1110 } 1111} 1112 1113static int 1114schizo_route_interrupt(device_t bridge, device_t dev, int pin) 1115{ 1116 struct schizo_softc *sc; 1117 struct ofw_pci_register reg; 1118 ofw_pci_intr_t pintr, mintr; 1119 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1120 1121 sc = device_get_softc(bridge); 1122 pintr = pin; 1123 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1124 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1125 NULL, maskbuf)) 1126 return (mintr); 1127 1128 device_printf(bridge, "could not route pin %d for device %d.%d\n", 1129 pin, pci_get_slot(dev), pci_get_function(dev)); 1130 return (PCI_INVALID_IRQ); 1131} 1132 1133static int 1134schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1135{ 1136 struct schizo_softc *sc; 1137 1138 sc = device_get_softc(dev); 1139 switch (which) { 1140 case PCIB_IVAR_DOMAIN: 1141 *result = device_get_unit(dev); 1142 return (0); 1143 case PCIB_IVAR_BUS: 1144 *result = sc->sc_pci_secbus; 1145 return (0); 1146 } 1147 return (ENOENT); 1148} 1149 1150static void 1151schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1152{ 1153 struct timeval cur, end; 1154 struct schizo_iommu_state *sis = dt->dt_cookie; 1155 struct schizo_softc *sc = sis->sis_sc; 1156 int res; 1157 1158 if ((map->dm_flags & DMF_STREAMED) != 0) { 1159 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1160 return; 1161 } 1162 1163 if ((map->dm_flags & DMF_LOADED) == 0) 1164 return; 1165 1166 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1167 /* 1168 * Note that in order to allow this function to be called from 1169 * filters we would need to use a spin mutex for serialization 1170 * but given that these disable interrupts we have to emulate 1171 * one. 1172 */ 1173 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1174 SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1175 ; 1176 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1177 microuptime(&cur); 1178 end.tv_sec = 1; 1179 end.tv_usec = 0; 1180 timevaladd(&end, &cur); 1181 for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1182 SCHIZO_CDMA_STATE_RECEIVED, SCHIZO_CDMA_STATE_IDLE)) == 1183 0 && timevalcmp(&cur, &end, <=);) 1184 microuptime(&cur); 1185 if (res == 0) 1186 panic("%s: DMA does not sync", __func__); 1187 } 1188 1189 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1190 membar(Sync); 1191} 1192 1193#define VIS_BLOCKSIZE 64 1194 1195static void 1196ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1197{ 1198 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1199 struct timeval cur, end; 1200 struct schizo_iommu_state *sis = dt->dt_cookie; 1201 struct schizo_softc *sc = sis->sis_sc; 1202 register_t reg, s; 1203 1204 if ((map->dm_flags & DMF_STREAMED) != 0) { 1205 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1206 return; 1207 } 1208 1209 if ((map->dm_flags & DMF_LOADED) == 0) 1210 return; 1211 1212 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1213 if (sc->sc_mode == SCHIZO_MODE_XMS) 1214 mtx_lock_spin(&sc->sc_sync_mtx); 1215 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1216 sc->sc_sync_val); 1217 microuptime(&cur); 1218 end.tv_sec = 1; 1219 end.tv_usec = 0; 1220 timevaladd(&end, &cur); 1221 for (; ((reg = SCHIZO_PCI_READ_8(sc, 1222 TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1223 timevalcmp(&cur, &end, <=);) 1224 microuptime(&cur); 1225 if ((reg & sc->sc_sync_val) != 0) 1226 panic("%s: DMA does not sync", __func__); 1227 if (sc->sc_mode == SCHIZO_MODE_XMS) 1228 mtx_unlock_spin(&sc->sc_sync_mtx); 1229 else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1230 s = intr_disable(); 1231 reg = rd(fprs); 1232 wr(fprs, reg | FPRS_FEF, 0); 1233 __asm __volatile("stda %%f0, [%0] %1" 1234 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1235 membar(Sync); 1236 wr(fprs, reg, 0); 1237 intr_restore(s); 1238 return; 1239 } 1240 } 1241 1242 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1243 membar(Sync); 1244} 1245 1246static void 1247schizo_intr_enable(void *arg) 1248{ 1249 struct intr_vector *iv = arg; 1250 struct schizo_icarg *sica = iv->iv_icarg; 1251 1252 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1253 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1254} 1255 1256static void 1257schizo_intr_disable(void *arg) 1258{ 1259 struct intr_vector *iv = arg; 1260 struct schizo_icarg *sica = iv->iv_icarg; 1261 1262 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1263} 1264 1265static void 1266schizo_intr_assign(void *arg) 1267{ 1268 struct intr_vector *iv = arg; 1269 struct schizo_icarg *sica = iv->iv_icarg; 1270 1271 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1272 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1273} 1274 1275static void 1276schizo_intr_clear(void *arg) 1277{ 1278 struct intr_vector *iv = arg; 1279 struct schizo_icarg *sica = iv->iv_icarg; 1280 1281 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1282} 1283 1284static int 1285schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1286 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1287 void **cookiep) 1288{ 1289 struct schizo_softc *sc; 1290 u_long vec; 1291 int error; 1292 1293 sc = device_get_softc(dev); 1294 /* 1295 * Make sure the vector is fully specified. 1296 */ 1297 vec = rman_get_start(ires); 1298 if (INTIGN(vec) != sc->sc_ign) { 1299 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1300 return (EINVAL); 1301 } 1302 1303 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1304 /* 1305 * Ensure we use the right softc in case the interrupt 1306 * is routed to our companion PBM for some odd reason. 1307 */ 1308 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1309 sica_sc; 1310 } else if (intr_vectors[vec].iv_ic == NULL) { 1311 /* 1312 * Work around broken firmware which misses entries in 1313 * the ino-bitmap. 1314 */ 1315 error = schizo_intr_register(sc, INTINO(vec)); 1316 if (error != 0) { 1317 device_printf(dev, "could not register interrupt " 1318 "controller for vector 0x%lx (%d)\n", vec, error); 1319 return (error); 1320 } 1321 if (bootverbose) 1322 device_printf(dev, "belatedly registered as " 1323 "interrupt controller for vector 0x%lx\n", vec); 1324 } else { 1325 device_printf(dev, 1326 "invalid interrupt controller for vector 0x%lx\n", vec); 1327 return (EINVAL); 1328 } 1329 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1330 arg, cookiep)); 1331} 1332 1333static struct resource * 1334schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1335 u_long start, u_long end, u_long count, u_int flags) 1336{ 1337 struct schizo_softc *sc; 1338 struct resource *rv; 1339 struct rman *rm; 1340 1341 sc = device_get_softc(bus); 1342 switch (type) { 1343 case SYS_RES_IRQ: 1344 /* 1345 * XXX: Don't accept blank ranges for now, only single 1346 * interrupts. The other case should not happen with 1347 * the MI PCI code... 1348 * XXX: This may return a resource that is out of the 1349 * range that was specified. Is this correct...? 1350 */ 1351 if (start != end) 1352 panic("%s: XXX: interrupt range", __func__); 1353 start = end = INTMAP_VEC(sc->sc_ign, end); 1354 return (bus_generic_alloc_resource(bus, child, type, rid, 1355 start, end, count, flags)); 1356 case SYS_RES_MEMORY: 1357 rm = &sc->sc_pci_mem_rman; 1358 break; 1359 case SYS_RES_IOPORT: 1360 rm = &sc->sc_pci_io_rman; 1361 break; 1362 default: 1363 return (NULL); 1364 } 1365 1366 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 1367 child); 1368 if (rv == NULL) 1369 return (NULL); 1370 rman_set_rid(rv, *rid); 1371 1372 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type, 1373 *rid, rv) != 0) { 1374 rman_release_resource(rv); 1375 return (NULL); 1376 } 1377 return (rv); 1378} 1379 1380static int 1381schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1382 struct resource *r) 1383{ 1384 struct schizo_softc *sc; 1385 struct bus_space_tag *tag; 1386 1387 sc = device_get_softc(bus); 1388 switch (type) { 1389 case SYS_RES_IRQ: 1390 return (bus_generic_activate_resource(bus, child, type, rid, 1391 r)); 1392 case SYS_RES_MEMORY: 1393 tag = sparc64_alloc_bus_tag(r, rman_get_bustag( 1394 sc->sc_mem_res[STX_PCI]), PCI_MEMORY_BUS_SPACE, NULL); 1395 if (tag == NULL) 1396 return (ENOMEM); 1397 rman_set_bustag(r, tag); 1398 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] + 1399 rman_get_start(r)); 1400 break; 1401 case SYS_RES_IOPORT: 1402 rman_set_bustag(r, sc->sc_pci_iot); 1403 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] + 1404 rman_get_start(r)); 1405 break; 1406 } 1407 return (rman_activate_resource(r)); 1408} 1409 1410static int 1411schizo_adjust_resource(device_t bus, device_t child, int type, 1412 struct resource *r, u_long start, u_long end) 1413{ 1414 struct schizo_softc *sc; 1415 struct rman *rm; 1416 1417 sc = device_get_softc(bus); 1418 switch (type) { 1419 case SYS_RES_IRQ: 1420 return (bus_generic_adjust_resource(bus, child, type, r, 1421 start, end)); 1422 case SYS_RES_MEMORY: 1423 rm = &sc->sc_pci_mem_rman; 1424 break; 1425 case SYS_RES_IOPORT: 1426 rm = &sc->sc_pci_io_rman; 1427 break; 1428 default: 1429 return (EINVAL); 1430 } 1431 if (rman_is_region_manager(r, rm) == 0) 1432 return (EINVAL); 1433 return (rman_adjust_resource(r, start, end)); 1434} 1435 1436static bus_dma_tag_t 1437schizo_get_dma_tag(device_t bus, device_t child __unused) 1438{ 1439 struct schizo_softc *sc; 1440 1441 sc = device_get_softc(bus); 1442 return (sc->sc_pci_dmat); 1443} 1444 1445static phandle_t 1446schizo_get_node(device_t bus, device_t child __unused) 1447{ 1448 struct schizo_softc *sc; 1449 1450 sc = device_get_softc(bus); 1451 /* We only have one child, the PCI bus, which needs our own node. */ 1452 return (sc->sc_node); 1453} 1454 1455static void 1456schizo_setup_device(device_t bus, device_t child) 1457{ 1458 struct schizo_softc *sc; 1459 uint64_t reg; 1460 int capreg; 1461 1462 sc = device_get_softc(bus); 1463 /* 1464 * Disable bus parking in order to work around a bus hang caused by 1465 * Casinni/Skyhawk combinations. 1466 */ 1467 if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1468 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1469 STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1470 1471 if (sc->sc_mode == SCHIZO_MODE_XMS) { 1472 /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1473 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1474 (pci_read_config(child, PCIR_HDRTYPE, 1) & 1475 PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1476 pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1477 pci_write_config(child, capreg + PCIXR_COMMAND, 1478 pci_read_config(child, capreg + PCIXR_COMMAND, 1479 2) & 0x7c, 2); 1480 /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1481 if (sc->sc_mrev >= 4) { 1482 reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1483 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1484 if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1485 XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1486 SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1487 } 1488 } 1489} 1490 1491static u_int 1492schizo_get_timecount(struct timecounter *tc) 1493{ 1494 struct schizo_softc *sc; 1495 1496 sc = tc->tc_priv; 1497 return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1498 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >> 1499 STX_CTRL_PERF_CNT_CNT0_SHIFT); 1500} 1501