schizo.c revision 190108
1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4183423Smarius * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 190108 2009-03-19 20:48:47Z marius $"); 36183423Smarius 37183423Smarius/* 38183423Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39183423Smarius * PCI 2.2 bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55185133Smarius#include <sys/time.h> 56183423Smarius#include <sys/timetc.h> 57183423Smarius 58183423Smarius#include <dev/ofw/ofw_bus.h> 59183423Smarius#include <dev/ofw/ofw_pci.h> 60183423Smarius#include <dev/ofw/openfirm.h> 61183423Smarius 62183423Smarius#include <machine/bus.h> 63183423Smarius#include <machine/bus_common.h> 64183423Smarius#include <machine/bus_private.h> 65183423Smarius#include <machine/fsr.h> 66183423Smarius#include <machine/iommureg.h> 67183423Smarius#include <machine/iommuvar.h> 68183423Smarius#include <machine/resource.h> 69183423Smarius 70183423Smarius#include <dev/pci/pcireg.h> 71183423Smarius#include <dev/pci/pcivar.h> 72183423Smarius 73183423Smarius#include <sparc64/pci/ofw_pci.h> 74183423Smarius#include <sparc64/pci/schizoreg.h> 75183423Smarius#include <sparc64/pci/schizovar.h> 76183423Smarius 77183423Smarius#include "pcib_if.h" 78183423Smarius 79183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 80183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 81183423Smarius driver_filter_t); 82185133Smariusstatic driver_filter_t schizo_dma_sync_stub; 83185133Smariusstatic driver_filter_t ichip_dma_sync_stub; 84183423Smariusstatic void schizo_intr_enable(void *); 85183423Smariusstatic void schizo_intr_disable(void *); 86183423Smariusstatic void schizo_intr_assign(void *); 87183423Smariusstatic void schizo_intr_clear(void *); 88185133Smariusstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 89183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 90183423Smarius bus_addr_t *, bus_addr_t *); 91183423Smariusstatic bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 92183423Smariusstatic timecounter_get_t schizo_get_timecount; 93183423Smarius 94183423Smarius/* Interrupt handlers */ 95183423Smariusstatic driver_filter_t schizo_pci_bus; 96183423Smariusstatic driver_filter_t schizo_ue; 97183423Smariusstatic driver_filter_t schizo_ce; 98183423Smariusstatic driver_filter_t schizo_host_bus; 99185133Smariusstatic driver_filter_t schizo_cdma; 100183423Smarius 101183423Smarius/* IOMMU support */ 102183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 103183423Smarius 104183423Smarius/* 105183423Smarius * Methods 106183423Smarius */ 107183423Smariusstatic device_probe_t schizo_probe; 108183423Smariusstatic device_attach_t schizo_attach; 109183423Smariusstatic bus_read_ivar_t schizo_read_ivar; 110183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 111183423Smariusstatic bus_teardown_intr_t schizo_teardown_intr; 112183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 113183423Smariusstatic bus_activate_resource_t schizo_activate_resource; 114183423Smariusstatic bus_deactivate_resource_t schizo_deactivate_resource; 115183423Smariusstatic bus_release_resource_t schizo_release_resource; 116183423Smariusstatic bus_get_dma_tag_t schizo_get_dma_tag; 117183423Smariusstatic pcib_maxslots_t schizo_maxslots; 118183423Smariusstatic pcib_read_config_t schizo_read_config; 119183423Smariusstatic pcib_write_config_t schizo_write_config; 120183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 121183423Smariusstatic ofw_bus_get_node_t schizo_get_node; 122183423Smarius 123183423Smariusstatic device_method_t schizo_methods[] = { 124183423Smarius /* Device interface */ 125183423Smarius DEVMETHOD(device_probe, schizo_probe), 126183423Smarius DEVMETHOD(device_attach, schizo_attach), 127183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 128183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 129183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 130183423Smarius 131183423Smarius /* Bus interface */ 132183423Smarius DEVMETHOD(bus_print_child, bus_generic_print_child), 133183423Smarius DEVMETHOD(bus_read_ivar, schizo_read_ivar), 134183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 135183423Smarius DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 136183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 137183423Smarius DEVMETHOD(bus_activate_resource, schizo_activate_resource), 138183423Smarius DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 139183423Smarius DEVMETHOD(bus_release_resource, schizo_release_resource), 140183423Smarius DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 141183423Smarius 142183423Smarius /* pcib interface */ 143183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 144183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 145183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 146183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 147183423Smarius 148183423Smarius /* ofw_bus interface */ 149183423Smarius DEVMETHOD(ofw_bus_get_node, schizo_get_node), 150183423Smarius 151190108Smarius KOBJMETHOD_END 152183423Smarius}; 153183423Smarius 154183423Smariusstatic devclass_t schizo_devclass; 155183423Smarius 156183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 157183423Smarius sizeof(struct schizo_softc)); 158183423SmariusDRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 159183423Smarius 160183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 161183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 162183423Smarius 163183423Smariusstatic const struct intr_controller schizo_ic = { 164183423Smarius schizo_intr_enable, 165183423Smarius schizo_intr_disable, 166183423Smarius schizo_intr_assign, 167183423Smarius schizo_intr_clear 168183423Smarius}; 169183423Smarius 170183423Smariusstruct schizo_icarg { 171183423Smarius struct schizo_softc *sica_sc; 172183423Smarius bus_addr_t sica_map; 173183423Smarius bus_addr_t sica_clr; 174183423Smarius}; 175183423Smarius 176185133Smariusstruct schizo_dma_sync { 177183423Smarius struct schizo_softc *sds_sc; 178183423Smarius driver_filter_t *sds_handler; 179183423Smarius void *sds_arg; 180183423Smarius void *sds_cookie; 181183423Smarius uint64_t sds_syncval; 182185133Smarius device_t sds_ppb; /* farest PCI-PCI bridge */ 183185133Smarius uint8_t sds_bus; /* bus of farest PCI device */ 184185133Smarius uint8_t sds_slot; /* slot of farest PCI device */ 185185133Smarius uint8_t sds_func; /* func. of farest PCI device */ 186183423Smarius}; 187183423Smarius 188183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 189183423Smarius 190183423Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 191183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 192183423Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 193183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 194183423Smarius 195183423Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 196183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 197183423Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 198183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 199183423Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 200183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 201183423Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 202183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 203183423Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 204183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 205183423Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 206183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 207183423Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 208183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 209183423Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 210183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 211183423Smarius 212183423Smarius#define OFW_PCI_TYPE "pci" 213183423Smarius 214183423Smariusstruct schizo_desc { 215183423Smarius const char *sd_string; 216183423Smarius int sd_mode; 217183423Smarius const char *sd_name; 218183423Smarius}; 219183423Smarius 220185133Smariusstatic const struct schizo_desc const schizo_compats[] = { 221183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 222183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 223183423Smarius { NULL, 0, NULL } 224183423Smarius}; 225183423Smarius 226183423Smariusstatic const struct schizo_desc * 227183423Smariusschizo_get_desc(device_t dev) 228183423Smarius{ 229183423Smarius const struct schizo_desc *desc; 230183423Smarius const char *compat; 231183423Smarius 232183423Smarius compat = ofw_bus_get_compat(dev); 233183423Smarius if (compat == NULL) 234183423Smarius return (NULL); 235183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 236183423Smarius if (strcmp(desc->sd_string, compat) == 0) 237183423Smarius return (desc); 238183423Smarius return (NULL); 239183423Smarius} 240183423Smarius 241183423Smariusstatic int 242183423Smariusschizo_probe(device_t dev) 243183423Smarius{ 244183423Smarius const char *dtype; 245183423Smarius 246183423Smarius dtype = ofw_bus_get_type(dev); 247183423Smarius if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 248183423Smarius schizo_get_desc(dev) != NULL) { 249183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 250183423Smarius return (0); 251183423Smarius } 252183423Smarius return (ENXIO); 253183423Smarius} 254183423Smarius 255183423Smariusstatic int 256183423Smariusschizo_attach(device_t dev) 257183423Smarius{ 258183423Smarius struct ofw_pci_ranges *range; 259183423Smarius const struct schizo_desc *desc; 260183423Smarius struct schizo_softc *asc, *sc, *osc; 261183423Smarius struct timecounter *tc; 262183423Smarius uint64_t ino_bitmap, reg; 263183423Smarius phandle_t node; 264183423Smarius uint32_t prop, prop_array[2]; 265183423Smarius int i, mode, n, nrange, rid, tsbsize; 266183423Smarius 267183423Smarius sc = device_get_softc(dev); 268183423Smarius node = ofw_bus_get_node(dev); 269183423Smarius desc = schizo_get_desc(dev); 270183423Smarius mode = desc->sd_mode; 271183423Smarius 272183423Smarius sc->sc_dev = dev; 273183423Smarius sc->sc_node = node; 274183423Smarius sc->sc_mode = mode; 275185133Smarius sc->sc_flags = 0; 276183423Smarius 277183423Smarius /* 278183423Smarius * The Schizo has three register banks: 279183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 280183423Smarius * shared with the UPA64s interrupt mapping register banks 281183423Smarius * (1) shared Schizo controller configuration and status registers 282183423Smarius * (2) per-PBM PCI configuration space 283183423Smarius * 284183423Smarius * The Tomatillo has four register banks: 285183423Smarius * (0) per-PBM PCI configuration and status registers 286183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 287183423Smarius * machines having the `jbusppm' device shared with its Estar 288183423Smarius * register bank for bus A 289183423Smarius * (2) per-PBM PCI configuration space 290183423Smarius * (3) per-PBM interrupt concentrator registers 291183423Smarius */ 292183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 293183423Smarius 20) & 1; 294183423Smarius for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 295183423Smarius n++) { 296183423Smarius rid = n; 297183423Smarius sc->sc_mem_res[n] = bus_alloc_resource_any(dev, 298183423Smarius SYS_RES_MEMORY, &rid, 299183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 300183423Smarius n == STX_PCI) || n == STX_CTRL)) || 301183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 302183423Smarius n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 303183423Smarius if (sc->sc_mem_res[n] == NULL) 304183423Smarius panic("%s: could not allocate register bank %d", 305183423Smarius __func__, n); 306183423Smarius } 307183423Smarius 308183423Smarius /* 309183423Smarius * Match other Schizos that are already configured against 310183423Smarius * the controller base physical address. This will be the 311183423Smarius * same for a pair of devices that share register space. 312183423Smarius */ 313183423Smarius osc = NULL; 314183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 315183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 316183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 317183423Smarius /* Found partner. */ 318183423Smarius osc = asc; 319183423Smarius break; 320183423Smarius } 321183423Smarius } 322183423Smarius if (osc == NULL) { 323183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 324183423Smarius M_NOWAIT | M_ZERO); 325183423Smarius if (sc->sc_mtx == NULL) 326183423Smarius panic("%s: could not malloc mutex", __func__); 327183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 328183423Smarius } else { 329185133Smarius if (sc->sc_mode != SCHIZO_MODE_SCZ) 330185133Smarius panic("%s: no partner expected", __func__); 331183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 332183423Smarius panic("%s: mutex not initialized", __func__); 333183423Smarius sc->sc_mtx = osc->sc_mtx; 334183423Smarius } 335183423Smarius 336183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 337183423Smarius panic("%s: could not determine IGN", __func__); 338183423Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1) 339183423Smarius panic("%s: could not determine version", __func__); 340183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 341183423Smarius prop = 33000000; 342183423Smarius 343183423Smarius device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 344183423Smarius desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 345183423Smarius prop / 1000 / 1000); 346183423Smarius 347183423Smarius /* Set up the PCI interrupt retry timer. */ 348183423Smarius#ifdef SCHIZO_DEBUG 349183423Smarius device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 350183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 351183423Smarius#endif 352183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 353183423Smarius 354183423Smarius /* Set up the PCI control register. */ 355183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 356183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 357183423Smarius STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 358183423Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 359183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 360183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 361183423Smarius if (mode == SCHIZO_MODE_TOM) { 362183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 363183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 364183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 365183423Smarius else 366183423Smarius reg |= STX_PCI_CTRL_PTO; 367183423Smarius } 368183423Smarius#ifdef SCHIZO_DEBUG 369183423Smarius device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 370183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 371183423Smarius (unsigned long long)reg); 372183423Smarius#endif 373183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 374183423Smarius 375183423Smarius /* Set up the PCI diagnostic register. */ 376183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 377183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 378183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 379183423Smarius#ifdef SCHIZO_DEBUG 380183423Smarius device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 381183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 382183423Smarius (unsigned long long)reg); 383183423Smarius#endif 384183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 385183423Smarius 386183423Smarius /* 387183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 388183423Smarius * Jalapeno bug). 389183423Smarius */ 390183423Smarius if (mode == SCHIZO_MODE_TOM) 391183423Smarius SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 392183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 393183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 394183423Smarius 395183423Smarius /* 396183423Smarius * Hunt through all the interrupt mapping regs and register 397186290Smarius * the interrupt controller for our interrupt vectors. We do 398186290Smarius * this early in order to be able to catch stray interrupts. 399186290Smarius * This is complicated by the fact that a pair of Schizo PBMs 400186290Smarius * shares one IGN. 401183423Smarius */ 402183423Smarius n = OF_getprop(node, "ino-bitmap", (void *)prop_array, 403183423Smarius sizeof(prop_array)); 404183423Smarius if (n == -1) 405183423Smarius panic("%s: could not get ino-bitmap", __func__); 406183423Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 407183423Smarius for (n = 0; n <= STX_MAX_INO; n++) { 408183423Smarius if ((ino_bitmap & (1ULL << n)) == 0) 409183423Smarius continue; 410183423Smarius if (n == STX_FB0_INO || n == STX_FB1_INO) 411183423Smarius /* Leave for upa(4). */ 412183423Smarius continue; 413185133Smarius i = schizo_intr_register(sc, n); 414185133Smarius if (i != 0) 415186290Smarius device_printf(dev, "could not register interrupt " 416186290Smarius "controller for INO %d (%d)\n", n, i); 417183423Smarius } 418183423Smarius 419183423Smarius /* 420183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 421183423Smarius * mode as timecounter. Unfortunately, this is broken with at 422183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 423183423Smarius * 1500, which apparently actually count some different event at 424183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 425183423Smarius * power mode). Besides, one counter seems to be shared by a 426183423Smarius * "pair" of Tomatillos, too. 427183423Smarius */ 428183423Smarius if (sc->sc_half == 0) { 429183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 430183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 431183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 432183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 433183423Smarius if (tc == NULL) 434183423Smarius panic("%s: could not malloc timecounter", __func__); 435183423Smarius tc->tc_get_timecount = schizo_get_timecount; 436183423Smarius tc->tc_poll_pps = NULL; 437183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 438183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 439183423Smarius sizeof(prop)) == -1) 440183423Smarius panic("%s: could not determine clock frequency", 441183423Smarius __func__); 442183423Smarius tc->tc_frequency = prop; 443183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 444183423Smarius if (mode == SCHIZO_MODE_SCZ) 445183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 446183423Smarius else 447183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 448183423Smarius tc->tc_priv = sc; 449183423Smarius tc_init(tc); 450183423Smarius } 451183423Smarius 452190108Smarius /* 453190108Smarius * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 454190108Smarius * one per PBM. Schizo and XMITS additionally have a streaming 455190108Smarius * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 456190108Smarius * affected by several errata and basically unusable though. 457190108Smarius */ 458183423Smarius sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 459190108Smarius sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0; 460190108Smarius if (OF_getproplen(node, "no-streaming-cache") < 0 && 461190108Smarius !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 462183423Smarius sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 463183423Smarius 464183423Smarius#define TSBCASE(x) \ 465183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 466183423Smarius tsbsize = (x); \ 467183423Smarius break; \ 468183423Smarius 469183423Smarius n = OF_getprop(node, "virtual-dma", (void *)prop_array, 470183423Smarius sizeof(prop_array)); 471183423Smarius if (n == -1 || n != sizeof(prop_array)) 472183423Smarius schizo_iommu_init(sc, 7, -1); 473183423Smarius else { 474183423Smarius switch (prop_array[1]) { 475183423Smarius TSBCASE(1); 476183423Smarius TSBCASE(2); 477183423Smarius TSBCASE(3); 478183423Smarius TSBCASE(4); 479183423Smarius TSBCASE(5); 480183423Smarius TSBCASE(6); 481183423Smarius TSBCASE(7); 482183423Smarius TSBCASE(8); 483183423Smarius default: 484183423Smarius panic("%s: unsupported DVMA size 0x%x", 485183423Smarius __func__, prop_array[1]); 486183423Smarius /* NOTREACHED */ 487183423Smarius } 488183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 489183423Smarius } 490185133Smarius 491183423Smarius#undef TSBCASE 492183423Smarius 493183423Smarius /* Initialize memory and I/O rmans. */ 494183423Smarius sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 495183423Smarius sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 496183423Smarius if (rman_init(&sc->sc_pci_io_rman) != 0 || 497183423Smarius rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 498183423Smarius panic("%s: failed to set up I/O rman", __func__); 499183423Smarius sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 500183423Smarius sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 501183423Smarius if (rman_init(&sc->sc_pci_mem_rman) != 0 || 502183423Smarius rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 503183423Smarius panic("%s: failed to set up memory rman", __func__); 504183423Smarius 505183423Smarius nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 506183423Smarius (void **)&range); 507183423Smarius /* 508183423Smarius * Make sure that the expected ranges are present. The 509183423Smarius * OFW_PCI_CS_MEM64 one is not currently used though. 510183423Smarius */ 511183423Smarius if (nrange != STX_NRANGE) 512183423Smarius panic("%s: unsupported number of ranges", __func__); 513183423Smarius /* 514183423Smarius * Find the addresses of the various bus spaces. 515183423Smarius * There should not be multiple ones of one kind. 516183423Smarius * The physical start addresses of the ranges are the configuration, 517183423Smarius * memory and I/O handles. 518183423Smarius */ 519183423Smarius for (n = 0; n < STX_NRANGE; n++) { 520183423Smarius i = OFW_PCI_RANGE_CS(&range[n]); 521183423Smarius if (sc->sc_pci_bh[i] != 0) 522183423Smarius panic("%s: duplicate range for space %d", __func__, i); 523183423Smarius sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 524183423Smarius } 525183423Smarius free(range, M_OFWPROP); 526183423Smarius 527183423Smarius /* Register the softc, this is needed for paired Schizos. */ 528183423Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 529183423Smarius 530183423Smarius /* Allocate our tags. */ 531183423Smarius sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 532183423Smarius sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 533183423Smarius sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 534183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 535183423Smarius sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 536183423Smarius 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 537183423Smarius panic("%s: bus_dma_tag_create failed", __func__); 538183423Smarius /* Customize the tag. */ 539183423Smarius sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 540183423Smarius sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 541183423Smarius 542183423Smarius /* 543183423Smarius * Get the bus range from the firmware. 544183423Smarius * NB: Tomatillos don't support PCI bus reenumeration. 545183423Smarius */ 546183423Smarius n = OF_getprop(node, "bus-range", (void *)prop_array, 547183423Smarius sizeof(prop_array)); 548183423Smarius if (n == -1) 549183423Smarius panic("%s: could not get bus-range", __func__); 550183423Smarius if (n != sizeof(prop_array)) 551183423Smarius panic("%s: broken bus-range (%d)", __func__, n); 552183423Smarius if (bootverbose) 553183423Smarius device_printf(dev, "bus range %u to %u; PCI bus %d\n", 554183423Smarius prop_array[0], prop_array[1], prop_array[0]); 555183423Smarius sc->sc_pci_secbus = prop_array[0]; 556183423Smarius 557183423Smarius /* Clear any pending PCI error bits. */ 558183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 559183423Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 560183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 561183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 562183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 563183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 564183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 565183423Smarius 566183423Smarius /* 567183423Smarius * Establish handlers for interesting interrupts... 568183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 569183423Smarius * bus error interrupts for one PBM can be routed to the other 570183423Smarius * PBM though we obviously need to use the softc of the former 571183423Smarius * as the argument for the interrupt handler and the softc of 572183423Smarius * the latter as the argument for the interrupt controller. 573183423Smarius */ 574183423Smarius if (sc->sc_half == 0) { 575183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 576183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 577183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 578183423Smarius sica_sc == osc)) 579183423Smarius /* 580183423Smarius * We are the driver for PBM A and either also 581183423Smarius * registered the interrupt controller for us or 582183423Smarius * the driver for PBM B has probed first and 583183423Smarius * registered it for us. 584183423Smarius */ 585183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 586183423Smarius schizo_pci_bus); 587183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 588183423Smarius osc != NULL) 589183423Smarius /* 590183423Smarius * We are the driver for PBM A but registered 591183423Smarius * the interrupt controller for PBM B, i.e. the 592183423Smarius * driver for PBM B attached first but couldn't 593183423Smarius * set up a handler for PBM B. 594183423Smarius */ 595183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 596183423Smarius schizo_pci_bus); 597183423Smarius } else { 598183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 599183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 600183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 601183423Smarius sica_sc == osc)) 602183423Smarius /* 603183423Smarius * We are the driver for PBM B and either also 604183423Smarius * registered the interrupt controller for us or 605183423Smarius * the driver for PBM A has probed first and 606183423Smarius * registered it for us. 607183423Smarius */ 608183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 609183423Smarius schizo_pci_bus); 610183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 611183423Smarius osc != NULL) 612183423Smarius /* 613183423Smarius * We are the driver for PBM B but registered 614183423Smarius * the interrupt controller for PBM A, i.e. the 615183423Smarius * driver for PBM A attached first but couldn't 616183423Smarius * set up a handler for PBM A. 617183423Smarius */ 618183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 619183423Smarius schizo_pci_bus); 620183423Smarius } 621183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 622183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 623183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 624183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 625183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 626183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 627183423Smarius 628183423Smarius /* 629185133Smarius * According to the Schizo Errata I-13, consistent DMA flushing/ 630185133Smarius * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 631185133Smarius * so we can't use it and need to live with the consequences. 632185133Smarius * With Schizo version >= 5, CDMA flushing/syncing is usable 633185133Smarius * but requires the the workaround described in Schizo Errata 634185133Smarius * I-23. With Tomatillo and XMITS, CDMA flushing/syncing works 635185133Smarius * as expected, Tomatillo version <= 4 (i.e. revision <= 2.3) 636185133Smarius * bridges additionally require a block store after a write to 637185133Smarius * TOMXMS_PCI_DMA_SYNC_PEND though. 638185133Smarius */ 639185133Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 640185133Smarius sc->sc_mode == SCHIZO_MODE_TOM || sc->sc_mode == SCHIZO_MODE_XMS) { 641185133Smarius sc->sc_flags |= SCHIZO_FLAGS_CDMA; 642185133Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) { 643185133Smarius n = STX_CDMA_A_INO + sc->sc_half; 644185133Smarius if (bus_set_resource(dev, SYS_RES_IRQ, 5, 645185133Smarius INTMAP_VEC(sc->sc_ign, n), 1) != 0) 646185133Smarius panic("%s: failed to add CDMA interrupt", 647185133Smarius __func__); 648185133Smarius i = schizo_intr_register(sc, n); 649185133Smarius if (i != 0) 650185133Smarius panic("%s: could not register interrupt " 651185133Smarius "controller for CDMA (%d)", __func__, i); 652185133Smarius (void)schizo_get_intrmap(sc, n, NULL, 653185133Smarius &sc->sc_cdma_clr); 654185133Smarius sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 655185133Smarius schizo_set_intr(sc, 5, n, schizo_cdma); 656185133Smarius } 657185133Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 658185133Smarius sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 659185133Smarius } 660185133Smarius 661185133Smarius /* 662183423Smarius * Set the latency timer register as this isn't always done by the 663183423Smarius * firmware. 664183423Smarius */ 665183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 666183423Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 667183423Smarius 668183423Smarius ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 669183423Smarius 670183423Smarius device_add_child(dev, "pci", -1); 671183423Smarius return (bus_generic_attach(dev)); 672183423Smarius} 673183423Smarius 674183423Smariusstatic void 675183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 676183423Smarius driver_filter_t handler) 677183423Smarius{ 678183423Smarius u_long vec; 679183423Smarius int rid; 680183423Smarius 681183423Smarius rid = index; 682183423Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 683183423Smarius &rid, RF_ACTIVE); 684183423Smarius if (sc->sc_irq_res[index] == NULL || 685183423Smarius INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 686183423Smarius INTINO(vec) != ino || 687183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 688185133Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 689185133Smarius INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 690185133Smarius &sc->sc_ihand[index]) != 0) 691183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 692183423Smarius} 693183423Smarius 694183423Smariusstatic int 695185133Smariusschizo_intr_register(struct schizo_softc *sc, u_int ino) 696185133Smarius{ 697185133Smarius struct schizo_icarg *sica; 698185133Smarius bus_addr_t intrclr, intrmap; 699185133Smarius int error; 700185133Smarius 701185133Smarius if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 702185133Smarius return (ENXIO); 703185133Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 704185133Smarius if (sica == NULL) 705185133Smarius return (ENOMEM); 706185133Smarius sica->sica_sc = sc; 707185133Smarius sica->sica_map = intrmap; 708185133Smarius sica->sica_clr = intrclr; 709185133Smarius#ifdef SCHIZO_DEBUG 710185133Smarius device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 711185133Smarius ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 712185133Smarius (u_long)intrclr); 713185133Smarius#endif 714185133Smarius error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 715185133Smarius &schizo_ic, sica)); 716185133Smarius if (error != 0) 717185133Smarius free(sica, M_DEVBUF); 718185133Smarius return (error); 719185133Smarius} 720185133Smarius 721185133Smariusstatic int 722183423Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr, 723183423Smarius bus_addr_t *intrclrptr) 724183423Smarius{ 725183423Smarius bus_addr_t intrclr, intrmap; 726183423Smarius uint64_t mr; 727183423Smarius 728183423Smarius /* 729183423Smarius * XXX we only look for INOs rather than INRs since the firmware 730183423Smarius * may not provide the IGN and the IGN is constant for all devices 731183423Smarius * on that PCI controller. 732183423Smarius */ 733183423Smarius 734183423Smarius if (ino > STX_MAX_INO) { 735183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 736183423Smarius ino); 737183423Smarius return (0); 738183423Smarius } 739183423Smarius 740183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 741183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 742183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 743183423Smarius if (INTINO(mr) != ino) { 744183423Smarius device_printf(sc->sc_dev, 745183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 746183423Smarius (int)INTINO(mr), ino); 747183423Smarius return (0); 748183423Smarius } 749183423Smarius 750183423Smarius if (intrmapptr != NULL) 751183423Smarius *intrmapptr = intrmap; 752183423Smarius if (intrclrptr != NULL) 753183423Smarius *intrclrptr = intrclr; 754183423Smarius return (1); 755183423Smarius} 756183423Smarius 757183423Smarius/* 758183423Smarius * Interrupt handlers 759183423Smarius */ 760183423Smariusstatic int 761183423Smariusschizo_pci_bus(void *arg) 762183423Smarius{ 763183423Smarius struct schizo_softc *sc = arg; 764183423Smarius uint64_t afar, afsr, csr, iommu; 765183423Smarius uint32_t status; 766183423Smarius 767183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 768183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 769183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 770183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 771183423Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 772183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 773183423Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 774183423Smarius if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 775183423Smarius goto clear_error; 776183423Smarius 777183423Smarius /* These are non-fatal if target abort was signaled. */ 778183423Smarius if ((status & PCIM_STATUS_STABORT) != 0 && 779183423Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) == 780183423Smarius TOM_PCI_IOMMU_INVALID_ERR || 781183423Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 782183423Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 783183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 784183423Smarius goto clear_error; 785183423Smarius } 786183423Smarius } 787183423Smarius 788183423Smarius panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 789183423Smarius "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 790183423Smarius 'A' + sc->sc_half, (unsigned long long)afar, 791183423Smarius (unsigned long long)afsr, (unsigned long long)csr, 792183423Smarius (unsigned long long)iommu, (unsigned long long)status); 793183423Smarius 794183423Smarius clear_error: 795183423Smarius if (bootverbose) 796183423Smarius device_printf(sc->sc_dev, 797183423Smarius "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 798183423Smarius "STATUS %#llx", 'A' + sc->sc_half, 799183423Smarius (unsigned long long)afar, (unsigned long long)afsr, 800183423Smarius (unsigned long long)csr, (unsigned long long)status); 801183423Smarius /* Clear the error bits that we caught. */ 802183423Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 803183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 804183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 805183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 806183423Smarius return (FILTER_HANDLED); 807183423Smarius} 808183423Smarius 809183423Smariusstatic int 810183423Smariusschizo_ue(void *arg) 811183423Smarius{ 812183423Smarius struct schizo_softc *sc = arg; 813183423Smarius uint64_t afar, afsr; 814183423Smarius int i; 815183423Smarius 816183423Smarius mtx_lock_spin(sc->sc_mtx); 817183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 818183423Smarius for (i = 0; i < 1000; i++) 819183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 820183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 821183423Smarius break; 822183423Smarius mtx_unlock_spin(sc->sc_mtx); 823183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 824183423Smarius device_get_name(sc->sc_dev), (unsigned long long)afar, 825183423Smarius (unsigned long long)afsr); 826183423Smarius return (FILTER_HANDLED); 827183423Smarius} 828183423Smarius 829183423Smariusstatic int 830183423Smariusschizo_ce(void *arg) 831183423Smarius{ 832183423Smarius struct schizo_softc *sc = arg; 833183423Smarius uint64_t afar, afsr; 834183423Smarius int i; 835183423Smarius 836183423Smarius mtx_lock_spin(sc->sc_mtx); 837183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 838183423Smarius for (i = 0; i < 1000; i++) 839183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 840183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 841183423Smarius break; 842183423Smarius device_printf(sc->sc_dev, 843183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 844183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 845183423Smarius /* Clear the error bits that we caught. */ 846183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 847183423Smarius mtx_unlock_spin(sc->sc_mtx); 848183423Smarius return (FILTER_HANDLED); 849183423Smarius} 850183423Smarius 851183423Smariusstatic int 852183423Smariusschizo_host_bus(void *arg) 853183423Smarius{ 854183423Smarius struct schizo_softc *sc = arg; 855183423Smarius uint64_t errlog; 856183423Smarius 857183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 858183423Smarius panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 859183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 860183423Smarius (unsigned long long)errlog); 861183423Smarius return (FILTER_HANDLED); 862183423Smarius} 863183423Smarius 864185133Smariusstatic int 865185133Smariusschizo_cdma(void *arg) 866185133Smarius{ 867185133Smarius struct schizo_softc *sc = arg; 868185133Smarius 869185133Smarius atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 870185133Smarius return (FILTER_HANDLED); 871185133Smarius} 872185133Smarius 873183423Smariusstatic void 874183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 875183423Smarius{ 876183423Smarius 877183423Smarius /* Punch in our copies. */ 878183423Smarius sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 879183423Smarius sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 880183423Smarius sc->sc_is.is_iommu = STX_PCI_IOMMU; 881183423Smarius sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 882183423Smarius sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 883183423Smarius sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 884183423Smarius sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 885183423Smarius sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 886183423Smarius 887183423Smarius iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 888183423Smarius dvmabase, 0); 889183423Smarius} 890183423Smarius 891183423Smariusstatic int 892183423Smariusschizo_maxslots(device_t dev) 893183423Smarius{ 894183423Smarius struct schizo_softc *sc; 895183423Smarius 896183423Smarius sc = device_get_softc(dev); 897183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 898183423Smarius return (sc->sc_half == 0 ? 4 : 6); 899183423Smarius 900183423Smarius /* XXX: is this correct? */ 901183423Smarius return (PCI_SLOTMAX); 902183423Smarius} 903183423Smarius 904183423Smariusstatic uint32_t 905183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 906183423Smarius int width) 907183423Smarius{ 908183423Smarius struct schizo_softc *sc; 909183423Smarius bus_space_handle_t bh; 910183423Smarius u_long offset = 0; 911183423Smarius uint32_t r, wrd; 912183423Smarius int i; 913183423Smarius uint16_t shrt; 914183423Smarius uint8_t byte; 915183423Smarius 916183423Smarius sc = device_get_softc(dev); 917183423Smarius 918183423Smarius /* 919183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 920183423Smarius */ 921183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 922183423Smarius slot == STX_CS_DEVICE && func == STX_CS_FUNC && 923183423Smarius reg + width > 0x80) 924183423Smarius return (0); 925183423Smarius 926183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 927183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 928183423Smarius switch (width) { 929183423Smarius case 1: 930183423Smarius i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 931183423Smarius r = byte; 932183423Smarius break; 933183423Smarius case 2: 934183423Smarius i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 935183423Smarius r = shrt; 936183423Smarius break; 937183423Smarius case 4: 938183423Smarius i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 939183423Smarius r = wrd; 940183423Smarius break; 941183423Smarius default: 942183423Smarius panic("%s: bad width", __func__); 943183423Smarius /* NOTREACHED */ 944183423Smarius } 945183423Smarius 946183423Smarius if (i) { 947183423Smarius#ifdef SCHIZO_DEBUG 948183423Smarius printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 949183423Smarius __func__, bus, slot, func, reg); 950183423Smarius#endif 951183423Smarius r = -1; 952183423Smarius } 953183423Smarius return (r); 954183423Smarius} 955183423Smarius 956183423Smariusstatic void 957183423Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 958183423Smarius uint32_t val, int width) 959183423Smarius{ 960183423Smarius struct schizo_softc *sc; 961183423Smarius bus_space_handle_t bh; 962183423Smarius u_long offset = 0; 963183423Smarius 964183423Smarius sc = device_get_softc(dev); 965183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 966183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 967183423Smarius switch (width) { 968183423Smarius case 1: 969183423Smarius bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 970183423Smarius break; 971183423Smarius case 2: 972183423Smarius bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 973183423Smarius break; 974183423Smarius case 4: 975183423Smarius bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 976183423Smarius break; 977183423Smarius default: 978183423Smarius panic("%s: bad width", __func__); 979183423Smarius /* NOTREACHED */ 980183423Smarius } 981183423Smarius} 982183423Smarius 983183423Smariusstatic int 984183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 985183423Smarius{ 986183423Smarius struct schizo_softc *sc; 987183423Smarius struct ofw_pci_register reg; 988183423Smarius ofw_pci_intr_t pintr, mintr; 989183423Smarius uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 990183423Smarius 991183423Smarius sc = device_get_softc(bridge); 992183423Smarius pintr = pin; 993183423Smarius if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 994183423Smarius sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 995183423Smarius return (mintr); 996183423Smarius 997183423Smarius device_printf(bridge, "could not route pin %d for device %d.%d\n", 998183423Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 999183423Smarius return (PCI_INVALID_IRQ); 1000183423Smarius} 1001183423Smarius 1002183423Smariusstatic int 1003183423Smariusschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1004183423Smarius{ 1005183423Smarius struct schizo_softc *sc; 1006183423Smarius 1007183423Smarius sc = device_get_softc(dev); 1008183423Smarius switch (which) { 1009183423Smarius case PCIB_IVAR_DOMAIN: 1010183423Smarius *result = device_get_unit(dev); 1011183423Smarius return (0); 1012183423Smarius case PCIB_IVAR_BUS: 1013183423Smarius *result = sc->sc_pci_secbus; 1014183423Smarius return (0); 1015183423Smarius } 1016183423Smarius return (ENOENT); 1017183423Smarius} 1018183423Smarius 1019185133Smariusstatic int 1020185133Smariusschizo_dma_sync_stub(void *arg) 1021185133Smarius{ 1022185133Smarius struct timeval cur, end; 1023185133Smarius struct schizo_dma_sync *sds = arg; 1024185133Smarius struct schizo_softc *sc = sds->sds_sc; 1025185133Smarius uint32_t state; 1026185133Smarius 1027185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1028185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1029185133Smarius for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE, 1030185133Smarius SCHIZO_CDMA_STATE_PENDING) == 0;) 1031185133Smarius ; 1032185133Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1); 1033185133Smarius microuptime(&cur); 1034185133Smarius end.tv_sec = 1; 1035185133Smarius end.tv_usec = 0; 1036185133Smarius timevaladd(&end, &cur); 1037185133Smarius for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1038185133Smarius SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1039185133Smarius microuptime(&cur); 1040185133Smarius if (state != SCHIZO_CDMA_STATE_DONE) 1041185133Smarius panic("%s: DMA does not sync", __func__); 1042185133Smarius return (sds->sds_handler(sds->sds_arg)); 1043185133Smarius} 1044185133Smarius 1045183423Smarius#define VIS_BLOCKSIZE 64 1046183423Smarius 1047183423Smariusstatic int 1048185133Smariusichip_dma_sync_stub(void *arg) 1049183423Smarius{ 1050183423Smarius static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1051185133Smarius struct timeval cur, end; 1052185133Smarius struct schizo_dma_sync *sds = arg; 1053183423Smarius struct schizo_softc *sc = sds->sds_sc; 1054184428Smarius register_t reg, s; 1055183423Smarius 1056185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1057185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1058184428Smarius SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1059185133Smarius microuptime(&cur); 1060185133Smarius end.tv_sec = 1; 1061185133Smarius end.tv_usec = 0; 1062185133Smarius timevaladd(&end, &cur); 1063185133Smarius for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1064185133Smarius sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1065185133Smarius microuptime(&cur); 1066185133Smarius if ((reg & sds->sds_syncval) != 0) 1067185133Smarius panic("%s: DMA does not sync", __func__); 1068183423Smarius 1069185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1070184428Smarius s = intr_disable(); 1071183423Smarius reg = rd(fprs); 1072183423Smarius wr(fprs, reg | FPRS_FEF, 0); 1073184428Smarius __asm __volatile("stda %%f0, [%0] %1" 1074183423Smarius : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1075184428Smarius membar(Sync); 1076183423Smarius wr(fprs, reg, 0); 1077184428Smarius intr_restore(s); 1078183423Smarius } 1079183423Smarius return (sds->sds_handler(sds->sds_arg)); 1080183423Smarius} 1081183423Smarius 1082183423Smariusstatic void 1083183423Smariusschizo_intr_enable(void *arg) 1084183423Smarius{ 1085183423Smarius struct intr_vector *iv = arg; 1086183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1087183423Smarius 1088183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1089183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1090183423Smarius} 1091183423Smarius 1092183423Smariusstatic void 1093183423Smariusschizo_intr_disable(void *arg) 1094183423Smarius{ 1095183423Smarius struct intr_vector *iv = arg; 1096183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1097183423Smarius 1098183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1099183423Smarius} 1100183423Smarius 1101183423Smariusstatic void 1102183423Smariusschizo_intr_assign(void *arg) 1103183423Smarius{ 1104183423Smarius struct intr_vector *iv = arg; 1105183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1106183423Smarius 1107183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1108183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1109183423Smarius} 1110183423Smarius 1111183423Smariusstatic void 1112183423Smariusschizo_intr_clear(void *arg) 1113183423Smarius{ 1114183423Smarius struct intr_vector *iv = arg; 1115183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1116183423Smarius 1117183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0); 1118183423Smarius} 1119183423Smarius 1120183423Smariusstatic int 1121183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1122183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1123183423Smarius void **cookiep) 1124183423Smarius{ 1125185133Smarius devclass_t pci_devclass; 1126185133Smarius device_t cdev, pdev, pcidev; 1127185133Smarius struct schizo_dma_sync *sds; 1128183423Smarius struct schizo_softc *sc; 1129183423Smarius u_long vec; 1130185133Smarius int error, found; 1131183423Smarius 1132183423Smarius sc = device_get_softc(dev); 1133183423Smarius /* 1134186290Smarius * Make sure the vector is fully specified. 1135183423Smarius */ 1136183423Smarius vec = rman_get_start(ires); 1137186290Smarius if (INTIGN(vec) != sc->sc_ign) { 1138183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1139183423Smarius return (EINVAL); 1140183423Smarius } 1141183423Smarius 1142186290Smarius if (intr_vectors[vec].iv_ic == &schizo_ic) { 1143186290Smarius /* 1144186290Smarius * Ensure we use the right softc in case the interrupt 1145186290Smarius * is routed to our companion PBM for some odd reason. 1146186290Smarius */ 1147186290Smarius sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1148186290Smarius sica_sc; 1149186290Smarius } else if (intr_vectors[vec].iv_ic == NULL) { 1150186290Smarius /* 1151186290Smarius * Work around broken firmware which misses entries in 1152186290Smarius * the ino-bitmap. 1153186290Smarius */ 1154186290Smarius error = schizo_intr_register(sc, INTINO(vec)); 1155186290Smarius if (error != 0) { 1156186290Smarius device_printf(dev, "could not register interrupt " 1157186290Smarius "controller for vector 0x%lx (%d)\n", vec, error); 1158186290Smarius return (error); 1159186290Smarius } 1160190108Smarius if (bootverbose) 1161190108Smarius device_printf(dev, "belatedly registered as " 1162190108Smarius "interrupt controller for vector 0x%lx\n", vec); 1163186290Smarius } else { 1164186290Smarius device_printf(dev, 1165186290Smarius "invalid interrupt controller for vector 0x%lx\n", vec); 1166186290Smarius return (EINVAL); 1167186290Smarius } 1168186290Smarius 1169183423Smarius /* 1170185133Smarius * Install a a wrapper for CDMA flushing/syncing for devices 1171185133Smarius * behind PCI-PCI bridges if possible. 1172183423Smarius */ 1173185133Smarius pcidev = NULL; 1174185133Smarius found = 0; 1175185133Smarius pci_devclass = devclass_find("pci"); 1176185133Smarius for (cdev = child; cdev != dev; cdev = pdev) { 1177185133Smarius pdev = device_get_parent(cdev); 1178185133Smarius if (pcidev == NULL) { 1179185133Smarius if (device_get_devclass(pdev) != pci_devclass) 1180185133Smarius continue; 1181185133Smarius pcidev = cdev; 1182185133Smarius continue; 1183185133Smarius } 1184185133Smarius if (pci_get_class(cdev) == PCIC_BRIDGE && 1185185133Smarius pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1186185133Smarius found = 1; 1187185133Smarius } 1188185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1189183423Smarius sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1190183423Smarius if (sds == NULL) 1191183423Smarius return (ENOMEM); 1192185133Smarius if (found != 0 && pcidev != NULL) { 1193185133Smarius sds->sds_sc = sc; 1194185133Smarius sds->sds_arg = arg; 1195185133Smarius sds->sds_ppb = 1196185133Smarius device_get_parent(device_get_parent(pcidev)); 1197185133Smarius sds->sds_bus = pci_get_bus(pcidev); 1198185133Smarius sds->sds_slot = pci_get_slot(pcidev); 1199185133Smarius sds->sds_func = pci_get_function(pcidev); 1200185133Smarius sds->sds_syncval = 1ULL << INTINO(vec); 1201185133Smarius if (bootverbose) 1202185133Smarius device_printf(dev, "installed DMA sync " 1203185133Smarius "wrapper for device %d.%d on bus %d\n", 1204185133Smarius sds->sds_slot, sds->sds_func, 1205185133Smarius sds->sds_bus); 1206185133Smarius 1207185133Smarius#define DMA_SYNC_STUB \ 1208185133Smarius (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1209185133Smarius ichip_dma_sync_stub) 1210185133Smarius 1211185133Smarius if (intr == NULL) { 1212185133Smarius sds->sds_handler = filt; 1213185133Smarius error = bus_generic_setup_intr(dev, child, 1214185133Smarius ires, flags, DMA_SYNC_STUB, intr, sds, 1215185133Smarius cookiep); 1216185133Smarius } else { 1217185133Smarius sds->sds_handler = (driver_filter_t *)intr; 1218185133Smarius error = bus_generic_setup_intr(dev, child, 1219185133Smarius ires, flags, filt, (driver_intr_t *) 1220185133Smarius DMA_SYNC_STUB, sds, cookiep); 1221185133Smarius } 1222185133Smarius 1223185133Smarius#undef DMA_SYNC_STUB 1224185133Smarius 1225185133Smarius } else 1226183423Smarius error = bus_generic_setup_intr(dev, child, ires, 1227185133Smarius flags, filt, intr, arg, cookiep); 1228183423Smarius if (error != 0) { 1229183423Smarius free(sds, M_DEVBUF); 1230183423Smarius return (error); 1231183423Smarius } 1232183423Smarius sds->sds_cookie = *cookiep; 1233183423Smarius *cookiep = sds; 1234183423Smarius return (error); 1235185133Smarius } else if (found != 0) 1236185133Smarius device_printf(dev, "WARNING: using devices behind PCI-PCI " 1237186290Smarius "bridges may cause data corruption\n"); 1238183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1239183423Smarius arg, cookiep)); 1240183423Smarius} 1241183423Smarius 1242183423Smariusstatic int 1243183423Smariusschizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1244183423Smarius void *cookie) 1245183423Smarius{ 1246185133Smarius struct schizo_dma_sync *sds; 1247183423Smarius struct schizo_softc *sc; 1248183423Smarius int error; 1249183423Smarius 1250183423Smarius sc = device_get_softc(dev); 1251185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1252183423Smarius sds = cookie; 1253183423Smarius error = bus_generic_teardown_intr(dev, child, vec, 1254183423Smarius sds->sds_cookie); 1255183423Smarius if (error == 0) 1256183423Smarius free(sds, M_DEVBUF); 1257183423Smarius return (error); 1258183423Smarius } 1259183423Smarius return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1260183423Smarius} 1261183423Smarius 1262183423Smariusstatic struct resource * 1263183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1264183423Smarius u_long start, u_long end, u_long count, u_int flags) 1265183423Smarius{ 1266183423Smarius struct schizo_softc *sc; 1267183423Smarius struct resource *rv; 1268183423Smarius struct rman *rm; 1269183423Smarius bus_space_tag_t bt; 1270183423Smarius bus_space_handle_t bh; 1271183423Smarius int needactivate = flags & RF_ACTIVE; 1272183423Smarius 1273183423Smarius flags &= ~RF_ACTIVE; 1274183423Smarius 1275183423Smarius sc = device_get_softc(bus); 1276183423Smarius if (type == SYS_RES_IRQ) { 1277183423Smarius /* 1278183423Smarius * XXX: Don't accept blank ranges for now, only single 1279183423Smarius * interrupts. The other case should not happen with 1280183423Smarius * the MI PCI code... 1281183423Smarius * XXX: This may return a resource that is out of the 1282183423Smarius * range that was specified. Is this correct...? 1283183423Smarius */ 1284183423Smarius if (start != end) 1285183423Smarius panic("%s: XXX: interrupt range", __func__); 1286183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1287183423Smarius return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1288183423Smarius rid, start, end, count, flags)); 1289183423Smarius } 1290183423Smarius switch (type) { 1291183423Smarius case SYS_RES_MEMORY: 1292183423Smarius rm = &sc->sc_pci_mem_rman; 1293183423Smarius bt = sc->sc_pci_memt; 1294183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1295183423Smarius break; 1296183423Smarius case SYS_RES_IOPORT: 1297183423Smarius rm = &sc->sc_pci_io_rman; 1298183423Smarius bt = sc->sc_pci_iot; 1299183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1300183423Smarius break; 1301183423Smarius default: 1302183423Smarius return (NULL); 1303183423Smarius /* NOTREACHED */ 1304183423Smarius } 1305183423Smarius 1306183423Smarius rv = rman_reserve_resource(rm, start, end, count, flags, child); 1307183423Smarius if (rv == NULL) 1308183423Smarius return (NULL); 1309183423Smarius rman_set_rid(rv, *rid); 1310183423Smarius bh += rman_get_start(rv); 1311183423Smarius rman_set_bustag(rv, bt); 1312183423Smarius rman_set_bushandle(rv, bh); 1313183423Smarius 1314183423Smarius if (needactivate) { 1315183423Smarius if (bus_activate_resource(child, type, *rid, rv)) { 1316183423Smarius rman_release_resource(rv); 1317183423Smarius return (NULL); 1318183423Smarius } 1319183423Smarius } 1320183423Smarius return (rv); 1321183423Smarius} 1322183423Smarius 1323183423Smariusstatic int 1324183423Smariusschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1325183423Smarius struct resource *r) 1326183423Smarius{ 1327183423Smarius void *p; 1328183423Smarius int error; 1329183423Smarius 1330183423Smarius if (type == SYS_RES_IRQ) 1331183423Smarius return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1332183423Smarius type, rid, r)); 1333183423Smarius if (type == SYS_RES_MEMORY) { 1334183423Smarius /* 1335185133Smarius * Need to memory-map the device space, as some drivers 1336185133Smarius * depend on the virtual address being set and usable. 1337183423Smarius */ 1338183423Smarius error = sparc64_bus_mem_map(rman_get_bustag(r), 1339183423Smarius rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1340183423Smarius if (error != 0) 1341183423Smarius return (error); 1342183423Smarius rman_set_virtual(r, p); 1343183423Smarius } 1344183423Smarius return (rman_activate_resource(r)); 1345183423Smarius} 1346183423Smarius 1347183423Smariusstatic int 1348183423Smariusschizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1349183423Smarius struct resource *r) 1350183423Smarius{ 1351183423Smarius 1352183423Smarius if (type == SYS_RES_IRQ) 1353183423Smarius return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1354183423Smarius type, rid, r)); 1355183423Smarius if (type == SYS_RES_MEMORY) { 1356183423Smarius sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1357183423Smarius rman_set_virtual(r, NULL); 1358183423Smarius } 1359183423Smarius return (rman_deactivate_resource(r)); 1360183423Smarius} 1361183423Smarius 1362183423Smariusstatic int 1363183423Smariusschizo_release_resource(device_t bus, device_t child, int type, int rid, 1364183423Smarius struct resource *r) 1365183423Smarius{ 1366183423Smarius int error; 1367183423Smarius 1368183423Smarius if (type == SYS_RES_IRQ) 1369183423Smarius return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1370183423Smarius type, rid, r)); 1371183423Smarius if (rman_get_flags(r) & RF_ACTIVE) { 1372183423Smarius error = bus_deactivate_resource(child, type, rid, r); 1373183423Smarius if (error) 1374183423Smarius return (error); 1375183423Smarius } 1376183423Smarius return (rman_release_resource(r)); 1377183423Smarius} 1378183423Smarius 1379183423Smariusstatic bus_dma_tag_t 1380183423Smariusschizo_get_dma_tag(device_t bus, device_t child) 1381183423Smarius{ 1382183423Smarius struct schizo_softc *sc; 1383183423Smarius 1384183423Smarius sc = device_get_softc(bus); 1385183423Smarius return (sc->sc_pci_dmat); 1386183423Smarius} 1387183423Smarius 1388183423Smariusstatic phandle_t 1389183423Smariusschizo_get_node(device_t bus, device_t dev) 1390183423Smarius{ 1391183423Smarius struct schizo_softc *sc; 1392183423Smarius 1393183423Smarius sc = device_get_softc(bus); 1394183423Smarius /* We only have one child, the PCI bus, which needs our own node. */ 1395183423Smarius return (sc->sc_node); 1396183423Smarius} 1397183423Smarius 1398183423Smariusstatic bus_space_tag_t 1399183423Smariusschizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1400183423Smarius{ 1401183423Smarius bus_space_tag_t bt; 1402183423Smarius 1403183423Smarius bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1404183423Smarius M_NOWAIT | M_ZERO); 1405183423Smarius if (bt == NULL) 1406183423Smarius panic("%s: out of memory", __func__); 1407183423Smarius 1408183423Smarius bt->bst_cookie = sc; 1409183423Smarius bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1410183423Smarius bt->bst_type = type; 1411183423Smarius return (bt); 1412183423Smarius} 1413183423Smarius 1414183423Smariusstatic u_int 1415183423Smariusschizo_get_timecount(struct timecounter *tc) 1416183423Smarius{ 1417183423Smarius struct schizo_softc *sc; 1418183423Smarius 1419183423Smarius sc = tc->tc_priv; 1420183423Smarius return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1421183423Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1422183423Smarius} 1423