schizo.c revision 190108
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 190108 2009-03-19 20:48:47Z marius $"); 36 37/* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39 * PCI 2.2 bridges 40 */ 41 42#include "opt_ofw_pci.h" 43#include "opt_schizo.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/rman.h> 55#include <sys/time.h> 56#include <sys/timetc.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/fsr.h> 66#include <machine/iommureg.h> 67#include <machine/iommuvar.h> 68#include <machine/resource.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73#include <sparc64/pci/ofw_pci.h> 74#include <sparc64/pci/schizoreg.h> 75#include <sparc64/pci/schizovar.h> 76 77#include "pcib_if.h" 78 79static const struct schizo_desc *schizo_get_desc(device_t); 80static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 81 driver_filter_t); 82static driver_filter_t schizo_dma_sync_stub; 83static driver_filter_t ichip_dma_sync_stub; 84static void schizo_intr_enable(void *); 85static void schizo_intr_disable(void *); 86static void schizo_intr_assign(void *); 87static void schizo_intr_clear(void *); 88static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 89static int schizo_get_intrmap(struct schizo_softc *, u_int, 90 bus_addr_t *, bus_addr_t *); 91static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 92static timecounter_get_t schizo_get_timecount; 93 94/* Interrupt handlers */ 95static driver_filter_t schizo_pci_bus; 96static driver_filter_t schizo_ue; 97static driver_filter_t schizo_ce; 98static driver_filter_t schizo_host_bus; 99static driver_filter_t schizo_cdma; 100 101/* IOMMU support */ 102static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 103 104/* 105 * Methods 106 */ 107static device_probe_t schizo_probe; 108static device_attach_t schizo_attach; 109static bus_read_ivar_t schizo_read_ivar; 110static bus_setup_intr_t schizo_setup_intr; 111static bus_teardown_intr_t schizo_teardown_intr; 112static bus_alloc_resource_t schizo_alloc_resource; 113static bus_activate_resource_t schizo_activate_resource; 114static bus_deactivate_resource_t schizo_deactivate_resource; 115static bus_release_resource_t schizo_release_resource; 116static bus_get_dma_tag_t schizo_get_dma_tag; 117static pcib_maxslots_t schizo_maxslots; 118static pcib_read_config_t schizo_read_config; 119static pcib_write_config_t schizo_write_config; 120static pcib_route_interrupt_t schizo_route_interrupt; 121static ofw_bus_get_node_t schizo_get_node; 122 123static device_method_t schizo_methods[] = { 124 /* Device interface */ 125 DEVMETHOD(device_probe, schizo_probe), 126 DEVMETHOD(device_attach, schizo_attach), 127 DEVMETHOD(device_shutdown, bus_generic_shutdown), 128 DEVMETHOD(device_suspend, bus_generic_suspend), 129 DEVMETHOD(device_resume, bus_generic_resume), 130 131 /* Bus interface */ 132 DEVMETHOD(bus_print_child, bus_generic_print_child), 133 DEVMETHOD(bus_read_ivar, schizo_read_ivar), 134 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 135 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 136 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 137 DEVMETHOD(bus_activate_resource, schizo_activate_resource), 138 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 139 DEVMETHOD(bus_release_resource, schizo_release_resource), 140 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 141 142 /* pcib interface */ 143 DEVMETHOD(pcib_maxslots, schizo_maxslots), 144 DEVMETHOD(pcib_read_config, schizo_read_config), 145 DEVMETHOD(pcib_write_config, schizo_write_config), 146 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 147 148 /* ofw_bus interface */ 149 DEVMETHOD(ofw_bus_get_node, schizo_get_node), 150 151 KOBJMETHOD_END 152}; 153 154static devclass_t schizo_devclass; 155 156DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 157 sizeof(struct schizo_softc)); 158DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 159 160static SLIST_HEAD(, schizo_softc) schizo_softcs = 161 SLIST_HEAD_INITIALIZER(schizo_softcs); 162 163static const struct intr_controller schizo_ic = { 164 schizo_intr_enable, 165 schizo_intr_disable, 166 schizo_intr_assign, 167 schizo_intr_clear 168}; 169 170struct schizo_icarg { 171 struct schizo_softc *sica_sc; 172 bus_addr_t sica_map; 173 bus_addr_t sica_clr; 174}; 175 176struct schizo_dma_sync { 177 struct schizo_softc *sds_sc; 178 driver_filter_t *sds_handler; 179 void *sds_arg; 180 void *sds_cookie; 181 uint64_t sds_syncval; 182 device_t sds_ppb; /* farest PCI-PCI bridge */ 183 uint8_t sds_bus; /* bus of farest PCI device */ 184 uint8_t sds_slot; /* slot of farest PCI device */ 185 uint8_t sds_func; /* func. of farest PCI device */ 186}; 187 188#define SCHIZO_PERF_CNT_QLTY 100 189 190#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 191 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 192#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 193 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 194 195#define SCHIZO_PCI_READ_8(sc, offs) \ 196 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 197#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 198 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 199#define SCHIZO_CTRL_READ_8(sc, offs) \ 200 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 201#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 202 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 203#define SCHIZO_PCICFG_READ_8(sc, offs) \ 204 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 205#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 206 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 207#define SCHIZO_ICON_READ_8(sc, offs) \ 208 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 209#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 210 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 211 212#define OFW_PCI_TYPE "pci" 213 214struct schizo_desc { 215 const char *sd_string; 216 int sd_mode; 217 const char *sd_name; 218}; 219 220static const struct schizo_desc const schizo_compats[] = { 221 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 222 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 223 { NULL, 0, NULL } 224}; 225 226static const struct schizo_desc * 227schizo_get_desc(device_t dev) 228{ 229 const struct schizo_desc *desc; 230 const char *compat; 231 232 compat = ofw_bus_get_compat(dev); 233 if (compat == NULL) 234 return (NULL); 235 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 236 if (strcmp(desc->sd_string, compat) == 0) 237 return (desc); 238 return (NULL); 239} 240 241static int 242schizo_probe(device_t dev) 243{ 244 const char *dtype; 245 246 dtype = ofw_bus_get_type(dev); 247 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 248 schizo_get_desc(dev) != NULL) { 249 device_set_desc(dev, "Sun Host-PCI bridge"); 250 return (0); 251 } 252 return (ENXIO); 253} 254 255static int 256schizo_attach(device_t dev) 257{ 258 struct ofw_pci_ranges *range; 259 const struct schizo_desc *desc; 260 struct schizo_softc *asc, *sc, *osc; 261 struct timecounter *tc; 262 uint64_t ino_bitmap, reg; 263 phandle_t node; 264 uint32_t prop, prop_array[2]; 265 int i, mode, n, nrange, rid, tsbsize; 266 267 sc = device_get_softc(dev); 268 node = ofw_bus_get_node(dev); 269 desc = schizo_get_desc(dev); 270 mode = desc->sd_mode; 271 272 sc->sc_dev = dev; 273 sc->sc_node = node; 274 sc->sc_mode = mode; 275 sc->sc_flags = 0; 276 277 /* 278 * The Schizo has three register banks: 279 * (0) per-PBM PCI configuration and status registers, but for bus B 280 * shared with the UPA64s interrupt mapping register banks 281 * (1) shared Schizo controller configuration and status registers 282 * (2) per-PBM PCI configuration space 283 * 284 * The Tomatillo has four register banks: 285 * (0) per-PBM PCI configuration and status registers 286 * (1) per-PBM Tomatillo controller configuration registers, but on 287 * machines having the `jbusppm' device shared with its Estar 288 * register bank for bus A 289 * (2) per-PBM PCI configuration space 290 * (3) per-PBM interrupt concentrator registers 291 */ 292 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 293 20) & 1; 294 for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 295 n++) { 296 rid = n; 297 sc->sc_mem_res[n] = bus_alloc_resource_any(dev, 298 SYS_RES_MEMORY, &rid, 299 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 300 n == STX_PCI) || n == STX_CTRL)) || 301 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 302 n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 303 if (sc->sc_mem_res[n] == NULL) 304 panic("%s: could not allocate register bank %d", 305 __func__, n); 306 } 307 308 /* 309 * Match other Schizos that are already configured against 310 * the controller base physical address. This will be the 311 * same for a pair of devices that share register space. 312 */ 313 osc = NULL; 314 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 315 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 316 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 317 /* Found partner. */ 318 osc = asc; 319 break; 320 } 321 } 322 if (osc == NULL) { 323 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 324 M_NOWAIT | M_ZERO); 325 if (sc->sc_mtx == NULL) 326 panic("%s: could not malloc mutex", __func__); 327 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 328 } else { 329 if (sc->sc_mode != SCHIZO_MODE_SCZ) 330 panic("%s: no partner expected", __func__); 331 if (mtx_initialized(osc->sc_mtx) == 0) 332 panic("%s: mutex not initialized", __func__); 333 sc->sc_mtx = osc->sc_mtx; 334 } 335 336 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 337 panic("%s: could not determine IGN", __func__); 338 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1) 339 panic("%s: could not determine version", __func__); 340 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 341 prop = 33000000; 342 343 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 344 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 345 prop / 1000 / 1000); 346 347 /* Set up the PCI interrupt retry timer. */ 348#ifdef SCHIZO_DEBUG 349 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 350 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 351#endif 352 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 353 354 /* Set up the PCI control register. */ 355 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 356 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 357 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 358 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 359 if (OF_getproplen(node, "no-bus-parking") < 0) 360 reg |= STX_PCI_CTRL_ARB_PARK; 361 if (mode == SCHIZO_MODE_TOM) { 362 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 363 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 364 reg |= TOM_PCI_CTRL_DTO_IEN; 365 else 366 reg |= STX_PCI_CTRL_PTO; 367 } 368#ifdef SCHIZO_DEBUG 369 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 370 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 371 (unsigned long long)reg); 372#endif 373 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 374 375 /* Set up the PCI diagnostic register. */ 376 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 377 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 378 STX_PCI_DIAG_INTRSYNC_DIS); 379#ifdef SCHIZO_DEBUG 380 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 381 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 382 (unsigned long long)reg); 383#endif 384 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 385 386 /* 387 * On Tomatillo clear the I/O prefetch lengths (workaround for a 388 * Jalapeno bug). 389 */ 390 if (mode == SCHIZO_MODE_TOM) 391 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 392 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 393 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 394 395 /* 396 * Hunt through all the interrupt mapping regs and register 397 * the interrupt controller for our interrupt vectors. We do 398 * this early in order to be able to catch stray interrupts. 399 * This is complicated by the fact that a pair of Schizo PBMs 400 * shares one IGN. 401 */ 402 n = OF_getprop(node, "ino-bitmap", (void *)prop_array, 403 sizeof(prop_array)); 404 if (n == -1) 405 panic("%s: could not get ino-bitmap", __func__); 406 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 407 for (n = 0; n <= STX_MAX_INO; n++) { 408 if ((ino_bitmap & (1ULL << n)) == 0) 409 continue; 410 if (n == STX_FB0_INO || n == STX_FB1_INO) 411 /* Leave for upa(4). */ 412 continue; 413 i = schizo_intr_register(sc, n); 414 if (i != 0) 415 device_printf(dev, "could not register interrupt " 416 "controller for INO %d (%d)\n", n, i); 417 } 418 419 /* 420 * Setup Safari/JBus performance counter 0 in bus cycle counting 421 * mode as timecounter. Unfortunately, this is broken with at 422 * least the version 4 Tomatillos found in Fire V120 and Blade 423 * 1500, which apparently actually count some different event at 424 * ~0.5 and 3MHz respectively instead (also when running in full 425 * power mode). Besides, one counter seems to be shared by a 426 * "pair" of Tomatillos, too. 427 */ 428 if (sc->sc_half == 0) { 429 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 430 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 431 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 432 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 433 if (tc == NULL) 434 panic("%s: could not malloc timecounter", __func__); 435 tc->tc_get_timecount = schizo_get_timecount; 436 tc->tc_poll_pps = NULL; 437 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 438 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 439 sizeof(prop)) == -1) 440 panic("%s: could not determine clock frequency", 441 __func__); 442 tc->tc_frequency = prop; 443 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 444 if (mode == SCHIZO_MODE_SCZ) 445 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 446 else 447 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 448 tc->tc_priv = sc; 449 tc_init(tc); 450 } 451 452 /* 453 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 454 * one per PBM. Schizo and XMITS additionally have a streaming 455 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 456 * affected by several errata and basically unusable though. 457 */ 458 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 459 sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0; 460 if (OF_getproplen(node, "no-streaming-cache") < 0 && 461 !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 462 sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 463 464#define TSBCASE(x) \ 465 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 466 tsbsize = (x); \ 467 break; \ 468 469 n = OF_getprop(node, "virtual-dma", (void *)prop_array, 470 sizeof(prop_array)); 471 if (n == -1 || n != sizeof(prop_array)) 472 schizo_iommu_init(sc, 7, -1); 473 else { 474 switch (prop_array[1]) { 475 TSBCASE(1); 476 TSBCASE(2); 477 TSBCASE(3); 478 TSBCASE(4); 479 TSBCASE(5); 480 TSBCASE(6); 481 TSBCASE(7); 482 TSBCASE(8); 483 default: 484 panic("%s: unsupported DVMA size 0x%x", 485 __func__, prop_array[1]); 486 /* NOTREACHED */ 487 } 488 schizo_iommu_init(sc, tsbsize, prop_array[0]); 489 } 490 491#undef TSBCASE 492 493 /* Initialize memory and I/O rmans. */ 494 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 495 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 496 if (rman_init(&sc->sc_pci_io_rman) != 0 || 497 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 498 panic("%s: failed to set up I/O rman", __func__); 499 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 500 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 501 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 502 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 503 panic("%s: failed to set up memory rman", __func__); 504 505 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 506 (void **)&range); 507 /* 508 * Make sure that the expected ranges are present. The 509 * OFW_PCI_CS_MEM64 one is not currently used though. 510 */ 511 if (nrange != STX_NRANGE) 512 panic("%s: unsupported number of ranges", __func__); 513 /* 514 * Find the addresses of the various bus spaces. 515 * There should not be multiple ones of one kind. 516 * The physical start addresses of the ranges are the configuration, 517 * memory and I/O handles. 518 */ 519 for (n = 0; n < STX_NRANGE; n++) { 520 i = OFW_PCI_RANGE_CS(&range[n]); 521 if (sc->sc_pci_bh[i] != 0) 522 panic("%s: duplicate range for space %d", __func__, i); 523 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 524 } 525 free(range, M_OFWPROP); 526 527 /* Register the softc, this is needed for paired Schizos. */ 528 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 529 530 /* Allocate our tags. */ 531 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 532 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 533 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 534 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 535 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 536 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 537 panic("%s: bus_dma_tag_create failed", __func__); 538 /* Customize the tag. */ 539 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 540 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 541 542 /* 543 * Get the bus range from the firmware. 544 * NB: Tomatillos don't support PCI bus reenumeration. 545 */ 546 n = OF_getprop(node, "bus-range", (void *)prop_array, 547 sizeof(prop_array)); 548 if (n == -1) 549 panic("%s: could not get bus-range", __func__); 550 if (n != sizeof(prop_array)) 551 panic("%s: broken bus-range (%d)", __func__, n); 552 if (bootverbose) 553 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 554 prop_array[0], prop_array[1], prop_array[0]); 555 sc->sc_pci_secbus = prop_array[0]; 556 557 /* Clear any pending PCI error bits. */ 558 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 559 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 560 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 561 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 562 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 563 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 564 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 565 566 /* 567 * Establish handlers for interesting interrupts... 568 * Someone at Sun clearly was smoking crack; with Schizos PCI 569 * bus error interrupts for one PBM can be routed to the other 570 * PBM though we obviously need to use the softc of the former 571 * as the argument for the interrupt handler and the softc of 572 * the latter as the argument for the interrupt controller. 573 */ 574 if (sc->sc_half == 0) { 575 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 576 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 577 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 578 sica_sc == osc)) 579 /* 580 * We are the driver for PBM A and either also 581 * registered the interrupt controller for us or 582 * the driver for PBM B has probed first and 583 * registered it for us. 584 */ 585 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 586 schizo_pci_bus); 587 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 588 osc != NULL) 589 /* 590 * We are the driver for PBM A but registered 591 * the interrupt controller for PBM B, i.e. the 592 * driver for PBM B attached first but couldn't 593 * set up a handler for PBM B. 594 */ 595 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 596 schizo_pci_bus); 597 } else { 598 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 599 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 600 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 601 sica_sc == osc)) 602 /* 603 * We are the driver for PBM B and either also 604 * registered the interrupt controller for us or 605 * the driver for PBM A has probed first and 606 * registered it for us. 607 */ 608 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 609 schizo_pci_bus); 610 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 611 osc != NULL) 612 /* 613 * We are the driver for PBM B but registered 614 * the interrupt controller for PBM A, i.e. the 615 * driver for PBM A attached first but couldn't 616 * set up a handler for PBM A. 617 */ 618 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 619 schizo_pci_bus); 620 } 621 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 622 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 623 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 624 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 625 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 626 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 627 628 /* 629 * According to the Schizo Errata I-13, consistent DMA flushing/ 630 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 631 * so we can't use it and need to live with the consequences. 632 * With Schizo version >= 5, CDMA flushing/syncing is usable 633 * but requires the the workaround described in Schizo Errata 634 * I-23. With Tomatillo and XMITS, CDMA flushing/syncing works 635 * as expected, Tomatillo version <= 4 (i.e. revision <= 2.3) 636 * bridges additionally require a block store after a write to 637 * TOMXMS_PCI_DMA_SYNC_PEND though. 638 */ 639 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 640 sc->sc_mode == SCHIZO_MODE_TOM || sc->sc_mode == SCHIZO_MODE_XMS) { 641 sc->sc_flags |= SCHIZO_FLAGS_CDMA; 642 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 643 n = STX_CDMA_A_INO + sc->sc_half; 644 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 645 INTMAP_VEC(sc->sc_ign, n), 1) != 0) 646 panic("%s: failed to add CDMA interrupt", 647 __func__); 648 i = schizo_intr_register(sc, n); 649 if (i != 0) 650 panic("%s: could not register interrupt " 651 "controller for CDMA (%d)", __func__, i); 652 (void)schizo_get_intrmap(sc, n, NULL, 653 &sc->sc_cdma_clr); 654 sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 655 schizo_set_intr(sc, 5, n, schizo_cdma); 656 } 657 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 658 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 659 } 660 661 /* 662 * Set the latency timer register as this isn't always done by the 663 * firmware. 664 */ 665 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 666 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 667 668 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 669 670 device_add_child(dev, "pci", -1); 671 return (bus_generic_attach(dev)); 672} 673 674static void 675schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 676 driver_filter_t handler) 677{ 678 u_long vec; 679 int rid; 680 681 rid = index; 682 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 683 &rid, RF_ACTIVE); 684 if (sc->sc_irq_res[index] == NULL || 685 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 686 INTINO(vec) != ino || 687 intr_vectors[vec].iv_ic != &schizo_ic || 688 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 689 INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 690 &sc->sc_ihand[index]) != 0) 691 panic("%s: failed to set up interrupt %d", __func__, index); 692} 693 694static int 695schizo_intr_register(struct schizo_softc *sc, u_int ino) 696{ 697 struct schizo_icarg *sica; 698 bus_addr_t intrclr, intrmap; 699 int error; 700 701 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 702 return (ENXIO); 703 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 704 if (sica == NULL) 705 return (ENOMEM); 706 sica->sica_sc = sc; 707 sica->sica_map = intrmap; 708 sica->sica_clr = intrclr; 709#ifdef SCHIZO_DEBUG 710 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 711 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 712 (u_long)intrclr); 713#endif 714 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 715 &schizo_ic, sica)); 716 if (error != 0) 717 free(sica, M_DEVBUF); 718 return (error); 719} 720 721static int 722schizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr, 723 bus_addr_t *intrclrptr) 724{ 725 bus_addr_t intrclr, intrmap; 726 uint64_t mr; 727 728 /* 729 * XXX we only look for INOs rather than INRs since the firmware 730 * may not provide the IGN and the IGN is constant for all devices 731 * on that PCI controller. 732 */ 733 734 if (ino > STX_MAX_INO) { 735 device_printf(sc->sc_dev, "out of range INO %d requested\n", 736 ino); 737 return (0); 738 } 739 740 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 741 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 742 mr = SCHIZO_PCI_READ_8(sc, intrmap); 743 if (INTINO(mr) != ino) { 744 device_printf(sc->sc_dev, 745 "interrupt map entry does not match INO (%d != %d)\n", 746 (int)INTINO(mr), ino); 747 return (0); 748 } 749 750 if (intrmapptr != NULL) 751 *intrmapptr = intrmap; 752 if (intrclrptr != NULL) 753 *intrclrptr = intrclr; 754 return (1); 755} 756 757/* 758 * Interrupt handlers 759 */ 760static int 761schizo_pci_bus(void *arg) 762{ 763 struct schizo_softc *sc = arg; 764 uint64_t afar, afsr, csr, iommu; 765 uint32_t status; 766 767 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 768 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 769 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 770 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 771 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 772 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 773 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 774 if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 775 goto clear_error; 776 777 /* These are non-fatal if target abort was signaled. */ 778 if ((status & PCIM_STATUS_STABORT) != 0 && 779 ((iommu & TOM_PCI_IOMMU_ERRMASK) == 780 TOM_PCI_IOMMU_INVALID_ERR || 781 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 782 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 783 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 784 goto clear_error; 785 } 786 } 787 788 panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 789 "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 790 'A' + sc->sc_half, (unsigned long long)afar, 791 (unsigned long long)afsr, (unsigned long long)csr, 792 (unsigned long long)iommu, (unsigned long long)status); 793 794 clear_error: 795 if (bootverbose) 796 device_printf(sc->sc_dev, 797 "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 798 "STATUS %#llx", 'A' + sc->sc_half, 799 (unsigned long long)afar, (unsigned long long)afsr, 800 (unsigned long long)csr, (unsigned long long)status); 801 /* Clear the error bits that we caught. */ 802 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 803 STX_CS_FUNC, PCIR_STATUS, status, 2); 804 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 805 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 806 return (FILTER_HANDLED); 807} 808 809static int 810schizo_ue(void *arg) 811{ 812 struct schizo_softc *sc = arg; 813 uint64_t afar, afsr; 814 int i; 815 816 mtx_lock_spin(sc->sc_mtx); 817 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 818 for (i = 0; i < 1000; i++) 819 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 820 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 821 break; 822 mtx_unlock_spin(sc->sc_mtx); 823 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 824 device_get_name(sc->sc_dev), (unsigned long long)afar, 825 (unsigned long long)afsr); 826 return (FILTER_HANDLED); 827} 828 829static int 830schizo_ce(void *arg) 831{ 832 struct schizo_softc *sc = arg; 833 uint64_t afar, afsr; 834 int i; 835 836 mtx_lock_spin(sc->sc_mtx); 837 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 838 for (i = 0; i < 1000; i++) 839 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 840 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 841 break; 842 device_printf(sc->sc_dev, 843 "correctable DMA error AFAR %#llx AFSR %#llx\n", 844 (unsigned long long)afar, (unsigned long long)afsr); 845 /* Clear the error bits that we caught. */ 846 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 847 mtx_unlock_spin(sc->sc_mtx); 848 return (FILTER_HANDLED); 849} 850 851static int 852schizo_host_bus(void *arg) 853{ 854 struct schizo_softc *sc = arg; 855 uint64_t errlog; 856 857 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 858 panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 859 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 860 (unsigned long long)errlog); 861 return (FILTER_HANDLED); 862} 863 864static int 865schizo_cdma(void *arg) 866{ 867 struct schizo_softc *sc = arg; 868 869 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 870 return (FILTER_HANDLED); 871} 872 873static void 874schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 875{ 876 877 /* Punch in our copies. */ 878 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 879 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 880 sc->sc_is.is_iommu = STX_PCI_IOMMU; 881 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 882 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 883 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 884 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 885 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 886 887 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 888 dvmabase, 0); 889} 890 891static int 892schizo_maxslots(device_t dev) 893{ 894 struct schizo_softc *sc; 895 896 sc = device_get_softc(dev); 897 if (sc->sc_mode == SCHIZO_MODE_SCZ) 898 return (sc->sc_half == 0 ? 4 : 6); 899 900 /* XXX: is this correct? */ 901 return (PCI_SLOTMAX); 902} 903 904static uint32_t 905schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 906 int width) 907{ 908 struct schizo_softc *sc; 909 bus_space_handle_t bh; 910 u_long offset = 0; 911 uint32_t r, wrd; 912 int i; 913 uint16_t shrt; 914 uint8_t byte; 915 916 sc = device_get_softc(dev); 917 918 /* 919 * The Schizo bridges contain a dupe of their header at 0x80. 920 */ 921 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 922 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 923 reg + width > 0x80) 924 return (0); 925 926 offset = STX_CONF_OFF(bus, slot, func, reg); 927 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 928 switch (width) { 929 case 1: 930 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 931 r = byte; 932 break; 933 case 2: 934 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 935 r = shrt; 936 break; 937 case 4: 938 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 939 r = wrd; 940 break; 941 default: 942 panic("%s: bad width", __func__); 943 /* NOTREACHED */ 944 } 945 946 if (i) { 947#ifdef SCHIZO_DEBUG 948 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 949 __func__, bus, slot, func, reg); 950#endif 951 r = -1; 952 } 953 return (r); 954} 955 956static void 957schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 958 uint32_t val, int width) 959{ 960 struct schizo_softc *sc; 961 bus_space_handle_t bh; 962 u_long offset = 0; 963 964 sc = device_get_softc(dev); 965 offset = STX_CONF_OFF(bus, slot, func, reg); 966 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 967 switch (width) { 968 case 1: 969 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 970 break; 971 case 2: 972 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 973 break; 974 case 4: 975 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 976 break; 977 default: 978 panic("%s: bad width", __func__); 979 /* NOTREACHED */ 980 } 981} 982 983static int 984schizo_route_interrupt(device_t bridge, device_t dev, int pin) 985{ 986 struct schizo_softc *sc; 987 struct ofw_pci_register reg; 988 ofw_pci_intr_t pintr, mintr; 989 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 990 991 sc = device_get_softc(bridge); 992 pintr = pin; 993 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 994 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 995 return (mintr); 996 997 device_printf(bridge, "could not route pin %d for device %d.%d\n", 998 pin, pci_get_slot(dev), pci_get_function(dev)); 999 return (PCI_INVALID_IRQ); 1000} 1001 1002static int 1003schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1004{ 1005 struct schizo_softc *sc; 1006 1007 sc = device_get_softc(dev); 1008 switch (which) { 1009 case PCIB_IVAR_DOMAIN: 1010 *result = device_get_unit(dev); 1011 return (0); 1012 case PCIB_IVAR_BUS: 1013 *result = sc->sc_pci_secbus; 1014 return (0); 1015 } 1016 return (ENOENT); 1017} 1018 1019static int 1020schizo_dma_sync_stub(void *arg) 1021{ 1022 struct timeval cur, end; 1023 struct schizo_dma_sync *sds = arg; 1024 struct schizo_softc *sc = sds->sds_sc; 1025 uint32_t state; 1026 1027 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1028 sds->sds_func, PCIR_VENDOR, 2); 1029 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE, 1030 SCHIZO_CDMA_STATE_PENDING) == 0;) 1031 ; 1032 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1); 1033 microuptime(&cur); 1034 end.tv_sec = 1; 1035 end.tv_usec = 0; 1036 timevaladd(&end, &cur); 1037 for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1038 SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1039 microuptime(&cur); 1040 if (state != SCHIZO_CDMA_STATE_DONE) 1041 panic("%s: DMA does not sync", __func__); 1042 return (sds->sds_handler(sds->sds_arg)); 1043} 1044 1045#define VIS_BLOCKSIZE 64 1046 1047static int 1048ichip_dma_sync_stub(void *arg) 1049{ 1050 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1051 struct timeval cur, end; 1052 struct schizo_dma_sync *sds = arg; 1053 struct schizo_softc *sc = sds->sds_sc; 1054 register_t reg, s; 1055 1056 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1057 sds->sds_func, PCIR_VENDOR, 2); 1058 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1059 microuptime(&cur); 1060 end.tv_sec = 1; 1061 end.tv_usec = 0; 1062 timevaladd(&end, &cur); 1063 for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1064 sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1065 microuptime(&cur); 1066 if ((reg & sds->sds_syncval) != 0) 1067 panic("%s: DMA does not sync", __func__); 1068 1069 if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1070 s = intr_disable(); 1071 reg = rd(fprs); 1072 wr(fprs, reg | FPRS_FEF, 0); 1073 __asm __volatile("stda %%f0, [%0] %1" 1074 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1075 membar(Sync); 1076 wr(fprs, reg, 0); 1077 intr_restore(s); 1078 } 1079 return (sds->sds_handler(sds->sds_arg)); 1080} 1081 1082static void 1083schizo_intr_enable(void *arg) 1084{ 1085 struct intr_vector *iv = arg; 1086 struct schizo_icarg *sica = iv->iv_icarg; 1087 1088 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1089 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1090} 1091 1092static void 1093schizo_intr_disable(void *arg) 1094{ 1095 struct intr_vector *iv = arg; 1096 struct schizo_icarg *sica = iv->iv_icarg; 1097 1098 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1099} 1100 1101static void 1102schizo_intr_assign(void *arg) 1103{ 1104 struct intr_vector *iv = arg; 1105 struct schizo_icarg *sica = iv->iv_icarg; 1106 1107 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1108 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1109} 1110 1111static void 1112schizo_intr_clear(void *arg) 1113{ 1114 struct intr_vector *iv = arg; 1115 struct schizo_icarg *sica = iv->iv_icarg; 1116 1117 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0); 1118} 1119 1120static int 1121schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1122 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1123 void **cookiep) 1124{ 1125 devclass_t pci_devclass; 1126 device_t cdev, pdev, pcidev; 1127 struct schizo_dma_sync *sds; 1128 struct schizo_softc *sc; 1129 u_long vec; 1130 int error, found; 1131 1132 sc = device_get_softc(dev); 1133 /* 1134 * Make sure the vector is fully specified. 1135 */ 1136 vec = rman_get_start(ires); 1137 if (INTIGN(vec) != sc->sc_ign) { 1138 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1139 return (EINVAL); 1140 } 1141 1142 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1143 /* 1144 * Ensure we use the right softc in case the interrupt 1145 * is routed to our companion PBM for some odd reason. 1146 */ 1147 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1148 sica_sc; 1149 } else if (intr_vectors[vec].iv_ic == NULL) { 1150 /* 1151 * Work around broken firmware which misses entries in 1152 * the ino-bitmap. 1153 */ 1154 error = schizo_intr_register(sc, INTINO(vec)); 1155 if (error != 0) { 1156 device_printf(dev, "could not register interrupt " 1157 "controller for vector 0x%lx (%d)\n", vec, error); 1158 return (error); 1159 } 1160 if (bootverbose) 1161 device_printf(dev, "belatedly registered as " 1162 "interrupt controller for vector 0x%lx\n", vec); 1163 } else { 1164 device_printf(dev, 1165 "invalid interrupt controller for vector 0x%lx\n", vec); 1166 return (EINVAL); 1167 } 1168 1169 /* 1170 * Install a a wrapper for CDMA flushing/syncing for devices 1171 * behind PCI-PCI bridges if possible. 1172 */ 1173 pcidev = NULL; 1174 found = 0; 1175 pci_devclass = devclass_find("pci"); 1176 for (cdev = child; cdev != dev; cdev = pdev) { 1177 pdev = device_get_parent(cdev); 1178 if (pcidev == NULL) { 1179 if (device_get_devclass(pdev) != pci_devclass) 1180 continue; 1181 pcidev = cdev; 1182 continue; 1183 } 1184 if (pci_get_class(cdev) == PCIC_BRIDGE && 1185 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1186 found = 1; 1187 } 1188 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1189 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1190 if (sds == NULL) 1191 return (ENOMEM); 1192 if (found != 0 && pcidev != NULL) { 1193 sds->sds_sc = sc; 1194 sds->sds_arg = arg; 1195 sds->sds_ppb = 1196 device_get_parent(device_get_parent(pcidev)); 1197 sds->sds_bus = pci_get_bus(pcidev); 1198 sds->sds_slot = pci_get_slot(pcidev); 1199 sds->sds_func = pci_get_function(pcidev); 1200 sds->sds_syncval = 1ULL << INTINO(vec); 1201 if (bootverbose) 1202 device_printf(dev, "installed DMA sync " 1203 "wrapper for device %d.%d on bus %d\n", 1204 sds->sds_slot, sds->sds_func, 1205 sds->sds_bus); 1206 1207#define DMA_SYNC_STUB \ 1208 (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1209 ichip_dma_sync_stub) 1210 1211 if (intr == NULL) { 1212 sds->sds_handler = filt; 1213 error = bus_generic_setup_intr(dev, child, 1214 ires, flags, DMA_SYNC_STUB, intr, sds, 1215 cookiep); 1216 } else { 1217 sds->sds_handler = (driver_filter_t *)intr; 1218 error = bus_generic_setup_intr(dev, child, 1219 ires, flags, filt, (driver_intr_t *) 1220 DMA_SYNC_STUB, sds, cookiep); 1221 } 1222 1223#undef DMA_SYNC_STUB 1224 1225 } else 1226 error = bus_generic_setup_intr(dev, child, ires, 1227 flags, filt, intr, arg, cookiep); 1228 if (error != 0) { 1229 free(sds, M_DEVBUF); 1230 return (error); 1231 } 1232 sds->sds_cookie = *cookiep; 1233 *cookiep = sds; 1234 return (error); 1235 } else if (found != 0) 1236 device_printf(dev, "WARNING: using devices behind PCI-PCI " 1237 "bridges may cause data corruption\n"); 1238 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1239 arg, cookiep)); 1240} 1241 1242static int 1243schizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1244 void *cookie) 1245{ 1246 struct schizo_dma_sync *sds; 1247 struct schizo_softc *sc; 1248 int error; 1249 1250 sc = device_get_softc(dev); 1251 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1252 sds = cookie; 1253 error = bus_generic_teardown_intr(dev, child, vec, 1254 sds->sds_cookie); 1255 if (error == 0) 1256 free(sds, M_DEVBUF); 1257 return (error); 1258 } 1259 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1260} 1261 1262static struct resource * 1263schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1264 u_long start, u_long end, u_long count, u_int flags) 1265{ 1266 struct schizo_softc *sc; 1267 struct resource *rv; 1268 struct rman *rm; 1269 bus_space_tag_t bt; 1270 bus_space_handle_t bh; 1271 int needactivate = flags & RF_ACTIVE; 1272 1273 flags &= ~RF_ACTIVE; 1274 1275 sc = device_get_softc(bus); 1276 if (type == SYS_RES_IRQ) { 1277 /* 1278 * XXX: Don't accept blank ranges for now, only single 1279 * interrupts. The other case should not happen with 1280 * the MI PCI code... 1281 * XXX: This may return a resource that is out of the 1282 * range that was specified. Is this correct...? 1283 */ 1284 if (start != end) 1285 panic("%s: XXX: interrupt range", __func__); 1286 start = end = INTMAP_VEC(sc->sc_ign, end); 1287 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1288 rid, start, end, count, flags)); 1289 } 1290 switch (type) { 1291 case SYS_RES_MEMORY: 1292 rm = &sc->sc_pci_mem_rman; 1293 bt = sc->sc_pci_memt; 1294 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1295 break; 1296 case SYS_RES_IOPORT: 1297 rm = &sc->sc_pci_io_rman; 1298 bt = sc->sc_pci_iot; 1299 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1300 break; 1301 default: 1302 return (NULL); 1303 /* NOTREACHED */ 1304 } 1305 1306 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1307 if (rv == NULL) 1308 return (NULL); 1309 rman_set_rid(rv, *rid); 1310 bh += rman_get_start(rv); 1311 rman_set_bustag(rv, bt); 1312 rman_set_bushandle(rv, bh); 1313 1314 if (needactivate) { 1315 if (bus_activate_resource(child, type, *rid, rv)) { 1316 rman_release_resource(rv); 1317 return (NULL); 1318 } 1319 } 1320 return (rv); 1321} 1322 1323static int 1324schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1325 struct resource *r) 1326{ 1327 void *p; 1328 int error; 1329 1330 if (type == SYS_RES_IRQ) 1331 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1332 type, rid, r)); 1333 if (type == SYS_RES_MEMORY) { 1334 /* 1335 * Need to memory-map the device space, as some drivers 1336 * depend on the virtual address being set and usable. 1337 */ 1338 error = sparc64_bus_mem_map(rman_get_bustag(r), 1339 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1340 if (error != 0) 1341 return (error); 1342 rman_set_virtual(r, p); 1343 } 1344 return (rman_activate_resource(r)); 1345} 1346 1347static int 1348schizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1349 struct resource *r) 1350{ 1351 1352 if (type == SYS_RES_IRQ) 1353 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1354 type, rid, r)); 1355 if (type == SYS_RES_MEMORY) { 1356 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1357 rman_set_virtual(r, NULL); 1358 } 1359 return (rman_deactivate_resource(r)); 1360} 1361 1362static int 1363schizo_release_resource(device_t bus, device_t child, int type, int rid, 1364 struct resource *r) 1365{ 1366 int error; 1367 1368 if (type == SYS_RES_IRQ) 1369 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1370 type, rid, r)); 1371 if (rman_get_flags(r) & RF_ACTIVE) { 1372 error = bus_deactivate_resource(child, type, rid, r); 1373 if (error) 1374 return (error); 1375 } 1376 return (rman_release_resource(r)); 1377} 1378 1379static bus_dma_tag_t 1380schizo_get_dma_tag(device_t bus, device_t child) 1381{ 1382 struct schizo_softc *sc; 1383 1384 sc = device_get_softc(bus); 1385 return (sc->sc_pci_dmat); 1386} 1387 1388static phandle_t 1389schizo_get_node(device_t bus, device_t dev) 1390{ 1391 struct schizo_softc *sc; 1392 1393 sc = device_get_softc(bus); 1394 /* We only have one child, the PCI bus, which needs our own node. */ 1395 return (sc->sc_node); 1396} 1397 1398static bus_space_tag_t 1399schizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1400{ 1401 bus_space_tag_t bt; 1402 1403 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1404 M_NOWAIT | M_ZERO); 1405 if (bt == NULL) 1406 panic("%s: out of memory", __func__); 1407 1408 bt->bst_cookie = sc; 1409 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1410 bt->bst_type = type; 1411 return (bt); 1412} 1413 1414static u_int 1415schizo_get_timecount(struct timecounter *tc) 1416{ 1417 struct schizo_softc *sc; 1418 1419 sc = tc->tc_priv; 1420 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1421 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1422} 1423