schizo.c revision 185133
1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4183423Smarius * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 185133 2008-11-20 18:44:09Z marius $"); 36183423Smarius 37183423Smarius/* 38183423Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39183423Smarius * PCI 2.2 bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55185133Smarius#include <sys/time.h> 56183423Smarius#include <sys/timetc.h> 57183423Smarius 58183423Smarius#include <dev/ofw/ofw_bus.h> 59183423Smarius#include <dev/ofw/ofw_pci.h> 60183423Smarius#include <dev/ofw/openfirm.h> 61183423Smarius 62183423Smarius#include <machine/bus.h> 63183423Smarius#include <machine/bus_common.h> 64183423Smarius#include <machine/bus_private.h> 65183423Smarius#include <machine/fsr.h> 66183423Smarius#include <machine/iommureg.h> 67183423Smarius#include <machine/iommuvar.h> 68183423Smarius#include <machine/ofw_bus.h> 69183423Smarius#include <machine/resource.h> 70183423Smarius 71183423Smarius#include <dev/pci/pcireg.h> 72183423Smarius#include <dev/pci/pcivar.h> 73183423Smarius 74183423Smarius#include <sparc64/pci/ofw_pci.h> 75183423Smarius#include <sparc64/pci/schizoreg.h> 76183423Smarius#include <sparc64/pci/schizovar.h> 77183423Smarius 78183423Smarius#include "pcib_if.h" 79183423Smarius 80183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 81183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82183423Smarius driver_filter_t); 83185133Smariusstatic driver_filter_t schizo_dma_sync_stub; 84185133Smariusstatic driver_filter_t ichip_dma_sync_stub; 85183423Smariusstatic void schizo_intr_enable(void *); 86183423Smariusstatic void schizo_intr_disable(void *); 87183423Smariusstatic void schizo_intr_assign(void *); 88183423Smariusstatic void schizo_intr_clear(void *); 89185133Smariusstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 90183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 91183423Smarius bus_addr_t *, bus_addr_t *); 92183423Smariusstatic bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 93183423Smariusstatic timecounter_get_t schizo_get_timecount; 94183423Smarius 95183423Smarius/* Interrupt handlers */ 96183423Smariusstatic driver_filter_t schizo_pci_bus; 97183423Smariusstatic driver_filter_t schizo_ue; 98183423Smariusstatic driver_filter_t schizo_ce; 99183423Smariusstatic driver_filter_t schizo_host_bus; 100185133Smariusstatic driver_filter_t schizo_cdma; 101183423Smarius 102183423Smarius/* IOMMU support */ 103183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 104183423Smarius 105183423Smarius/* 106183423Smarius * Methods 107183423Smarius */ 108183423Smariusstatic device_probe_t schizo_probe; 109183423Smariusstatic device_attach_t schizo_attach; 110183423Smariusstatic bus_read_ivar_t schizo_read_ivar; 111183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 112183423Smariusstatic bus_teardown_intr_t schizo_teardown_intr; 113183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 114183423Smariusstatic bus_activate_resource_t schizo_activate_resource; 115183423Smariusstatic bus_deactivate_resource_t schizo_deactivate_resource; 116183423Smariusstatic bus_release_resource_t schizo_release_resource; 117183423Smariusstatic bus_get_dma_tag_t schizo_get_dma_tag; 118183423Smariusstatic pcib_maxslots_t schizo_maxslots; 119183423Smariusstatic pcib_read_config_t schizo_read_config; 120183423Smariusstatic pcib_write_config_t schizo_write_config; 121183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 122183423Smariusstatic ofw_bus_get_node_t schizo_get_node; 123183423Smarius 124183423Smariusstatic device_method_t schizo_methods[] = { 125183423Smarius /* Device interface */ 126183423Smarius DEVMETHOD(device_probe, schizo_probe), 127183423Smarius DEVMETHOD(device_attach, schizo_attach), 128183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 129183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 130183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 131183423Smarius 132183423Smarius /* Bus interface */ 133183423Smarius DEVMETHOD(bus_print_child, bus_generic_print_child), 134183423Smarius DEVMETHOD(bus_read_ivar, schizo_read_ivar), 135183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 136183423Smarius DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 137183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 138183423Smarius DEVMETHOD(bus_activate_resource, schizo_activate_resource), 139183423Smarius DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 140183423Smarius DEVMETHOD(bus_release_resource, schizo_release_resource), 141183423Smarius DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 142183423Smarius 143183423Smarius /* pcib interface */ 144183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 145183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 146183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 147183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 148183423Smarius 149183423Smarius /* ofw_bus interface */ 150183423Smarius DEVMETHOD(ofw_bus_get_node, schizo_get_node), 151183423Smarius 152183423Smarius { 0, 0 } 153183423Smarius}; 154183423Smarius 155183423Smariusstatic devclass_t schizo_devclass; 156183423Smarius 157183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 158183423Smarius sizeof(struct schizo_softc)); 159183423SmariusDRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 160183423Smarius 161183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 162183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 163183423Smarius 164183423Smariusstatic const struct intr_controller schizo_ic = { 165183423Smarius schizo_intr_enable, 166183423Smarius schizo_intr_disable, 167183423Smarius schizo_intr_assign, 168183423Smarius schizo_intr_clear 169183423Smarius}; 170183423Smarius 171183423Smariusstruct schizo_icarg { 172183423Smarius struct schizo_softc *sica_sc; 173183423Smarius bus_addr_t sica_map; 174183423Smarius bus_addr_t sica_clr; 175183423Smarius}; 176183423Smarius 177185133Smariusstruct schizo_dma_sync { 178183423Smarius struct schizo_softc *sds_sc; 179183423Smarius driver_filter_t *sds_handler; 180183423Smarius void *sds_arg; 181183423Smarius void *sds_cookie; 182183423Smarius uint64_t sds_syncval; 183185133Smarius device_t sds_ppb; /* farest PCI-PCI bridge */ 184185133Smarius uint8_t sds_bus; /* bus of farest PCI device */ 185185133Smarius uint8_t sds_slot; /* slot of farest PCI device */ 186185133Smarius uint8_t sds_func; /* func. of farest PCI device */ 187183423Smarius}; 188183423Smarius 189183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 190183423Smarius 191183423Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 192183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 193183423Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 194183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 195183423Smarius 196183423Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 197183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 198183423Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 199183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 200183423Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 201183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 202183423Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 203183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 204183423Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 205183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 206183423Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 207183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 208183423Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 209183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 210183423Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 211183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 212183423Smarius 213183423Smarius#define OFW_PCI_TYPE "pci" 214183423Smarius 215183423Smariusstruct schizo_desc { 216183423Smarius const char *sd_string; 217183423Smarius int sd_mode; 218183423Smarius const char *sd_name; 219183423Smarius}; 220183423Smarius 221185133Smariusstatic const struct schizo_desc const schizo_compats[] = { 222183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 223183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 224183423Smarius { NULL, 0, NULL } 225183423Smarius}; 226183423Smarius 227183423Smariusstatic const struct schizo_desc * 228183423Smariusschizo_get_desc(device_t dev) 229183423Smarius{ 230183423Smarius const struct schizo_desc *desc; 231183423Smarius const char *compat; 232183423Smarius 233183423Smarius compat = ofw_bus_get_compat(dev); 234183423Smarius if (compat == NULL) 235183423Smarius return (NULL); 236183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 237183423Smarius if (strcmp(desc->sd_string, compat) == 0) 238183423Smarius return (desc); 239183423Smarius return (NULL); 240183423Smarius} 241183423Smarius 242183423Smariusstatic int 243183423Smariusschizo_probe(device_t dev) 244183423Smarius{ 245183423Smarius const char *dtype; 246183423Smarius 247183423Smarius dtype = ofw_bus_get_type(dev); 248183423Smarius if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 249183423Smarius schizo_get_desc(dev) != NULL) { 250183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 251183423Smarius return (0); 252183423Smarius } 253183423Smarius return (ENXIO); 254183423Smarius} 255183423Smarius 256183423Smariusstatic int 257183423Smariusschizo_attach(device_t dev) 258183423Smarius{ 259183423Smarius struct ofw_pci_ranges *range; 260183423Smarius const struct schizo_desc *desc; 261183423Smarius struct schizo_softc *asc, *sc, *osc; 262183423Smarius struct timecounter *tc; 263183423Smarius uint64_t ino_bitmap, reg; 264183423Smarius phandle_t node; 265183423Smarius uint32_t prop, prop_array[2]; 266183423Smarius int i, mode, n, nrange, rid, tsbsize; 267183423Smarius 268183423Smarius sc = device_get_softc(dev); 269183423Smarius node = ofw_bus_get_node(dev); 270183423Smarius desc = schizo_get_desc(dev); 271183423Smarius mode = desc->sd_mode; 272183423Smarius 273183423Smarius sc->sc_dev = dev; 274183423Smarius sc->sc_node = node; 275183423Smarius sc->sc_mode = mode; 276185133Smarius sc->sc_flags = 0; 277183423Smarius 278183423Smarius /* 279183423Smarius * The Schizo has three register banks: 280183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 281183423Smarius * shared with the UPA64s interrupt mapping register banks 282183423Smarius * (1) shared Schizo controller configuration and status registers 283183423Smarius * (2) per-PBM PCI configuration space 284183423Smarius * 285183423Smarius * The Tomatillo has four register banks: 286183423Smarius * (0) per-PBM PCI configuration and status registers 287183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 288183423Smarius * machines having the `jbusppm' device shared with its Estar 289183423Smarius * register bank for bus A 290183423Smarius * (2) per-PBM PCI configuration space 291183423Smarius * (3) per-PBM interrupt concentrator registers 292183423Smarius */ 293183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 294183423Smarius 20) & 1; 295183423Smarius for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 296183423Smarius n++) { 297183423Smarius rid = n; 298183423Smarius sc->sc_mem_res[n] = bus_alloc_resource_any(dev, 299183423Smarius SYS_RES_MEMORY, &rid, 300183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 301183423Smarius n == STX_PCI) || n == STX_CTRL)) || 302183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 303183423Smarius n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 304183423Smarius if (sc->sc_mem_res[n] == NULL) 305183423Smarius panic("%s: could not allocate register bank %d", 306183423Smarius __func__, n); 307183423Smarius } 308183423Smarius 309183423Smarius /* 310183423Smarius * Match other Schizos that are already configured against 311183423Smarius * the controller base physical address. This will be the 312183423Smarius * same for a pair of devices that share register space. 313183423Smarius */ 314183423Smarius osc = NULL; 315183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 316183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 317183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 318183423Smarius /* Found partner. */ 319183423Smarius osc = asc; 320183423Smarius break; 321183423Smarius } 322183423Smarius } 323183423Smarius if (osc == NULL) { 324183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 325183423Smarius M_NOWAIT | M_ZERO); 326183423Smarius if (sc->sc_mtx == NULL) 327183423Smarius panic("%s: could not malloc mutex", __func__); 328183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 329183423Smarius } else { 330185133Smarius if (sc->sc_mode != SCHIZO_MODE_SCZ) 331185133Smarius panic("%s: no partner expected", __func__); 332183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 333183423Smarius panic("%s: mutex not initialized", __func__); 334183423Smarius sc->sc_mtx = osc->sc_mtx; 335183423Smarius } 336183423Smarius 337183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 338183423Smarius panic("%s: could not determine IGN", __func__); 339183423Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1) 340183423Smarius panic("%s: could not determine version", __func__); 341183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 342183423Smarius prop = 33000000; 343183423Smarius 344183423Smarius device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 345183423Smarius desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 346183423Smarius prop / 1000 / 1000); 347183423Smarius 348183423Smarius /* Set up the PCI interrupt retry timer. */ 349183423Smarius#ifdef SCHIZO_DEBUG 350183423Smarius device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 351183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 352183423Smarius#endif 353183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 354183423Smarius 355183423Smarius /* Set up the PCI control register. */ 356183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 357183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 358183423Smarius STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 359183423Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 360183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 361183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 362183423Smarius if (mode == SCHIZO_MODE_TOM) { 363183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 364183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 365183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 366183423Smarius else 367183423Smarius reg |= STX_PCI_CTRL_PTO; 368183423Smarius } 369183423Smarius#ifdef SCHIZO_DEBUG 370183423Smarius device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 371183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 372183423Smarius (unsigned long long)reg); 373183423Smarius#endif 374183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 375183423Smarius 376183423Smarius /* Set up the PCI diagnostic register. */ 377183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 378183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 379183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 380183423Smarius#ifdef SCHIZO_DEBUG 381183423Smarius device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 382183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 383183423Smarius (unsigned long long)reg); 384183423Smarius#endif 385183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 386183423Smarius 387183423Smarius /* 388183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 389183423Smarius * Jalapeno bug). 390183423Smarius */ 391183423Smarius if (mode == SCHIZO_MODE_TOM) 392183423Smarius SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 393183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 394183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 395183423Smarius 396183423Smarius /* 397183423Smarius * Hunt through all the interrupt mapping regs and register 398183423Smarius * the interrupt controller for our interrupt vectors. This 399183423Smarius * is complicated by the fact that a pair of Schizo PBMs 400183423Smarius * share one IGN. 401183423Smarius */ 402183423Smarius n = OF_getprop(node, "ino-bitmap", (void *)prop_array, 403183423Smarius sizeof(prop_array)); 404183423Smarius if (n == -1) 405183423Smarius panic("%s: could not get ino-bitmap", __func__); 406183423Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 407183423Smarius for (n = 0; n <= STX_MAX_INO; n++) { 408183423Smarius if ((ino_bitmap & (1ULL << n)) == 0) 409183423Smarius continue; 410183423Smarius if (n == STX_FB0_INO || n == STX_FB1_INO) 411183423Smarius /* Leave for upa(4). */ 412183423Smarius continue; 413185133Smarius i = schizo_intr_register(sc, n); 414185133Smarius if (i != 0) 415183423Smarius panic("%s: could not register interrupt controller " 416185133Smarius "for INO %d (%d)", __func__, n, i); 417183423Smarius } 418183423Smarius 419183423Smarius /* 420183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 421183423Smarius * mode as timecounter. Unfortunately, this is broken with at 422183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 423183423Smarius * 1500, which apparently actually count some different event at 424183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 425183423Smarius * power mode). Besides, one counter seems to be shared by a 426183423Smarius * "pair" of Tomatillos, too. 427183423Smarius */ 428183423Smarius if (sc->sc_half == 0) { 429183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 430183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 431183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 432183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 433183423Smarius if (tc == NULL) 434183423Smarius panic("%s: could not malloc timecounter", __func__); 435183423Smarius tc->tc_get_timecount = schizo_get_timecount; 436183423Smarius tc->tc_poll_pps = NULL; 437183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 438183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 439183423Smarius sizeof(prop)) == -1) 440183423Smarius panic("%s: could not determine clock frequency", 441183423Smarius __func__); 442183423Smarius tc->tc_frequency = prop; 443183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 444183423Smarius if (mode == SCHIZO_MODE_SCZ) 445183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 446183423Smarius else 447183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 448183423Smarius tc->tc_priv = sc; 449183423Smarius tc_init(tc); 450183423Smarius } 451183423Smarius 452183423Smarius /* Set up the IOMMU. Both Schizo and Tomatillo have one per PBM. */ 453183423Smarius sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 454183423Smarius sc->sc_is.is_sb[0] = 0; 455183423Smarius sc->sc_is.is_sb[1] = 0; 456185133Smarius#ifdef notyet 457183423Smarius if (OF_getproplen(node, "no-streaming-cache") < 0) 458183423Smarius sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 459185133Smarius#endif 460183423Smarius 461183423Smarius#define TSBCASE(x) \ 462183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 463183423Smarius tsbsize = (x); \ 464183423Smarius break; \ 465183423Smarius 466183423Smarius n = OF_getprop(node, "virtual-dma", (void *)prop_array, 467183423Smarius sizeof(prop_array)); 468183423Smarius if (n == -1 || n != sizeof(prop_array)) 469183423Smarius schizo_iommu_init(sc, 7, -1); 470183423Smarius else { 471183423Smarius switch (prop_array[1]) { 472183423Smarius TSBCASE(1); 473183423Smarius TSBCASE(2); 474183423Smarius TSBCASE(3); 475183423Smarius TSBCASE(4); 476183423Smarius TSBCASE(5); 477183423Smarius TSBCASE(6); 478183423Smarius TSBCASE(7); 479183423Smarius TSBCASE(8); 480183423Smarius default: 481183423Smarius panic("%s: unsupported DVMA size 0x%x", 482183423Smarius __func__, prop_array[1]); 483183423Smarius /* NOTREACHED */ 484183423Smarius } 485183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 486183423Smarius } 487185133Smarius 488183423Smarius#undef TSBCASE 489183423Smarius 490183423Smarius /* Initialize memory and I/O rmans. */ 491183423Smarius sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 492183423Smarius sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 493183423Smarius if (rman_init(&sc->sc_pci_io_rman) != 0 || 494183423Smarius rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 495183423Smarius panic("%s: failed to set up I/O rman", __func__); 496183423Smarius sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 497183423Smarius sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 498183423Smarius if (rman_init(&sc->sc_pci_mem_rman) != 0 || 499183423Smarius rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 500183423Smarius panic("%s: failed to set up memory rman", __func__); 501183423Smarius 502183423Smarius nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 503183423Smarius (void **)&range); 504183423Smarius /* 505183423Smarius * Make sure that the expected ranges are present. The 506183423Smarius * OFW_PCI_CS_MEM64 one is not currently used though. 507183423Smarius */ 508183423Smarius if (nrange != STX_NRANGE) 509183423Smarius panic("%s: unsupported number of ranges", __func__); 510183423Smarius /* 511183423Smarius * Find the addresses of the various bus spaces. 512183423Smarius * There should not be multiple ones of one kind. 513183423Smarius * The physical start addresses of the ranges are the configuration, 514183423Smarius * memory and I/O handles. 515183423Smarius */ 516183423Smarius for (n = 0; n < STX_NRANGE; n++) { 517183423Smarius i = OFW_PCI_RANGE_CS(&range[n]); 518183423Smarius if (sc->sc_pci_bh[i] != 0) 519183423Smarius panic("%s: duplicate range for space %d", __func__, i); 520183423Smarius sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 521183423Smarius } 522183423Smarius free(range, M_OFWPROP); 523183423Smarius 524183423Smarius /* Register the softc, this is needed for paired Schizos. */ 525183423Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 526183423Smarius 527183423Smarius /* Allocate our tags. */ 528183423Smarius sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 529183423Smarius sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 530183423Smarius sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 531183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 532183423Smarius sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 533183423Smarius 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 534183423Smarius panic("%s: bus_dma_tag_create failed", __func__); 535183423Smarius /* Customize the tag. */ 536183423Smarius sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 537183423Smarius sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 538183423Smarius 539183423Smarius /* 540183423Smarius * Get the bus range from the firmware. 541183423Smarius * NB: Tomatillos don't support PCI bus reenumeration. 542183423Smarius */ 543183423Smarius n = OF_getprop(node, "bus-range", (void *)prop_array, 544183423Smarius sizeof(prop_array)); 545183423Smarius if (n == -1) 546183423Smarius panic("%s: could not get bus-range", __func__); 547183423Smarius if (n != sizeof(prop_array)) 548183423Smarius panic("%s: broken bus-range (%d)", __func__, n); 549183423Smarius if (bootverbose) 550183423Smarius device_printf(dev, "bus range %u to %u; PCI bus %d\n", 551183423Smarius prop_array[0], prop_array[1], prop_array[0]); 552183423Smarius sc->sc_pci_secbus = prop_array[0]; 553183423Smarius 554183423Smarius /* Clear any pending PCI error bits. */ 555183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 556183423Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 557183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 558183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 559183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 560183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 561183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 562183423Smarius 563183423Smarius /* 564183423Smarius * Establish handlers for interesting interrupts... 565183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 566183423Smarius * bus error interrupts for one PBM can be routed to the other 567183423Smarius * PBM though we obviously need to use the softc of the former 568183423Smarius * as the argument for the interrupt handler and the softc of 569183423Smarius * the latter as the argument for the interrupt controller. 570183423Smarius */ 571183423Smarius if (sc->sc_half == 0) { 572183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 573183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 574183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 575183423Smarius sica_sc == osc)) 576183423Smarius /* 577183423Smarius * We are the driver for PBM A and either also 578183423Smarius * registered the interrupt controller for us or 579183423Smarius * the driver for PBM B has probed first and 580183423Smarius * registered it for us. 581183423Smarius */ 582183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 583183423Smarius schizo_pci_bus); 584183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 585183423Smarius osc != NULL) 586183423Smarius /* 587183423Smarius * We are the driver for PBM A but registered 588183423Smarius * the interrupt controller for PBM B, i.e. the 589183423Smarius * driver for PBM B attached first but couldn't 590183423Smarius * set up a handler for PBM B. 591183423Smarius */ 592183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 593183423Smarius schizo_pci_bus); 594183423Smarius } else { 595183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 596183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 597183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 598183423Smarius sica_sc == osc)) 599183423Smarius /* 600183423Smarius * We are the driver for PBM B and either also 601183423Smarius * registered the interrupt controller for us or 602183423Smarius * the driver for PBM A has probed first and 603183423Smarius * registered it for us. 604183423Smarius */ 605183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 606183423Smarius schizo_pci_bus); 607183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 608183423Smarius osc != NULL) 609183423Smarius /* 610183423Smarius * We are the driver for PBM B but registered 611183423Smarius * the interrupt controller for PBM A, i.e. the 612183423Smarius * driver for PBM A attached first but couldn't 613183423Smarius * set up a handler for PBM A. 614183423Smarius */ 615183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 616183423Smarius schizo_pci_bus); 617183423Smarius } 618183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 619183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 620183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 621183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 622183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 623183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 624183423Smarius 625183423Smarius /* 626185133Smarius * According to the Schizo Errata I-13, consistent DMA flushing/ 627185133Smarius * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 628185133Smarius * so we can't use it and need to live with the consequences. 629185133Smarius * With Schizo version >= 5, CDMA flushing/syncing is usable 630185133Smarius * but requires the the workaround described in Schizo Errata 631185133Smarius * I-23. With Tomatillo and XMITS, CDMA flushing/syncing works 632185133Smarius * as expected, Tomatillo version <= 4 (i.e. revision <= 2.3) 633185133Smarius * bridges additionally require a block store after a write to 634185133Smarius * TOMXMS_PCI_DMA_SYNC_PEND though. 635185133Smarius */ 636185133Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 637185133Smarius sc->sc_mode == SCHIZO_MODE_TOM || sc->sc_mode == SCHIZO_MODE_XMS) { 638185133Smarius sc->sc_flags |= SCHIZO_FLAGS_CDMA; 639185133Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) { 640185133Smarius n = STX_CDMA_A_INO + sc->sc_half; 641185133Smarius if (bus_set_resource(dev, SYS_RES_IRQ, 5, 642185133Smarius INTMAP_VEC(sc->sc_ign, n), 1) != 0) 643185133Smarius panic("%s: failed to add CDMA interrupt", 644185133Smarius __func__); 645185133Smarius i = schizo_intr_register(sc, n); 646185133Smarius if (i != 0) 647185133Smarius panic("%s: could not register interrupt " 648185133Smarius "controller for CDMA (%d)", __func__, i); 649185133Smarius (void)schizo_get_intrmap(sc, n, NULL, 650185133Smarius &sc->sc_cdma_clr); 651185133Smarius sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 652185133Smarius schizo_set_intr(sc, 5, n, schizo_cdma); 653185133Smarius } 654185133Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 655185133Smarius sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 656185133Smarius } 657185133Smarius 658185133Smarius /* 659183423Smarius * Set the latency timer register as this isn't always done by the 660183423Smarius * firmware. 661183423Smarius */ 662183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 663183423Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 664183423Smarius 665183423Smarius ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 666183423Smarius 667183423Smarius device_add_child(dev, "pci", -1); 668183423Smarius return (bus_generic_attach(dev)); 669183423Smarius} 670183423Smarius 671183423Smariusstatic void 672183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 673183423Smarius driver_filter_t handler) 674183423Smarius{ 675183423Smarius u_long vec; 676183423Smarius int rid; 677183423Smarius 678183423Smarius rid = index; 679183423Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 680183423Smarius &rid, RF_ACTIVE); 681183423Smarius if (sc->sc_irq_res[index] == NULL || 682183423Smarius INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 683183423Smarius INTINO(vec) != ino || 684183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 685185133Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 686185133Smarius INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 687185133Smarius &sc->sc_ihand[index]) != 0) 688183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 689183423Smarius} 690183423Smarius 691183423Smariusstatic int 692185133Smariusschizo_intr_register(struct schizo_softc *sc, u_int ino) 693185133Smarius{ 694185133Smarius struct schizo_icarg *sica; 695185133Smarius bus_addr_t intrclr, intrmap; 696185133Smarius int error; 697185133Smarius 698185133Smarius if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 699185133Smarius return (ENXIO); 700185133Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 701185133Smarius if (sica == NULL) 702185133Smarius return (ENOMEM); 703185133Smarius sica->sica_sc = sc; 704185133Smarius sica->sica_map = intrmap; 705185133Smarius sica->sica_clr = intrclr; 706185133Smarius#ifdef SCHIZO_DEBUG 707185133Smarius device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 708185133Smarius ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 709185133Smarius (u_long)intrclr); 710185133Smarius#endif 711185133Smarius error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 712185133Smarius &schizo_ic, sica)); 713185133Smarius if (error != 0) 714185133Smarius free(sica, M_DEVBUF); 715185133Smarius return (error); 716185133Smarius} 717185133Smarius 718185133Smariusstatic int 719183423Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr, 720183423Smarius bus_addr_t *intrclrptr) 721183423Smarius{ 722183423Smarius bus_addr_t intrclr, intrmap; 723183423Smarius uint64_t mr; 724183423Smarius 725183423Smarius /* 726183423Smarius * XXX we only look for INOs rather than INRs since the firmware 727183423Smarius * may not provide the IGN and the IGN is constant for all devices 728183423Smarius * on that PCI controller. 729183423Smarius */ 730183423Smarius 731183423Smarius if (ino > STX_MAX_INO) { 732183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 733183423Smarius ino); 734183423Smarius return (0); 735183423Smarius } 736183423Smarius 737183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 738183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 739183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 740183423Smarius if (INTINO(mr) != ino) { 741183423Smarius device_printf(sc->sc_dev, 742183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 743183423Smarius (int)INTINO(mr), ino); 744183423Smarius return (0); 745183423Smarius } 746183423Smarius 747183423Smarius if (intrmapptr != NULL) 748183423Smarius *intrmapptr = intrmap; 749183423Smarius if (intrclrptr != NULL) 750183423Smarius *intrclrptr = intrclr; 751183423Smarius return (1); 752183423Smarius} 753183423Smarius 754183423Smarius/* 755183423Smarius * Interrupt handlers 756183423Smarius */ 757183423Smariusstatic int 758183423Smariusschizo_pci_bus(void *arg) 759183423Smarius{ 760183423Smarius struct schizo_softc *sc = arg; 761183423Smarius uint64_t afar, afsr, csr, iommu; 762183423Smarius uint32_t status; 763183423Smarius 764183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 765183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 766183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 767183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 768183423Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 769183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 770183423Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 771183423Smarius if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 772183423Smarius goto clear_error; 773183423Smarius 774183423Smarius /* These are non-fatal if target abort was signaled. */ 775183423Smarius if ((status & PCIM_STATUS_STABORT) != 0 && 776183423Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) == 777183423Smarius TOM_PCI_IOMMU_INVALID_ERR || 778183423Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 779183423Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 780183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 781183423Smarius goto clear_error; 782183423Smarius } 783183423Smarius } 784183423Smarius 785183423Smarius panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 786183423Smarius "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 787183423Smarius 'A' + sc->sc_half, (unsigned long long)afar, 788183423Smarius (unsigned long long)afsr, (unsigned long long)csr, 789183423Smarius (unsigned long long)iommu, (unsigned long long)status); 790183423Smarius 791183423Smarius clear_error: 792183423Smarius if (bootverbose) 793183423Smarius device_printf(sc->sc_dev, 794183423Smarius "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 795183423Smarius "STATUS %#llx", 'A' + sc->sc_half, 796183423Smarius (unsigned long long)afar, (unsigned long long)afsr, 797183423Smarius (unsigned long long)csr, (unsigned long long)status); 798183423Smarius /* Clear the error bits that we caught. */ 799183423Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 800183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 801183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 802183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 803183423Smarius return (FILTER_HANDLED); 804183423Smarius} 805183423Smarius 806183423Smariusstatic int 807183423Smariusschizo_ue(void *arg) 808183423Smarius{ 809183423Smarius struct schizo_softc *sc = arg; 810183423Smarius uint64_t afar, afsr; 811183423Smarius int i; 812183423Smarius 813183423Smarius mtx_lock_spin(sc->sc_mtx); 814183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 815183423Smarius for (i = 0; i < 1000; i++) 816183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 817183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 818183423Smarius break; 819183423Smarius mtx_unlock_spin(sc->sc_mtx); 820183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 821183423Smarius device_get_name(sc->sc_dev), (unsigned long long)afar, 822183423Smarius (unsigned long long)afsr); 823183423Smarius return (FILTER_HANDLED); 824183423Smarius} 825183423Smarius 826183423Smariusstatic int 827183423Smariusschizo_ce(void *arg) 828183423Smarius{ 829183423Smarius struct schizo_softc *sc = arg; 830183423Smarius uint64_t afar, afsr; 831183423Smarius int i; 832183423Smarius 833183423Smarius mtx_lock_spin(sc->sc_mtx); 834183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 835183423Smarius for (i = 0; i < 1000; i++) 836183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 837183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 838183423Smarius break; 839183423Smarius device_printf(sc->sc_dev, 840183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 841183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 842183423Smarius /* Clear the error bits that we caught. */ 843183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 844183423Smarius mtx_unlock_spin(sc->sc_mtx); 845183423Smarius return (FILTER_HANDLED); 846183423Smarius} 847183423Smarius 848183423Smariusstatic int 849183423Smariusschizo_host_bus(void *arg) 850183423Smarius{ 851183423Smarius struct schizo_softc *sc = arg; 852183423Smarius uint64_t errlog; 853183423Smarius 854183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 855183423Smarius panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 856183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 857183423Smarius (unsigned long long)errlog); 858183423Smarius return (FILTER_HANDLED); 859183423Smarius} 860183423Smarius 861185133Smariusstatic int 862185133Smariusschizo_cdma(void *arg) 863185133Smarius{ 864185133Smarius struct schizo_softc *sc = arg; 865185133Smarius 866185133Smarius atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 867185133Smarius return (FILTER_HANDLED); 868185133Smarius} 869185133Smarius 870183423Smariusstatic void 871183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 872183423Smarius{ 873183423Smarius 874183423Smarius /* Punch in our copies. */ 875183423Smarius sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 876183423Smarius sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 877183423Smarius sc->sc_is.is_iommu = STX_PCI_IOMMU; 878183423Smarius sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 879183423Smarius sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 880183423Smarius sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 881183423Smarius sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 882183423Smarius sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 883183423Smarius 884183423Smarius iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 885183423Smarius dvmabase, 0); 886183423Smarius} 887183423Smarius 888183423Smariusstatic int 889183423Smariusschizo_maxslots(device_t dev) 890183423Smarius{ 891183423Smarius struct schizo_softc *sc; 892183423Smarius 893183423Smarius sc = device_get_softc(dev); 894183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 895183423Smarius return (sc->sc_half == 0 ? 4 : 6); 896183423Smarius 897183423Smarius /* XXX: is this correct? */ 898183423Smarius return (PCI_SLOTMAX); 899183423Smarius} 900183423Smarius 901183423Smariusstatic uint32_t 902183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 903183423Smarius int width) 904183423Smarius{ 905183423Smarius struct schizo_softc *sc; 906183423Smarius bus_space_handle_t bh; 907183423Smarius u_long offset = 0; 908183423Smarius uint32_t r, wrd; 909183423Smarius int i; 910183423Smarius uint16_t shrt; 911183423Smarius uint8_t byte; 912183423Smarius 913183423Smarius sc = device_get_softc(dev); 914183423Smarius 915183423Smarius /* 916183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 917183423Smarius */ 918183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 919183423Smarius slot == STX_CS_DEVICE && func == STX_CS_FUNC && 920183423Smarius reg + width > 0x80) 921183423Smarius return (0); 922183423Smarius 923183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 924183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 925183423Smarius switch (width) { 926183423Smarius case 1: 927183423Smarius i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 928183423Smarius r = byte; 929183423Smarius break; 930183423Smarius case 2: 931183423Smarius i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 932183423Smarius r = shrt; 933183423Smarius break; 934183423Smarius case 4: 935183423Smarius i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 936183423Smarius r = wrd; 937183423Smarius break; 938183423Smarius default: 939183423Smarius panic("%s: bad width", __func__); 940183423Smarius /* NOTREACHED */ 941183423Smarius } 942183423Smarius 943183423Smarius if (i) { 944183423Smarius#ifdef SCHIZO_DEBUG 945183423Smarius printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 946183423Smarius __func__, bus, slot, func, reg); 947183423Smarius#endif 948183423Smarius r = -1; 949183423Smarius } 950183423Smarius return (r); 951183423Smarius} 952183423Smarius 953183423Smariusstatic void 954183423Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 955183423Smarius uint32_t val, int width) 956183423Smarius{ 957183423Smarius struct schizo_softc *sc; 958183423Smarius bus_space_handle_t bh; 959183423Smarius u_long offset = 0; 960183423Smarius 961183423Smarius sc = device_get_softc(dev); 962183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 963183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 964183423Smarius switch (width) { 965183423Smarius case 1: 966183423Smarius bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 967183423Smarius break; 968183423Smarius case 2: 969183423Smarius bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 970183423Smarius break; 971183423Smarius case 4: 972183423Smarius bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 973183423Smarius break; 974183423Smarius default: 975183423Smarius panic("%s: bad width", __func__); 976183423Smarius /* NOTREACHED */ 977183423Smarius } 978183423Smarius} 979183423Smarius 980183423Smariusstatic int 981183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 982183423Smarius{ 983183423Smarius struct schizo_softc *sc; 984183423Smarius struct ofw_pci_register reg; 985183423Smarius ofw_pci_intr_t pintr, mintr; 986183423Smarius uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 987183423Smarius 988183423Smarius sc = device_get_softc(bridge); 989183423Smarius pintr = pin; 990183423Smarius if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 991183423Smarius sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 992183423Smarius return (mintr); 993183423Smarius 994183423Smarius device_printf(bridge, "could not route pin %d for device %d.%d\n", 995183423Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 996183423Smarius return (PCI_INVALID_IRQ); 997183423Smarius} 998183423Smarius 999183423Smariusstatic int 1000183423Smariusschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1001183423Smarius{ 1002183423Smarius struct schizo_softc *sc; 1003183423Smarius 1004183423Smarius sc = device_get_softc(dev); 1005183423Smarius switch (which) { 1006183423Smarius case PCIB_IVAR_DOMAIN: 1007183423Smarius *result = device_get_unit(dev); 1008183423Smarius return (0); 1009183423Smarius case PCIB_IVAR_BUS: 1010183423Smarius *result = sc->sc_pci_secbus; 1011183423Smarius return (0); 1012183423Smarius } 1013183423Smarius return (ENOENT); 1014183423Smarius} 1015183423Smarius 1016185133Smariusstatic int 1017185133Smariusschizo_dma_sync_stub(void *arg) 1018185133Smarius{ 1019185133Smarius struct timeval cur, end; 1020185133Smarius struct schizo_dma_sync *sds = arg; 1021185133Smarius struct schizo_softc *sc = sds->sds_sc; 1022185133Smarius uint32_t state; 1023185133Smarius 1024185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1025185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1026185133Smarius for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE, 1027185133Smarius SCHIZO_CDMA_STATE_PENDING) == 0;) 1028185133Smarius ; 1029185133Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1); 1030185133Smarius microuptime(&cur); 1031185133Smarius end.tv_sec = 1; 1032185133Smarius end.tv_usec = 0; 1033185133Smarius timevaladd(&end, &cur); 1034185133Smarius for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1035185133Smarius SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1036185133Smarius microuptime(&cur); 1037185133Smarius if (state != SCHIZO_CDMA_STATE_DONE) 1038185133Smarius panic("%s: DMA does not sync", __func__); 1039185133Smarius return (sds->sds_handler(sds->sds_arg)); 1040185133Smarius} 1041185133Smarius 1042183423Smarius#define VIS_BLOCKSIZE 64 1043183423Smarius 1044183423Smariusstatic int 1045185133Smariusichip_dma_sync_stub(void *arg) 1046183423Smarius{ 1047183423Smarius static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1048185133Smarius struct timeval cur, end; 1049185133Smarius struct schizo_dma_sync *sds = arg; 1050183423Smarius struct schizo_softc *sc = sds->sds_sc; 1051184428Smarius register_t reg, s; 1052183423Smarius 1053185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1054185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1055184428Smarius SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1056185133Smarius microuptime(&cur); 1057185133Smarius end.tv_sec = 1; 1058185133Smarius end.tv_usec = 0; 1059185133Smarius timevaladd(&end, &cur); 1060185133Smarius for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1061185133Smarius sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1062185133Smarius microuptime(&cur); 1063185133Smarius if ((reg & sds->sds_syncval) != 0) 1064185133Smarius panic("%s: DMA does not sync", __func__); 1065183423Smarius 1066185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1067184428Smarius s = intr_disable(); 1068183423Smarius reg = rd(fprs); 1069183423Smarius wr(fprs, reg | FPRS_FEF, 0); 1070184428Smarius __asm __volatile("stda %%f0, [%0] %1" 1071183423Smarius : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1072184428Smarius membar(Sync); 1073183423Smarius wr(fprs, reg, 0); 1074184428Smarius intr_restore(s); 1075183423Smarius } 1076183423Smarius return (sds->sds_handler(sds->sds_arg)); 1077183423Smarius} 1078183423Smarius 1079183423Smariusstatic void 1080183423Smariusschizo_intr_enable(void *arg) 1081183423Smarius{ 1082183423Smarius struct intr_vector *iv = arg; 1083183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1084183423Smarius 1085183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1086183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1087183423Smarius} 1088183423Smarius 1089183423Smariusstatic void 1090183423Smariusschizo_intr_disable(void *arg) 1091183423Smarius{ 1092183423Smarius struct intr_vector *iv = arg; 1093183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1094183423Smarius 1095183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1096183423Smarius} 1097183423Smarius 1098183423Smariusstatic void 1099183423Smariusschizo_intr_assign(void *arg) 1100183423Smarius{ 1101183423Smarius struct intr_vector *iv = arg; 1102183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1103183423Smarius 1104183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1105183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1106183423Smarius} 1107183423Smarius 1108183423Smariusstatic void 1109183423Smariusschizo_intr_clear(void *arg) 1110183423Smarius{ 1111183423Smarius struct intr_vector *iv = arg; 1112183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1113183423Smarius 1114183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0); 1115183423Smarius} 1116183423Smarius 1117183423Smariusstatic int 1118183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1119183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1120183423Smarius void **cookiep) 1121183423Smarius{ 1122185133Smarius devclass_t pci_devclass; 1123185133Smarius device_t cdev, pdev, pcidev; 1124185133Smarius struct schizo_dma_sync *sds; 1125183423Smarius struct schizo_softc *sc; 1126183423Smarius u_long vec; 1127185133Smarius int error, found; 1128183423Smarius 1129183423Smarius sc = device_get_softc(dev); 1130183423Smarius /* 1131183423Smarius * Make sure the vector is fully specified and we registered 1132183423Smarius * our interrupt controller for it. 1133183423Smarius */ 1134183423Smarius vec = rman_get_start(ires); 1135183423Smarius if (INTIGN(vec) != sc->sc_ign || 1136183423Smarius intr_vectors[vec].iv_ic != &schizo_ic) { 1137183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1138183423Smarius return (EINVAL); 1139183423Smarius } 1140183423Smarius 1141183423Smarius /* 1142185133Smarius * Install a a wrapper for CDMA flushing/syncing for devices 1143185133Smarius * behind PCI-PCI bridges if possible. 1144183423Smarius */ 1145185133Smarius pcidev = NULL; 1146185133Smarius found = 0; 1147185133Smarius pci_devclass = devclass_find("pci"); 1148185133Smarius for (cdev = child; cdev != dev; cdev = pdev) { 1149185133Smarius pdev = device_get_parent(cdev); 1150185133Smarius if (pcidev == NULL) { 1151185133Smarius if (device_get_devclass(pdev) != pci_devclass) 1152185133Smarius continue; 1153185133Smarius pcidev = cdev; 1154185133Smarius continue; 1155185133Smarius } 1156185133Smarius if (pci_get_class(cdev) == PCIC_BRIDGE && 1157185133Smarius pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1158185133Smarius found = 1; 1159185133Smarius } 1160185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1161183423Smarius sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1162183423Smarius if (sds == NULL) 1163183423Smarius return (ENOMEM); 1164185133Smarius if (found != 0 && pcidev != NULL) { 1165185133Smarius sds->sds_sc = sc; 1166185133Smarius sds->sds_arg = arg; 1167185133Smarius sds->sds_ppb = 1168185133Smarius device_get_parent(device_get_parent(pcidev)); 1169185133Smarius sds->sds_bus = pci_get_bus(pcidev); 1170185133Smarius sds->sds_slot = pci_get_slot(pcidev); 1171185133Smarius sds->sds_func = pci_get_function(pcidev); 1172185133Smarius sds->sds_syncval = 1ULL << INTINO(vec); 1173185133Smarius if (bootverbose) 1174185133Smarius device_printf(dev, "installed DMA sync " 1175185133Smarius "wrapper for device %d.%d on bus %d\n", 1176185133Smarius sds->sds_slot, sds->sds_func, 1177185133Smarius sds->sds_bus); 1178185133Smarius 1179185133Smarius#define DMA_SYNC_STUB \ 1180185133Smarius (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1181185133Smarius ichip_dma_sync_stub) 1182185133Smarius 1183185133Smarius if (intr == NULL) { 1184185133Smarius sds->sds_handler = filt; 1185185133Smarius error = bus_generic_setup_intr(dev, child, 1186185133Smarius ires, flags, DMA_SYNC_STUB, intr, sds, 1187185133Smarius cookiep); 1188185133Smarius } else { 1189185133Smarius sds->sds_handler = (driver_filter_t *)intr; 1190185133Smarius error = bus_generic_setup_intr(dev, child, 1191185133Smarius ires, flags, filt, (driver_intr_t *) 1192185133Smarius DMA_SYNC_STUB, sds, cookiep); 1193185133Smarius } 1194185133Smarius 1195185133Smarius#undef DMA_SYNC_STUB 1196185133Smarius 1197185133Smarius } else 1198183423Smarius error = bus_generic_setup_intr(dev, child, ires, 1199185133Smarius flags, filt, intr, arg, cookiep); 1200183423Smarius if (error != 0) { 1201183423Smarius free(sds, M_DEVBUF); 1202183423Smarius return (error); 1203183423Smarius } 1204183423Smarius sds->sds_cookie = *cookiep; 1205183423Smarius *cookiep = sds; 1206183423Smarius return (error); 1207185133Smarius } else if (found != 0) 1208185133Smarius device_printf(dev, "WARNING: using devices behind PCI-PCI " 1209185133Smarius "bridges may cause data corruption"); 1210183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1211183423Smarius arg, cookiep)); 1212183423Smarius} 1213183423Smarius 1214183423Smariusstatic int 1215183423Smariusschizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1216183423Smarius void *cookie) 1217183423Smarius{ 1218185133Smarius struct schizo_dma_sync *sds; 1219183423Smarius struct schizo_softc *sc; 1220183423Smarius int error; 1221183423Smarius 1222183423Smarius sc = device_get_softc(dev); 1223185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1224183423Smarius sds = cookie; 1225183423Smarius error = bus_generic_teardown_intr(dev, child, vec, 1226183423Smarius sds->sds_cookie); 1227183423Smarius if (error == 0) 1228183423Smarius free(sds, M_DEVBUF); 1229183423Smarius return (error); 1230183423Smarius } 1231183423Smarius return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1232183423Smarius} 1233183423Smarius 1234183423Smariusstatic struct resource * 1235183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1236183423Smarius u_long start, u_long end, u_long count, u_int flags) 1237183423Smarius{ 1238183423Smarius struct schizo_softc *sc; 1239183423Smarius struct resource *rv; 1240183423Smarius struct rman *rm; 1241183423Smarius bus_space_tag_t bt; 1242183423Smarius bus_space_handle_t bh; 1243183423Smarius int needactivate = flags & RF_ACTIVE; 1244183423Smarius 1245183423Smarius flags &= ~RF_ACTIVE; 1246183423Smarius 1247183423Smarius sc = device_get_softc(bus); 1248183423Smarius if (type == SYS_RES_IRQ) { 1249183423Smarius /* 1250183423Smarius * XXX: Don't accept blank ranges for now, only single 1251183423Smarius * interrupts. The other case should not happen with 1252183423Smarius * the MI PCI code... 1253183423Smarius * XXX: This may return a resource that is out of the 1254183423Smarius * range that was specified. Is this correct...? 1255183423Smarius */ 1256183423Smarius if (start != end) 1257183423Smarius panic("%s: XXX: interrupt range", __func__); 1258183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1259183423Smarius return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1260183423Smarius rid, start, end, count, flags)); 1261183423Smarius } 1262183423Smarius switch (type) { 1263183423Smarius case SYS_RES_MEMORY: 1264183423Smarius rm = &sc->sc_pci_mem_rman; 1265183423Smarius bt = sc->sc_pci_memt; 1266183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1267183423Smarius break; 1268183423Smarius case SYS_RES_IOPORT: 1269183423Smarius rm = &sc->sc_pci_io_rman; 1270183423Smarius bt = sc->sc_pci_iot; 1271183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1272183423Smarius break; 1273183423Smarius default: 1274183423Smarius return (NULL); 1275183423Smarius /* NOTREACHED */ 1276183423Smarius } 1277183423Smarius 1278183423Smarius rv = rman_reserve_resource(rm, start, end, count, flags, child); 1279183423Smarius if (rv == NULL) 1280183423Smarius return (NULL); 1281183423Smarius rman_set_rid(rv, *rid); 1282183423Smarius bh += rman_get_start(rv); 1283183423Smarius rman_set_bustag(rv, bt); 1284183423Smarius rman_set_bushandle(rv, bh); 1285183423Smarius 1286183423Smarius if (needactivate) { 1287183423Smarius if (bus_activate_resource(child, type, *rid, rv)) { 1288183423Smarius rman_release_resource(rv); 1289183423Smarius return (NULL); 1290183423Smarius } 1291183423Smarius } 1292183423Smarius return (rv); 1293183423Smarius} 1294183423Smarius 1295183423Smariusstatic int 1296183423Smariusschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1297183423Smarius struct resource *r) 1298183423Smarius{ 1299183423Smarius void *p; 1300183423Smarius int error; 1301183423Smarius 1302183423Smarius if (type == SYS_RES_IRQ) 1303183423Smarius return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1304183423Smarius type, rid, r)); 1305183423Smarius if (type == SYS_RES_MEMORY) { 1306183423Smarius /* 1307185133Smarius * Need to memory-map the device space, as some drivers 1308185133Smarius * depend on the virtual address being set and usable. 1309183423Smarius */ 1310183423Smarius error = sparc64_bus_mem_map(rman_get_bustag(r), 1311183423Smarius rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1312183423Smarius if (error != 0) 1313183423Smarius return (error); 1314183423Smarius rman_set_virtual(r, p); 1315183423Smarius } 1316183423Smarius return (rman_activate_resource(r)); 1317183423Smarius} 1318183423Smarius 1319183423Smariusstatic int 1320183423Smariusschizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1321183423Smarius struct resource *r) 1322183423Smarius{ 1323183423Smarius 1324183423Smarius if (type == SYS_RES_IRQ) 1325183423Smarius return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1326183423Smarius type, rid, r)); 1327183423Smarius if (type == SYS_RES_MEMORY) { 1328183423Smarius sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1329183423Smarius rman_set_virtual(r, NULL); 1330183423Smarius } 1331183423Smarius return (rman_deactivate_resource(r)); 1332183423Smarius} 1333183423Smarius 1334183423Smariusstatic int 1335183423Smariusschizo_release_resource(device_t bus, device_t child, int type, int rid, 1336183423Smarius struct resource *r) 1337183423Smarius{ 1338183423Smarius int error; 1339183423Smarius 1340183423Smarius if (type == SYS_RES_IRQ) 1341183423Smarius return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1342183423Smarius type, rid, r)); 1343183423Smarius if (rman_get_flags(r) & RF_ACTIVE) { 1344183423Smarius error = bus_deactivate_resource(child, type, rid, r); 1345183423Smarius if (error) 1346183423Smarius return (error); 1347183423Smarius } 1348183423Smarius return (rman_release_resource(r)); 1349183423Smarius} 1350183423Smarius 1351183423Smariusstatic bus_dma_tag_t 1352183423Smariusschizo_get_dma_tag(device_t bus, device_t child) 1353183423Smarius{ 1354183423Smarius struct schizo_softc *sc; 1355183423Smarius 1356183423Smarius sc = device_get_softc(bus); 1357183423Smarius return (sc->sc_pci_dmat); 1358183423Smarius} 1359183423Smarius 1360183423Smariusstatic phandle_t 1361183423Smariusschizo_get_node(device_t bus, device_t dev) 1362183423Smarius{ 1363183423Smarius struct schizo_softc *sc; 1364183423Smarius 1365183423Smarius sc = device_get_softc(bus); 1366183423Smarius /* We only have one child, the PCI bus, which needs our own node. */ 1367183423Smarius return (sc->sc_node); 1368183423Smarius} 1369183423Smarius 1370183423Smariusstatic bus_space_tag_t 1371183423Smariusschizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1372183423Smarius{ 1373183423Smarius bus_space_tag_t bt; 1374183423Smarius 1375183423Smarius bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1376183423Smarius M_NOWAIT | M_ZERO); 1377183423Smarius if (bt == NULL) 1378183423Smarius panic("%s: out of memory", __func__); 1379183423Smarius 1380183423Smarius bt->bst_cookie = sc; 1381183423Smarius bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1382183423Smarius bt->bst_type = type; 1383183423Smarius return (bt); 1384183423Smarius} 1385183423Smarius 1386183423Smariusstatic u_int 1387183423Smariusschizo_get_timecount(struct timecounter *tc) 1388183423Smarius{ 1389183423Smarius struct schizo_softc *sc; 1390183423Smarius 1391183423Smarius sc = tc->tc_priv; 1392183423Smarius return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1393183423Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1394183423Smarius} 1395