schizo.c revision 185133
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 185133 2008-11-20 18:44:09Z marius $"); 36 37/* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39 * PCI 2.2 bridges 40 */ 41 42#include "opt_ofw_pci.h" 43#include "opt_schizo.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/rman.h> 55#include <sys/time.h> 56#include <sys/timetc.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/fsr.h> 66#include <machine/iommureg.h> 67#include <machine/iommuvar.h> 68#include <machine/ofw_bus.h> 69#include <machine/resource.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/schizoreg.h> 76#include <sparc64/pci/schizovar.h> 77 78#include "pcib_if.h" 79 80static const struct schizo_desc *schizo_get_desc(device_t); 81static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82 driver_filter_t); 83static driver_filter_t schizo_dma_sync_stub; 84static driver_filter_t ichip_dma_sync_stub; 85static void schizo_intr_enable(void *); 86static void schizo_intr_disable(void *); 87static void schizo_intr_assign(void *); 88static void schizo_intr_clear(void *); 89static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 90static int schizo_get_intrmap(struct schizo_softc *, u_int, 91 bus_addr_t *, bus_addr_t *); 92static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 93static timecounter_get_t schizo_get_timecount; 94 95/* Interrupt handlers */ 96static driver_filter_t schizo_pci_bus; 97static driver_filter_t schizo_ue; 98static driver_filter_t schizo_ce; 99static driver_filter_t schizo_host_bus; 100static driver_filter_t schizo_cdma; 101 102/* IOMMU support */ 103static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 104 105/* 106 * Methods 107 */ 108static device_probe_t schizo_probe; 109static device_attach_t schizo_attach; 110static bus_read_ivar_t schizo_read_ivar; 111static bus_setup_intr_t schizo_setup_intr; 112static bus_teardown_intr_t schizo_teardown_intr; 113static bus_alloc_resource_t schizo_alloc_resource; 114static bus_activate_resource_t schizo_activate_resource; 115static bus_deactivate_resource_t schizo_deactivate_resource; 116static bus_release_resource_t schizo_release_resource; 117static bus_get_dma_tag_t schizo_get_dma_tag; 118static pcib_maxslots_t schizo_maxslots; 119static pcib_read_config_t schizo_read_config; 120static pcib_write_config_t schizo_write_config; 121static pcib_route_interrupt_t schizo_route_interrupt; 122static ofw_bus_get_node_t schizo_get_node; 123 124static device_method_t schizo_methods[] = { 125 /* Device interface */ 126 DEVMETHOD(device_probe, schizo_probe), 127 DEVMETHOD(device_attach, schizo_attach), 128 DEVMETHOD(device_shutdown, bus_generic_shutdown), 129 DEVMETHOD(device_suspend, bus_generic_suspend), 130 DEVMETHOD(device_resume, bus_generic_resume), 131 132 /* Bus interface */ 133 DEVMETHOD(bus_print_child, bus_generic_print_child), 134 DEVMETHOD(bus_read_ivar, schizo_read_ivar), 135 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 136 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 137 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 138 DEVMETHOD(bus_activate_resource, schizo_activate_resource), 139 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 140 DEVMETHOD(bus_release_resource, schizo_release_resource), 141 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 142 143 /* pcib interface */ 144 DEVMETHOD(pcib_maxslots, schizo_maxslots), 145 DEVMETHOD(pcib_read_config, schizo_read_config), 146 DEVMETHOD(pcib_write_config, schizo_write_config), 147 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 148 149 /* ofw_bus interface */ 150 DEVMETHOD(ofw_bus_get_node, schizo_get_node), 151 152 { 0, 0 } 153}; 154 155static devclass_t schizo_devclass; 156 157DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 158 sizeof(struct schizo_softc)); 159DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 160 161static SLIST_HEAD(, schizo_softc) schizo_softcs = 162 SLIST_HEAD_INITIALIZER(schizo_softcs); 163 164static const struct intr_controller schizo_ic = { 165 schizo_intr_enable, 166 schizo_intr_disable, 167 schizo_intr_assign, 168 schizo_intr_clear 169}; 170 171struct schizo_icarg { 172 struct schizo_softc *sica_sc; 173 bus_addr_t sica_map; 174 bus_addr_t sica_clr; 175}; 176 177struct schizo_dma_sync { 178 struct schizo_softc *sds_sc; 179 driver_filter_t *sds_handler; 180 void *sds_arg; 181 void *sds_cookie; 182 uint64_t sds_syncval; 183 device_t sds_ppb; /* farest PCI-PCI bridge */ 184 uint8_t sds_bus; /* bus of farest PCI device */ 185 uint8_t sds_slot; /* slot of farest PCI device */ 186 uint8_t sds_func; /* func. of farest PCI device */ 187}; 188 189#define SCHIZO_PERF_CNT_QLTY 100 190 191#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 192 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 193#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 194 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 195 196#define SCHIZO_PCI_READ_8(sc, offs) \ 197 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 198#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 199 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 200#define SCHIZO_CTRL_READ_8(sc, offs) \ 201 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 202#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 203 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 204#define SCHIZO_PCICFG_READ_8(sc, offs) \ 205 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 206#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 207 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 208#define SCHIZO_ICON_READ_8(sc, offs) \ 209 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 210#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 211 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 212 213#define OFW_PCI_TYPE "pci" 214 215struct schizo_desc { 216 const char *sd_string; 217 int sd_mode; 218 const char *sd_name; 219}; 220 221static const struct schizo_desc const schizo_compats[] = { 222 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 223 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 224 { NULL, 0, NULL } 225}; 226 227static const struct schizo_desc * 228schizo_get_desc(device_t dev) 229{ 230 const struct schizo_desc *desc; 231 const char *compat; 232 233 compat = ofw_bus_get_compat(dev); 234 if (compat == NULL) 235 return (NULL); 236 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 237 if (strcmp(desc->sd_string, compat) == 0) 238 return (desc); 239 return (NULL); 240} 241 242static int 243schizo_probe(device_t dev) 244{ 245 const char *dtype; 246 247 dtype = ofw_bus_get_type(dev); 248 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 249 schizo_get_desc(dev) != NULL) { 250 device_set_desc(dev, "Sun Host-PCI bridge"); 251 return (0); 252 } 253 return (ENXIO); 254} 255 256static int 257schizo_attach(device_t dev) 258{ 259 struct ofw_pci_ranges *range; 260 const struct schizo_desc *desc; 261 struct schizo_softc *asc, *sc, *osc; 262 struct timecounter *tc; 263 uint64_t ino_bitmap, reg; 264 phandle_t node; 265 uint32_t prop, prop_array[2]; 266 int i, mode, n, nrange, rid, tsbsize; 267 268 sc = device_get_softc(dev); 269 node = ofw_bus_get_node(dev); 270 desc = schizo_get_desc(dev); 271 mode = desc->sd_mode; 272 273 sc->sc_dev = dev; 274 sc->sc_node = node; 275 sc->sc_mode = mode; 276 sc->sc_flags = 0; 277 278 /* 279 * The Schizo has three register banks: 280 * (0) per-PBM PCI configuration and status registers, but for bus B 281 * shared with the UPA64s interrupt mapping register banks 282 * (1) shared Schizo controller configuration and status registers 283 * (2) per-PBM PCI configuration space 284 * 285 * The Tomatillo has four register banks: 286 * (0) per-PBM PCI configuration and status registers 287 * (1) per-PBM Tomatillo controller configuration registers, but on 288 * machines having the `jbusppm' device shared with its Estar 289 * register bank for bus A 290 * (2) per-PBM PCI configuration space 291 * (3) per-PBM interrupt concentrator registers 292 */ 293 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 294 20) & 1; 295 for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 296 n++) { 297 rid = n; 298 sc->sc_mem_res[n] = bus_alloc_resource_any(dev, 299 SYS_RES_MEMORY, &rid, 300 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 301 n == STX_PCI) || n == STX_CTRL)) || 302 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 303 n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 304 if (sc->sc_mem_res[n] == NULL) 305 panic("%s: could not allocate register bank %d", 306 __func__, n); 307 } 308 309 /* 310 * Match other Schizos that are already configured against 311 * the controller base physical address. This will be the 312 * same for a pair of devices that share register space. 313 */ 314 osc = NULL; 315 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 316 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 317 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 318 /* Found partner. */ 319 osc = asc; 320 break; 321 } 322 } 323 if (osc == NULL) { 324 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 325 M_NOWAIT | M_ZERO); 326 if (sc->sc_mtx == NULL) 327 panic("%s: could not malloc mutex", __func__); 328 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 329 } else { 330 if (sc->sc_mode != SCHIZO_MODE_SCZ) 331 panic("%s: no partner expected", __func__); 332 if (mtx_initialized(osc->sc_mtx) == 0) 333 panic("%s: mutex not initialized", __func__); 334 sc->sc_mtx = osc->sc_mtx; 335 } 336 337 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 338 panic("%s: could not determine IGN", __func__); 339 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1) 340 panic("%s: could not determine version", __func__); 341 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 342 prop = 33000000; 343 344 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 345 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 346 prop / 1000 / 1000); 347 348 /* Set up the PCI interrupt retry timer. */ 349#ifdef SCHIZO_DEBUG 350 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 351 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 352#endif 353 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 354 355 /* Set up the PCI control register. */ 356 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 357 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 358 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 359 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 360 if (OF_getproplen(node, "no-bus-parking") < 0) 361 reg |= STX_PCI_CTRL_ARB_PARK; 362 if (mode == SCHIZO_MODE_TOM) { 363 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 364 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 365 reg |= TOM_PCI_CTRL_DTO_IEN; 366 else 367 reg |= STX_PCI_CTRL_PTO; 368 } 369#ifdef SCHIZO_DEBUG 370 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 371 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 372 (unsigned long long)reg); 373#endif 374 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 375 376 /* Set up the PCI diagnostic register. */ 377 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 378 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 379 STX_PCI_DIAG_INTRSYNC_DIS); 380#ifdef SCHIZO_DEBUG 381 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 382 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 383 (unsigned long long)reg); 384#endif 385 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 386 387 /* 388 * On Tomatillo clear the I/O prefetch lengths (workaround for a 389 * Jalapeno bug). 390 */ 391 if (mode == SCHIZO_MODE_TOM) 392 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 393 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 394 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 395 396 /* 397 * Hunt through all the interrupt mapping regs and register 398 * the interrupt controller for our interrupt vectors. This 399 * is complicated by the fact that a pair of Schizo PBMs 400 * share one IGN. 401 */ 402 n = OF_getprop(node, "ino-bitmap", (void *)prop_array, 403 sizeof(prop_array)); 404 if (n == -1) 405 panic("%s: could not get ino-bitmap", __func__); 406 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 407 for (n = 0; n <= STX_MAX_INO; n++) { 408 if ((ino_bitmap & (1ULL << n)) == 0) 409 continue; 410 if (n == STX_FB0_INO || n == STX_FB1_INO) 411 /* Leave for upa(4). */ 412 continue; 413 i = schizo_intr_register(sc, n); 414 if (i != 0) 415 panic("%s: could not register interrupt controller " 416 "for INO %d (%d)", __func__, n, i); 417 } 418 419 /* 420 * Setup Safari/JBus performance counter 0 in bus cycle counting 421 * mode as timecounter. Unfortunately, this is broken with at 422 * least the version 4 Tomatillos found in Fire V120 and Blade 423 * 1500, which apparently actually count some different event at 424 * ~0.5 and 3MHz respectively instead (also when running in full 425 * power mode). Besides, one counter seems to be shared by a 426 * "pair" of Tomatillos, too. 427 */ 428 if (sc->sc_half == 0) { 429 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 430 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 431 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 432 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 433 if (tc == NULL) 434 panic("%s: could not malloc timecounter", __func__); 435 tc->tc_get_timecount = schizo_get_timecount; 436 tc->tc_poll_pps = NULL; 437 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 438 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 439 sizeof(prop)) == -1) 440 panic("%s: could not determine clock frequency", 441 __func__); 442 tc->tc_frequency = prop; 443 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 444 if (mode == SCHIZO_MODE_SCZ) 445 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 446 else 447 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 448 tc->tc_priv = sc; 449 tc_init(tc); 450 } 451 452 /* Set up the IOMMU. Both Schizo and Tomatillo have one per PBM. */ 453 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 454 sc->sc_is.is_sb[0] = 0; 455 sc->sc_is.is_sb[1] = 0; 456#ifdef notyet 457 if (OF_getproplen(node, "no-streaming-cache") < 0) 458 sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 459#endif 460 461#define TSBCASE(x) \ 462 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 463 tsbsize = (x); \ 464 break; \ 465 466 n = OF_getprop(node, "virtual-dma", (void *)prop_array, 467 sizeof(prop_array)); 468 if (n == -1 || n != sizeof(prop_array)) 469 schizo_iommu_init(sc, 7, -1); 470 else { 471 switch (prop_array[1]) { 472 TSBCASE(1); 473 TSBCASE(2); 474 TSBCASE(3); 475 TSBCASE(4); 476 TSBCASE(5); 477 TSBCASE(6); 478 TSBCASE(7); 479 TSBCASE(8); 480 default: 481 panic("%s: unsupported DVMA size 0x%x", 482 __func__, prop_array[1]); 483 /* NOTREACHED */ 484 } 485 schizo_iommu_init(sc, tsbsize, prop_array[0]); 486 } 487 488#undef TSBCASE 489 490 /* Initialize memory and I/O rmans. */ 491 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 492 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 493 if (rman_init(&sc->sc_pci_io_rman) != 0 || 494 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 495 panic("%s: failed to set up I/O rman", __func__); 496 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 497 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 498 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 499 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 500 panic("%s: failed to set up memory rman", __func__); 501 502 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 503 (void **)&range); 504 /* 505 * Make sure that the expected ranges are present. The 506 * OFW_PCI_CS_MEM64 one is not currently used though. 507 */ 508 if (nrange != STX_NRANGE) 509 panic("%s: unsupported number of ranges", __func__); 510 /* 511 * Find the addresses of the various bus spaces. 512 * There should not be multiple ones of one kind. 513 * The physical start addresses of the ranges are the configuration, 514 * memory and I/O handles. 515 */ 516 for (n = 0; n < STX_NRANGE; n++) { 517 i = OFW_PCI_RANGE_CS(&range[n]); 518 if (sc->sc_pci_bh[i] != 0) 519 panic("%s: duplicate range for space %d", __func__, i); 520 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 521 } 522 free(range, M_OFWPROP); 523 524 /* Register the softc, this is needed for paired Schizos. */ 525 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 526 527 /* Allocate our tags. */ 528 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 529 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 530 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 531 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 532 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 533 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 534 panic("%s: bus_dma_tag_create failed", __func__); 535 /* Customize the tag. */ 536 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 537 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 538 539 /* 540 * Get the bus range from the firmware. 541 * NB: Tomatillos don't support PCI bus reenumeration. 542 */ 543 n = OF_getprop(node, "bus-range", (void *)prop_array, 544 sizeof(prop_array)); 545 if (n == -1) 546 panic("%s: could not get bus-range", __func__); 547 if (n != sizeof(prop_array)) 548 panic("%s: broken bus-range (%d)", __func__, n); 549 if (bootverbose) 550 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 551 prop_array[0], prop_array[1], prop_array[0]); 552 sc->sc_pci_secbus = prop_array[0]; 553 554 /* Clear any pending PCI error bits. */ 555 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 556 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 557 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 558 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 559 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 560 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 561 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 562 563 /* 564 * Establish handlers for interesting interrupts... 565 * Someone at Sun clearly was smoking crack; with Schizos PCI 566 * bus error interrupts for one PBM can be routed to the other 567 * PBM though we obviously need to use the softc of the former 568 * as the argument for the interrupt handler and the softc of 569 * the latter as the argument for the interrupt controller. 570 */ 571 if (sc->sc_half == 0) { 572 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 573 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 574 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 575 sica_sc == osc)) 576 /* 577 * We are the driver for PBM A and either also 578 * registered the interrupt controller for us or 579 * the driver for PBM B has probed first and 580 * registered it for us. 581 */ 582 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 583 schizo_pci_bus); 584 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 585 osc != NULL) 586 /* 587 * We are the driver for PBM A but registered 588 * the interrupt controller for PBM B, i.e. the 589 * driver for PBM B attached first but couldn't 590 * set up a handler for PBM B. 591 */ 592 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 593 schizo_pci_bus); 594 } else { 595 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 596 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 597 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 598 sica_sc == osc)) 599 /* 600 * We are the driver for PBM B and either also 601 * registered the interrupt controller for us or 602 * the driver for PBM A has probed first and 603 * registered it for us. 604 */ 605 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 606 schizo_pci_bus); 607 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 608 osc != NULL) 609 /* 610 * We are the driver for PBM B but registered 611 * the interrupt controller for PBM A, i.e. the 612 * driver for PBM A attached first but couldn't 613 * set up a handler for PBM A. 614 */ 615 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 616 schizo_pci_bus); 617 } 618 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 619 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 620 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 621 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 622 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 623 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 624 625 /* 626 * According to the Schizo Errata I-13, consistent DMA flushing/ 627 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 628 * so we can't use it and need to live with the consequences. 629 * With Schizo version >= 5, CDMA flushing/syncing is usable 630 * but requires the the workaround described in Schizo Errata 631 * I-23. With Tomatillo and XMITS, CDMA flushing/syncing works 632 * as expected, Tomatillo version <= 4 (i.e. revision <= 2.3) 633 * bridges additionally require a block store after a write to 634 * TOMXMS_PCI_DMA_SYNC_PEND though. 635 */ 636 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 637 sc->sc_mode == SCHIZO_MODE_TOM || sc->sc_mode == SCHIZO_MODE_XMS) { 638 sc->sc_flags |= SCHIZO_FLAGS_CDMA; 639 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 640 n = STX_CDMA_A_INO + sc->sc_half; 641 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 642 INTMAP_VEC(sc->sc_ign, n), 1) != 0) 643 panic("%s: failed to add CDMA interrupt", 644 __func__); 645 i = schizo_intr_register(sc, n); 646 if (i != 0) 647 panic("%s: could not register interrupt " 648 "controller for CDMA (%d)", __func__, i); 649 (void)schizo_get_intrmap(sc, n, NULL, 650 &sc->sc_cdma_clr); 651 sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 652 schizo_set_intr(sc, 5, n, schizo_cdma); 653 } 654 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 655 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 656 } 657 658 /* 659 * Set the latency timer register as this isn't always done by the 660 * firmware. 661 */ 662 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 663 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 664 665 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 666 667 device_add_child(dev, "pci", -1); 668 return (bus_generic_attach(dev)); 669} 670 671static void 672schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 673 driver_filter_t handler) 674{ 675 u_long vec; 676 int rid; 677 678 rid = index; 679 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 680 &rid, RF_ACTIVE); 681 if (sc->sc_irq_res[index] == NULL || 682 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 683 INTINO(vec) != ino || 684 intr_vectors[vec].iv_ic != &schizo_ic || 685 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 686 INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 687 &sc->sc_ihand[index]) != 0) 688 panic("%s: failed to set up interrupt %d", __func__, index); 689} 690 691static int 692schizo_intr_register(struct schizo_softc *sc, u_int ino) 693{ 694 struct schizo_icarg *sica; 695 bus_addr_t intrclr, intrmap; 696 int error; 697 698 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 699 return (ENXIO); 700 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 701 if (sica == NULL) 702 return (ENOMEM); 703 sica->sica_sc = sc; 704 sica->sica_map = intrmap; 705 sica->sica_clr = intrclr; 706#ifdef SCHIZO_DEBUG 707 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 708 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 709 (u_long)intrclr); 710#endif 711 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 712 &schizo_ic, sica)); 713 if (error != 0) 714 free(sica, M_DEVBUF); 715 return (error); 716} 717 718static int 719schizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr, 720 bus_addr_t *intrclrptr) 721{ 722 bus_addr_t intrclr, intrmap; 723 uint64_t mr; 724 725 /* 726 * XXX we only look for INOs rather than INRs since the firmware 727 * may not provide the IGN and the IGN is constant for all devices 728 * on that PCI controller. 729 */ 730 731 if (ino > STX_MAX_INO) { 732 device_printf(sc->sc_dev, "out of range INO %d requested\n", 733 ino); 734 return (0); 735 } 736 737 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 738 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 739 mr = SCHIZO_PCI_READ_8(sc, intrmap); 740 if (INTINO(mr) != ino) { 741 device_printf(sc->sc_dev, 742 "interrupt map entry does not match INO (%d != %d)\n", 743 (int)INTINO(mr), ino); 744 return (0); 745 } 746 747 if (intrmapptr != NULL) 748 *intrmapptr = intrmap; 749 if (intrclrptr != NULL) 750 *intrclrptr = intrclr; 751 return (1); 752} 753 754/* 755 * Interrupt handlers 756 */ 757static int 758schizo_pci_bus(void *arg) 759{ 760 struct schizo_softc *sc = arg; 761 uint64_t afar, afsr, csr, iommu; 762 uint32_t status; 763 764 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 765 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 766 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 767 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 768 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 769 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 770 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 771 if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 772 goto clear_error; 773 774 /* These are non-fatal if target abort was signaled. */ 775 if ((status & PCIM_STATUS_STABORT) != 0 && 776 ((iommu & TOM_PCI_IOMMU_ERRMASK) == 777 TOM_PCI_IOMMU_INVALID_ERR || 778 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 779 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 780 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 781 goto clear_error; 782 } 783 } 784 785 panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 786 "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 787 'A' + sc->sc_half, (unsigned long long)afar, 788 (unsigned long long)afsr, (unsigned long long)csr, 789 (unsigned long long)iommu, (unsigned long long)status); 790 791 clear_error: 792 if (bootverbose) 793 device_printf(sc->sc_dev, 794 "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 795 "STATUS %#llx", 'A' + sc->sc_half, 796 (unsigned long long)afar, (unsigned long long)afsr, 797 (unsigned long long)csr, (unsigned long long)status); 798 /* Clear the error bits that we caught. */ 799 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 800 STX_CS_FUNC, PCIR_STATUS, status, 2); 801 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 802 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 803 return (FILTER_HANDLED); 804} 805 806static int 807schizo_ue(void *arg) 808{ 809 struct schizo_softc *sc = arg; 810 uint64_t afar, afsr; 811 int i; 812 813 mtx_lock_spin(sc->sc_mtx); 814 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 815 for (i = 0; i < 1000; i++) 816 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 817 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 818 break; 819 mtx_unlock_spin(sc->sc_mtx); 820 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 821 device_get_name(sc->sc_dev), (unsigned long long)afar, 822 (unsigned long long)afsr); 823 return (FILTER_HANDLED); 824} 825 826static int 827schizo_ce(void *arg) 828{ 829 struct schizo_softc *sc = arg; 830 uint64_t afar, afsr; 831 int i; 832 833 mtx_lock_spin(sc->sc_mtx); 834 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 835 for (i = 0; i < 1000; i++) 836 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 837 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 838 break; 839 device_printf(sc->sc_dev, 840 "correctable DMA error AFAR %#llx AFSR %#llx\n", 841 (unsigned long long)afar, (unsigned long long)afsr); 842 /* Clear the error bits that we caught. */ 843 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 844 mtx_unlock_spin(sc->sc_mtx); 845 return (FILTER_HANDLED); 846} 847 848static int 849schizo_host_bus(void *arg) 850{ 851 struct schizo_softc *sc = arg; 852 uint64_t errlog; 853 854 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 855 panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 856 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 857 (unsigned long long)errlog); 858 return (FILTER_HANDLED); 859} 860 861static int 862schizo_cdma(void *arg) 863{ 864 struct schizo_softc *sc = arg; 865 866 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 867 return (FILTER_HANDLED); 868} 869 870static void 871schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 872{ 873 874 /* Punch in our copies. */ 875 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 876 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 877 sc->sc_is.is_iommu = STX_PCI_IOMMU; 878 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 879 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 880 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 881 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 882 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 883 884 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 885 dvmabase, 0); 886} 887 888static int 889schizo_maxslots(device_t dev) 890{ 891 struct schizo_softc *sc; 892 893 sc = device_get_softc(dev); 894 if (sc->sc_mode == SCHIZO_MODE_SCZ) 895 return (sc->sc_half == 0 ? 4 : 6); 896 897 /* XXX: is this correct? */ 898 return (PCI_SLOTMAX); 899} 900 901static uint32_t 902schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 903 int width) 904{ 905 struct schizo_softc *sc; 906 bus_space_handle_t bh; 907 u_long offset = 0; 908 uint32_t r, wrd; 909 int i; 910 uint16_t shrt; 911 uint8_t byte; 912 913 sc = device_get_softc(dev); 914 915 /* 916 * The Schizo bridges contain a dupe of their header at 0x80. 917 */ 918 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 919 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 920 reg + width > 0x80) 921 return (0); 922 923 offset = STX_CONF_OFF(bus, slot, func, reg); 924 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 925 switch (width) { 926 case 1: 927 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 928 r = byte; 929 break; 930 case 2: 931 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 932 r = shrt; 933 break; 934 case 4: 935 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 936 r = wrd; 937 break; 938 default: 939 panic("%s: bad width", __func__); 940 /* NOTREACHED */ 941 } 942 943 if (i) { 944#ifdef SCHIZO_DEBUG 945 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 946 __func__, bus, slot, func, reg); 947#endif 948 r = -1; 949 } 950 return (r); 951} 952 953static void 954schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 955 uint32_t val, int width) 956{ 957 struct schizo_softc *sc; 958 bus_space_handle_t bh; 959 u_long offset = 0; 960 961 sc = device_get_softc(dev); 962 offset = STX_CONF_OFF(bus, slot, func, reg); 963 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 964 switch (width) { 965 case 1: 966 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 967 break; 968 case 2: 969 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 970 break; 971 case 4: 972 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 973 break; 974 default: 975 panic("%s: bad width", __func__); 976 /* NOTREACHED */ 977 } 978} 979 980static int 981schizo_route_interrupt(device_t bridge, device_t dev, int pin) 982{ 983 struct schizo_softc *sc; 984 struct ofw_pci_register reg; 985 ofw_pci_intr_t pintr, mintr; 986 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 987 988 sc = device_get_softc(bridge); 989 pintr = pin; 990 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 991 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 992 return (mintr); 993 994 device_printf(bridge, "could not route pin %d for device %d.%d\n", 995 pin, pci_get_slot(dev), pci_get_function(dev)); 996 return (PCI_INVALID_IRQ); 997} 998 999static int 1000schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1001{ 1002 struct schizo_softc *sc; 1003 1004 sc = device_get_softc(dev); 1005 switch (which) { 1006 case PCIB_IVAR_DOMAIN: 1007 *result = device_get_unit(dev); 1008 return (0); 1009 case PCIB_IVAR_BUS: 1010 *result = sc->sc_pci_secbus; 1011 return (0); 1012 } 1013 return (ENOENT); 1014} 1015 1016static int 1017schizo_dma_sync_stub(void *arg) 1018{ 1019 struct timeval cur, end; 1020 struct schizo_dma_sync *sds = arg; 1021 struct schizo_softc *sc = sds->sds_sc; 1022 uint32_t state; 1023 1024 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1025 sds->sds_func, PCIR_VENDOR, 2); 1026 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE, 1027 SCHIZO_CDMA_STATE_PENDING) == 0;) 1028 ; 1029 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1); 1030 microuptime(&cur); 1031 end.tv_sec = 1; 1032 end.tv_usec = 0; 1033 timevaladd(&end, &cur); 1034 for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1035 SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1036 microuptime(&cur); 1037 if (state != SCHIZO_CDMA_STATE_DONE) 1038 panic("%s: DMA does not sync", __func__); 1039 return (sds->sds_handler(sds->sds_arg)); 1040} 1041 1042#define VIS_BLOCKSIZE 64 1043 1044static int 1045ichip_dma_sync_stub(void *arg) 1046{ 1047 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1048 struct timeval cur, end; 1049 struct schizo_dma_sync *sds = arg; 1050 struct schizo_softc *sc = sds->sds_sc; 1051 register_t reg, s; 1052 1053 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1054 sds->sds_func, PCIR_VENDOR, 2); 1055 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1056 microuptime(&cur); 1057 end.tv_sec = 1; 1058 end.tv_usec = 0; 1059 timevaladd(&end, &cur); 1060 for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1061 sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1062 microuptime(&cur); 1063 if ((reg & sds->sds_syncval) != 0) 1064 panic("%s: DMA does not sync", __func__); 1065 1066 if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1067 s = intr_disable(); 1068 reg = rd(fprs); 1069 wr(fprs, reg | FPRS_FEF, 0); 1070 __asm __volatile("stda %%f0, [%0] %1" 1071 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1072 membar(Sync); 1073 wr(fprs, reg, 0); 1074 intr_restore(s); 1075 } 1076 return (sds->sds_handler(sds->sds_arg)); 1077} 1078 1079static void 1080schizo_intr_enable(void *arg) 1081{ 1082 struct intr_vector *iv = arg; 1083 struct schizo_icarg *sica = iv->iv_icarg; 1084 1085 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1086 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1087} 1088 1089static void 1090schizo_intr_disable(void *arg) 1091{ 1092 struct intr_vector *iv = arg; 1093 struct schizo_icarg *sica = iv->iv_icarg; 1094 1095 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1096} 1097 1098static void 1099schizo_intr_assign(void *arg) 1100{ 1101 struct intr_vector *iv = arg; 1102 struct schizo_icarg *sica = iv->iv_icarg; 1103 1104 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1105 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1106} 1107 1108static void 1109schizo_intr_clear(void *arg) 1110{ 1111 struct intr_vector *iv = arg; 1112 struct schizo_icarg *sica = iv->iv_icarg; 1113 1114 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0); 1115} 1116 1117static int 1118schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1119 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1120 void **cookiep) 1121{ 1122 devclass_t pci_devclass; 1123 device_t cdev, pdev, pcidev; 1124 struct schizo_dma_sync *sds; 1125 struct schizo_softc *sc; 1126 u_long vec; 1127 int error, found; 1128 1129 sc = device_get_softc(dev); 1130 /* 1131 * Make sure the vector is fully specified and we registered 1132 * our interrupt controller for it. 1133 */ 1134 vec = rman_get_start(ires); 1135 if (INTIGN(vec) != sc->sc_ign || 1136 intr_vectors[vec].iv_ic != &schizo_ic) { 1137 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1138 return (EINVAL); 1139 } 1140 1141 /* 1142 * Install a a wrapper for CDMA flushing/syncing for devices 1143 * behind PCI-PCI bridges if possible. 1144 */ 1145 pcidev = NULL; 1146 found = 0; 1147 pci_devclass = devclass_find("pci"); 1148 for (cdev = child; cdev != dev; cdev = pdev) { 1149 pdev = device_get_parent(cdev); 1150 if (pcidev == NULL) { 1151 if (device_get_devclass(pdev) != pci_devclass) 1152 continue; 1153 pcidev = cdev; 1154 continue; 1155 } 1156 if (pci_get_class(cdev) == PCIC_BRIDGE && 1157 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1158 found = 1; 1159 } 1160 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1161 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1162 if (sds == NULL) 1163 return (ENOMEM); 1164 if (found != 0 && pcidev != NULL) { 1165 sds->sds_sc = sc; 1166 sds->sds_arg = arg; 1167 sds->sds_ppb = 1168 device_get_parent(device_get_parent(pcidev)); 1169 sds->sds_bus = pci_get_bus(pcidev); 1170 sds->sds_slot = pci_get_slot(pcidev); 1171 sds->sds_func = pci_get_function(pcidev); 1172 sds->sds_syncval = 1ULL << INTINO(vec); 1173 if (bootverbose) 1174 device_printf(dev, "installed DMA sync " 1175 "wrapper for device %d.%d on bus %d\n", 1176 sds->sds_slot, sds->sds_func, 1177 sds->sds_bus); 1178 1179#define DMA_SYNC_STUB \ 1180 (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1181 ichip_dma_sync_stub) 1182 1183 if (intr == NULL) { 1184 sds->sds_handler = filt; 1185 error = bus_generic_setup_intr(dev, child, 1186 ires, flags, DMA_SYNC_STUB, intr, sds, 1187 cookiep); 1188 } else { 1189 sds->sds_handler = (driver_filter_t *)intr; 1190 error = bus_generic_setup_intr(dev, child, 1191 ires, flags, filt, (driver_intr_t *) 1192 DMA_SYNC_STUB, sds, cookiep); 1193 } 1194 1195#undef DMA_SYNC_STUB 1196 1197 } else 1198 error = bus_generic_setup_intr(dev, child, ires, 1199 flags, filt, intr, arg, cookiep); 1200 if (error != 0) { 1201 free(sds, M_DEVBUF); 1202 return (error); 1203 } 1204 sds->sds_cookie = *cookiep; 1205 *cookiep = sds; 1206 return (error); 1207 } else if (found != 0) 1208 device_printf(dev, "WARNING: using devices behind PCI-PCI " 1209 "bridges may cause data corruption"); 1210 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1211 arg, cookiep)); 1212} 1213 1214static int 1215schizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1216 void *cookie) 1217{ 1218 struct schizo_dma_sync *sds; 1219 struct schizo_softc *sc; 1220 int error; 1221 1222 sc = device_get_softc(dev); 1223 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1224 sds = cookie; 1225 error = bus_generic_teardown_intr(dev, child, vec, 1226 sds->sds_cookie); 1227 if (error == 0) 1228 free(sds, M_DEVBUF); 1229 return (error); 1230 } 1231 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1232} 1233 1234static struct resource * 1235schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1236 u_long start, u_long end, u_long count, u_int flags) 1237{ 1238 struct schizo_softc *sc; 1239 struct resource *rv; 1240 struct rman *rm; 1241 bus_space_tag_t bt; 1242 bus_space_handle_t bh; 1243 int needactivate = flags & RF_ACTIVE; 1244 1245 flags &= ~RF_ACTIVE; 1246 1247 sc = device_get_softc(bus); 1248 if (type == SYS_RES_IRQ) { 1249 /* 1250 * XXX: Don't accept blank ranges for now, only single 1251 * interrupts. The other case should not happen with 1252 * the MI PCI code... 1253 * XXX: This may return a resource that is out of the 1254 * range that was specified. Is this correct...? 1255 */ 1256 if (start != end) 1257 panic("%s: XXX: interrupt range", __func__); 1258 start = end = INTMAP_VEC(sc->sc_ign, end); 1259 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1260 rid, start, end, count, flags)); 1261 } 1262 switch (type) { 1263 case SYS_RES_MEMORY: 1264 rm = &sc->sc_pci_mem_rman; 1265 bt = sc->sc_pci_memt; 1266 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1267 break; 1268 case SYS_RES_IOPORT: 1269 rm = &sc->sc_pci_io_rman; 1270 bt = sc->sc_pci_iot; 1271 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1272 break; 1273 default: 1274 return (NULL); 1275 /* NOTREACHED */ 1276 } 1277 1278 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1279 if (rv == NULL) 1280 return (NULL); 1281 rman_set_rid(rv, *rid); 1282 bh += rman_get_start(rv); 1283 rman_set_bustag(rv, bt); 1284 rman_set_bushandle(rv, bh); 1285 1286 if (needactivate) { 1287 if (bus_activate_resource(child, type, *rid, rv)) { 1288 rman_release_resource(rv); 1289 return (NULL); 1290 } 1291 } 1292 return (rv); 1293} 1294 1295static int 1296schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1297 struct resource *r) 1298{ 1299 void *p; 1300 int error; 1301 1302 if (type == SYS_RES_IRQ) 1303 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1304 type, rid, r)); 1305 if (type == SYS_RES_MEMORY) { 1306 /* 1307 * Need to memory-map the device space, as some drivers 1308 * depend on the virtual address being set and usable. 1309 */ 1310 error = sparc64_bus_mem_map(rman_get_bustag(r), 1311 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1312 if (error != 0) 1313 return (error); 1314 rman_set_virtual(r, p); 1315 } 1316 return (rman_activate_resource(r)); 1317} 1318 1319static int 1320schizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1321 struct resource *r) 1322{ 1323 1324 if (type == SYS_RES_IRQ) 1325 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1326 type, rid, r)); 1327 if (type == SYS_RES_MEMORY) { 1328 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1329 rman_set_virtual(r, NULL); 1330 } 1331 return (rman_deactivate_resource(r)); 1332} 1333 1334static int 1335schizo_release_resource(device_t bus, device_t child, int type, int rid, 1336 struct resource *r) 1337{ 1338 int error; 1339 1340 if (type == SYS_RES_IRQ) 1341 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1342 type, rid, r)); 1343 if (rman_get_flags(r) & RF_ACTIVE) { 1344 error = bus_deactivate_resource(child, type, rid, r); 1345 if (error) 1346 return (error); 1347 } 1348 return (rman_release_resource(r)); 1349} 1350 1351static bus_dma_tag_t 1352schizo_get_dma_tag(device_t bus, device_t child) 1353{ 1354 struct schizo_softc *sc; 1355 1356 sc = device_get_softc(bus); 1357 return (sc->sc_pci_dmat); 1358} 1359 1360static phandle_t 1361schizo_get_node(device_t bus, device_t dev) 1362{ 1363 struct schizo_softc *sc; 1364 1365 sc = device_get_softc(bus); 1366 /* We only have one child, the PCI bus, which needs our own node. */ 1367 return (sc->sc_node); 1368} 1369 1370static bus_space_tag_t 1371schizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1372{ 1373 bus_space_tag_t bt; 1374 1375 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1376 M_NOWAIT | M_ZERO); 1377 if (bt == NULL) 1378 panic("%s: out of memory", __func__); 1379 1380 bt->bst_cookie = sc; 1381 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1382 bt->bst_type = type; 1383 return (bt); 1384} 1385 1386static u_int 1387schizo_get_timecount(struct timecounter *tc) 1388{ 1389 struct schizo_softc *sc; 1390 1391 sc = tc->tc_priv; 1392 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1393 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1394} 1395