1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)vmparam.h 5.9 (Berkeley) 5/12/91 35 * from: FreeBSD: src/sys/i386/include/vmparam.h,v 1.33 2000/03/30 36 * $FreeBSD: releng/10.3/sys/sparc64/include/vmparam.h 266204 2014-05-16 01:30:30Z ian $ 37 */ 38 39#ifndef _MACHINE_VMPARAM_H_ 40#define _MACHINE_VMPARAM_H_ 41 42/* 43 * Virtual memory related constants, all in bytes 44 */ 45#ifndef MAXTSIZ 46#define MAXTSIZ (1*1024*1024*1024) /* max text size */ 47#endif 48#ifndef DFLDSIZ 49#define DFLDSIZ (128*1024*1024) /* initial data size limit */ 50#endif 51#ifndef MAXDSIZ 52#define MAXDSIZ (1*1024*1024*1024) /* max data size */ 53#endif 54#ifndef DFLSSIZ 55#define DFLSSIZ (128*1024*1024) /* initial stack size limit */ 56#endif 57#ifndef MAXSSIZ 58#define MAXSSIZ (1*1024*1024*1024) /* max stack size */ 59#endif 60#ifndef SGROWSIZ 61#define SGROWSIZ (128*1024) /* amount to grow stack */ 62#endif 63 64/* 65 * The physical address space is sparsely populated. 66 */ 67#define VM_PHYSSEG_SPARSE 68 69/* 70 * The number of PHYSSEG entries must be one greater than the number 71 * of phys_avail entries because the phys_avail entry that spans the 72 * largest physical address that is accessible by ISA DMA is split 73 * into two PHYSSEG entries. 74 */ 75#define VM_PHYSSEG_MAX 64 76 77/* 78 * Create three free page pools: VM_FREEPOOL_DEFAULT is the default pool 79 * from which physical pages are allocated and VM_FREEPOOL_DIRECT is 80 * the pool from which physical pages for small UMA objects are 81 * allocated. 82 */ 83#define VM_NFREEPOOL 3 84#define VM_FREEPOOL_CACHE 2 85#define VM_FREEPOOL_DEFAULT 0 86#define VM_FREEPOOL_DIRECT 1 87 88/* 89 * Create two free page lists: VM_FREELIST_DEFAULT is for physical 90 * pages that are above the largest physical address that is 91 * accessible by ISA DMA and VM_FREELIST_ISADMA is for physical pages 92 * that are below that address. 93 */ 94#define VM_NFREELIST 2 95#define VM_FREELIST_DEFAULT 0 96#define VM_FREELIST_ISADMA 1 97 98/* 99 * An allocation size of 16MB is supported in order to optimize the 100 * use of the direct map by UMA. Specifically, a cache line contains 101 * at most four TTEs, collectively mapping 16MB of physical memory. 102 * By reducing the number of distinct 16MB "pages" that are used by UMA, 103 * the physical memory allocator reduces the likelihood of both 4MB 104 * page TLB misses and cache misses caused by 4MB page TLB misses. 105 */ 106#define VM_NFREEORDER 12 107 108/* 109 * Enable superpage reservations: 1 level. 110 */ 111#ifndef VM_NRESERVLEVEL 112#define VM_NRESERVLEVEL 1 113#endif 114 115/* 116 * Level 0 reservations consist of 512 pages. 117 */ 118#ifndef VM_LEVEL_0_ORDER 119#define VM_LEVEL_0_ORDER 9 120#endif 121 122/** 123 * Address space layout. 124 * 125 * UltraSPARC I and II implement a 44 bit virtual address space. The address 126 * space is split into 2 regions at each end of the 64 bit address space, with 127 * an out of range "hole" in the middle. UltraSPARC III implements the full 128 * 64 bit virtual address space, but we don't really have any use for it and 129 * 43 bits of user address space is considered to be "enough", so we ignore it. 130 * 131 * Upper region: 0xffffffffffffffff 132 * 0xfffff80000000000 133 * 134 * Hole: 0xfffff7ffffffffff 135 * 0x0000080000000000 136 * 137 * Lower region: 0x000007ffffffffff 138 * 0x0000000000000000 139 * 140 * In general we ignore the upper region, and use the lower region as mappable 141 * space. 142 * 143 * We define some interesting address constants: 144 * 145 * VM_MIN_ADDRESS and VM_MAX_ADDRESS define the start and end of the entire 146 * 64 bit address space, mostly just for convenience. 147 * 148 * VM_MIN_DIRECT_ADDRESS and VM_MAX_DIRECT_ADDRESS define the start and end 149 * of the direct mapped region. This maps virtual addresses to physical 150 * addresses directly using 4mb tlb entries, with the physical address encoded 151 * in the lower 43 bits of virtual address. These mappings are convenient 152 * because they do not require page tables, and because they never change they 153 * do not require tlb flushes. However, since these mappings are cacheable, 154 * we must ensure that all pages accessed this way are either not double 155 * mapped, or that all other mappings have virtual color equal to physical 156 * color, in order to avoid creating illegal aliases in the data cache. 157 * 158 * VM_MIN_KERNEL_ADDRESS and VM_MAX_KERNEL_ADDRESS define the start and end of 159 * mappable kernel virtual address space. VM_MIN_KERNEL_ADDRESS is basically 160 * arbitrary, a convenient address is chosen which allows both the kernel text 161 * and data and the prom's address space to be mapped with 1 4mb tsb page. 162 * VM_MAX_KERNEL_ADDRESS is variable, computed at startup time based on the 163 * amount of physical memory available. Each 4mb tsb page provides 1g of 164 * virtual address space, with the only practical limit being available 165 * phsyical memory. 166 * 167 * VM_MIN_PROM_ADDRESS and VM_MAX_PROM_ADDRESS define the start and end of the 168 * prom address space. On startup the prom's mappings are duplicated in the 169 * kernel tsb, to allow prom memory to be accessed normally by the kernel. 170 * 171 * VM_MIN_USER_ADDRESS and VM_MAX_USER_ADDRESS define the start and end of the 172 * user address space. There are some hardware errata about using addresses 173 * at the boundary of the va hole, so we allow just under 43 bits of user 174 * address space. Note that the kernel and user address spaces overlap, but 175 * this doesn't matter because they use different tlb contexts, and because 176 * the kernel address space is not mapped into each process' address space. 177 */ 178#define VM_MIN_ADDRESS (0x0000000000000000UL) 179#define VM_MAX_ADDRESS (0xffffffffffffffffUL) 180 181#define VM_MIN_DIRECT_ADDRESS (0xfffff80000000000UL) 182#define VM_MAX_DIRECT_ADDRESS (VM_MAX_ADDRESS) 183 184#define VM_MIN_KERNEL_ADDRESS (0x00000000c0000000UL) 185#define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address) 186 187#define VM_MIN_PROM_ADDRESS (0x00000000f0000000UL) 188#define VM_MAX_PROM_ADDRESS (0x00000000ffffffffUL) 189 190#define VM_MIN_USER_ADDRESS (0x0000000000000000UL) 191#define VM_MAX_USER_ADDRESS (0x000007fe00000000UL) 192 193#define VM_MINUSER_ADDRESS (VM_MIN_USER_ADDRESS) 194#define VM_MAXUSER_ADDRESS (VM_MAX_USER_ADDRESS) 195 196#define KERNBASE (VM_MIN_KERNEL_ADDRESS) 197#define PROMBASE (VM_MIN_PROM_ADDRESS) 198#define USRSTACK (VM_MAX_USER_ADDRESS) 199 200/* 201 * How many physical pages per kmem arena virtual page. 202 */ 203#ifndef VM_KMEM_SIZE_SCALE 204#define VM_KMEM_SIZE_SCALE (tsb_kernel_ldd_phys == 0 ? 3 : 2) 205#endif 206 207/* 208 * Optional floor (in bytes) on the size of the kmem arena. 209 */ 210#ifndef VM_KMEM_SIZE_MIN 211#define VM_KMEM_SIZE_MIN (16 * 1024 * 1024) 212#endif 213 214/* 215 * Optional ceiling (in bytes) on the size of the kmem arena: 60% of the 216 * kernel map. 217 */ 218#ifndef VM_KMEM_SIZE_MAX 219#define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \ 220 VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5) 221#endif 222 223/* 224 * Initial pagein size of beginning of executable file. 225 */ 226#ifndef VM_INITIAL_PAGEIN 227#define VM_INITIAL_PAGEIN 16 228#endif 229 230#define UMA_MD_SMALL_ALLOC 231 232extern u_int tsb_kernel_ldd_phys; 233extern vm_offset_t vm_max_kernel_address; 234 235/* 236 * Older sparc64 machines have a virtually indexed L1 data cache of 16KB. 237 * Consequently, mapping the same physical page multiple times may have 238 * caching disabled. 239 */ 240#define ZERO_REGION_SIZE PAGE_SIZE 241 242#endif /* !_MACHINE_VMPARAM_H_ */ 243