1188808Sgonzo/*-
2188808Sgonzo * Copyright (c) 2009, Oleksandr Tymoshenko
3188808Sgonzo * All rights reserved.
4188808Sgonzo *
5188808Sgonzo * Redistribution and use in source and binary forms, with or without
6188808Sgonzo * modification, are permitted provided that the following conditions
7188808Sgonzo * are met:
8188808Sgonzo * 1. Redistributions of source code must retain the above copyright
9188808Sgonzo *    notice unmodified, this list of conditions, and the following
10188808Sgonzo *    disclaimer.
11188808Sgonzo * 2. Redistributions in binary form must reproduce the above copyright
12188808Sgonzo *    notice, this list of conditions and the following disclaimer in the
13188808Sgonzo *    documentation and/or other materials provided with the distribution.
14188808Sgonzo *
15188808Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16188808Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17188808Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18188808Sgonzo * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19188808Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20188808Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21188808Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22188808Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23188808Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24188808Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25188808Sgonzo * SUCH DAMAGE.
26209802Sadrian *
27209802Sadrian * $FreeBSD: releng/10.3/sys/mips/atheros/if_argevar.h 261455 2014-02-04 03:36:42Z eadler $
28188808Sgonzo */
29188808Sgonzo
30188808Sgonzo#ifndef __IF_ARGEVAR_H__
31188808Sgonzo#define __IF_ARGEVAR_H__
32188808Sgonzo
33199234Sgonzo#define	ARGE_NPHY		32
34188808Sgonzo#define	ARGE_TX_RING_COUNT	128
35188808Sgonzo#define	ARGE_RX_RING_COUNT	128
36188808Sgonzo#define	ARGE_RX_DMA_SIZE	ARGE_RX_RING_COUNT * sizeof(struct arge_desc)
37188808Sgonzo#define	ARGE_TX_DMA_SIZE	ARGE_TX_RING_COUNT * sizeof(struct arge_desc)
38188808Sgonzo#define	ARGE_MAXFRAGS		8
39188808Sgonzo#define ARGE_RING_ALIGN		sizeof(struct arge_desc)
40188808Sgonzo#define ARGE_RX_ALIGN		sizeof(uint32_t)
41188808Sgonzo#define ARGE_MAXFRAGS		8
42188808Sgonzo#define	ARGE_TX_RING_ADDR(sc, i)	\
43188808Sgonzo    ((sc)->arge_rdata.arge_tx_ring_paddr + sizeof(struct arge_desc) * (i))
44188808Sgonzo#define	ARGE_RX_RING_ADDR(sc, i)	\
45188808Sgonzo    ((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i))
46188808Sgonzo#define	ARGE_INC(x,y)		(x) = (((x) + 1) % y)
47188808Sgonzo
48188808Sgonzo
49188808Sgonzo#define	ARGE_MII_TIMEOUT	1000
50188808Sgonzo
51188808Sgonzo#define	ARGE_LOCK(_sc)		mtx_lock(&(_sc)->arge_mtx)
52188808Sgonzo#define	ARGE_UNLOCK(_sc)	mtx_unlock(&(_sc)->arge_mtx)
53188808Sgonzo#define	ARGE_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->arge_mtx, MA_OWNED)
54188808Sgonzo
55188808Sgonzo/*
56188808Sgonzo * register space access macros
57188808Sgonzo */
58188808Sgonzo#define ARGE_WRITE(sc, reg, val)	do {	\
59188808Sgonzo		bus_write_4(sc->arge_res, (reg), (val)); \
60188808Sgonzo	} while (0)
61188808Sgonzo
62188808Sgonzo#define ARGE_READ(sc, reg)	 bus_read_4(sc->arge_res, (reg))
63188808Sgonzo
64188808Sgonzo#define ARGE_SET_BITS(sc, reg, bits)	\
65188808Sgonzo	ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits))
66188808Sgonzo
67188808Sgonzo#define ARGE_CLEAR_BITS(sc, reg, bits)	\
68188808Sgonzo	ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits))
69188808Sgonzo
70234862Sadrian#define ARGE_MDIO_WRITE(_sc, _reg, _val)	\
71234862Sadrian	ARGE_WRITE((_sc), (_reg), (_val))
72234862Sadrian#define ARGE_MDIO_READ(_sc, _reg)	\
73234862Sadrian	ARGE_READ((_sc), (_reg))
74199038Sgonzo
75261455Seadler#define ARGE_DESC_EMPTY		(1U << 31)
76188808Sgonzo#define ARGE_DESC_MORE		(1 << 24)
77188808Sgonzo#define ARGE_DESC_SIZE_MASK	((1 << 12) - 1)
78188808Sgonzo#define	ARGE_DMASIZE(len)	((len) & ARGE_DESC_SIZE_MASK)
79188808Sgonzostruct arge_desc {
80188808Sgonzo	uint32_t	packet_addr;
81188808Sgonzo	uint32_t	packet_ctrl;
82188808Sgonzo	uint32_t	next_desc;
83188808Sgonzo	uint32_t	padding;
84188808Sgonzo};
85188808Sgonzo
86188808Sgonzostruct arge_txdesc {
87188808Sgonzo	struct mbuf	*tx_m;
88188808Sgonzo	bus_dmamap_t	tx_dmamap;
89188808Sgonzo};
90188808Sgonzo
91188808Sgonzostruct arge_rxdesc {
92188808Sgonzo	struct mbuf		*rx_m;
93188808Sgonzo	bus_dmamap_t		rx_dmamap;
94188808Sgonzo	struct arge_desc	*desc;
95188808Sgonzo};
96188808Sgonzo
97188808Sgonzostruct arge_chain_data {
98188808Sgonzo	bus_dma_tag_t		arge_parent_tag;
99188808Sgonzo	bus_dma_tag_t		arge_tx_tag;
100188808Sgonzo	struct arge_txdesc	arge_txdesc[ARGE_TX_RING_COUNT];
101188808Sgonzo	bus_dma_tag_t		arge_rx_tag;
102188808Sgonzo	struct arge_rxdesc	arge_rxdesc[ARGE_RX_RING_COUNT];
103188808Sgonzo	bus_dma_tag_t		arge_tx_ring_tag;
104188808Sgonzo	bus_dma_tag_t		arge_rx_ring_tag;
105188808Sgonzo	bus_dmamap_t		arge_tx_ring_map;
106188808Sgonzo	bus_dmamap_t		arge_rx_ring_map;
107188808Sgonzo	bus_dmamap_t		arge_rx_sparemap;
108188808Sgonzo	int			arge_tx_prod;
109188808Sgonzo	int			arge_tx_cons;
110188808Sgonzo	int			arge_tx_cnt;
111188808Sgonzo	int			arge_rx_cons;
112188808Sgonzo};
113188808Sgonzo
114188808Sgonzostruct arge_ring_data {
115188808Sgonzo	struct arge_desc	*arge_rx_ring;
116188808Sgonzo	struct arge_desc	*arge_tx_ring;
117188808Sgonzo	bus_addr_t		arge_rx_ring_paddr;
118188808Sgonzo	bus_addr_t		arge_tx_ring_paddr;
119188808Sgonzo};
120188808Sgonzo
121234919Sadrian/*
122234919Sadrian * Allow PLL values to be overridden.
123234919Sadrian */
124234919Sadrianstruct arge_pll_data {
125234919Sadrian	uint32_t pll_10;
126234919Sadrian	uint32_t pll_100;
127234919Sadrian	uint32_t pll_1000;
128234919Sadrian};
129234919Sadrian
130188808Sgonzostruct arge_softc {
131188808Sgonzo	struct ifnet		*arge_ifp;	/* interface info */
132188808Sgonzo	device_t		arge_dev;
133199234Sgonzo	struct ifmedia		arge_ifmedia;
134199234Sgonzo	/*
135199234Sgonzo	 * Media & duples settings for multiPHY MAC
136199234Sgonzo	 */
137199234Sgonzo	uint32_t		arge_media_type;
138199234Sgonzo	uint32_t		arge_duplex_mode;
139234862Sadrian	uint32_t		arge_phymask;
140234862Sadrian	uint8_t			arge_eaddr[ETHER_ADDR_LEN];
141188808Sgonzo	struct resource		*arge_res;
142188808Sgonzo	int			arge_rid;
143188808Sgonzo	struct resource		*arge_irq;
144188808Sgonzo	void			*arge_intrhand;
145188808Sgonzo	device_t		arge_miibus;
146234862Sadrian	device_t		arge_miiproxy;
147234910Sadrian	ar71xx_mii_mode		arge_miicfg;
148234919Sadrian	struct arge_pll_data	arge_pllcfg;
149188808Sgonzo	bus_dma_tag_t		arge_parent_tag;
150188808Sgonzo	bus_dma_tag_t		arge_tag;
151188808Sgonzo	struct mtx		arge_mtx;
152188808Sgonzo	struct callout		arge_stat_callout;
153188808Sgonzo	struct task		arge_link_task;
154188808Sgonzo	struct arge_chain_data	arge_cdata;
155188808Sgonzo	struct arge_ring_data	arge_rdata;
156188808Sgonzo	int			arge_link_status;
157188808Sgonzo	int			arge_detach;
158188808Sgonzo	uint32_t		arge_intr_status;
159188808Sgonzo	int			arge_mac_unit;
160198932Sgonzo	int			arge_if_flags;
161209802Sadrian	uint32_t		arge_debug;
162209809Sadrian	struct {
163209809Sadrian		uint32_t	tx_pkts_unaligned;
164209809Sadrian		uint32_t	tx_pkts_aligned;
165220356Sadrian		uint32_t	rx_overflow;
166220356Sadrian		uint32_t	tx_underflow;
167209809Sadrian	} stats;
168188808Sgonzo};
169188808Sgonzo
170188808Sgonzo#endif /* __IF_ARGEVAR_H__ */
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