History log of /freebsd-10.3-release/sys/mips/atheros/if_argevar.h
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# 296373 04-Mar-2016 marius

- Copy stable/10@296371 to releng/10.3 in preparation for 10.3-RC1
builds.
- Update newvers.sh to reflect RC1.
- Update __FreeBSD_version to reflect 10.3.
- Update default pkg(8) configuration to use the quarterly branch.

Approved by: re (implicit)

# 261455 04-Feb-2014 eadler

MFC r258779,r258780,r258787,r258822:

Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.

Similar to the (1 << 31) case it is not defined to do (2 << 30).

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.


# 256281 10-Oct-2013 gjb

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation


# 234919 02-May-2012 adrian

Implement PLL configuration override support, similar to what openwrt
implements.


# 234910 02-May-2012 adrian

Allow the MII mode to be overridden via 'hint.arge.X.miimode'.

It takes a number at the moment, rather than a string.

Some of the Linux board configurations specify the MII mode explicitly.


# 234862 01-May-2012 adrian

Break out the arge MDIO bus code into an optional argemdio device.

This is only done if the ARGE_MDIO option is included.

* Shuffle the arge MDIO bus into a separate device, that needs to be
probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.

This is done regardless:

* Shift the arge MAC and MDIO bus reset code into separate functions
and call it early during MDIO bus attach. It's required for
correct MDIO bus IO to occur on AR71xx/AR91xx devices.

* Remove the AR71xx/AR91xx centric assumption that there's only one
MDIO bus. The initial code mapped miibus0(arge0) and miibus1(arge1)
MII register operations to the MII0 (arge0) register space. The
AR724x (and later, upcoming chipsets) have two MDIO busses and
the second is very much in use.

TODO:

* since the multiphy behaviour has changed (where now a phymask of >1
PHY will still be enumerated), multiphy setups may be quite wrong.
I'll go and fix these so they still have a chance of working, at least.
until the switch PHY support appears in -HEAD.

Submitted by: Stefan Bethke <stb@lassitu.de>


# 220356 05-Apr-2011 adrian

* Add some more debugging to if_arge
* Make doubly sure that IFF_DRV_OACTIVE is set if the hardware TX queue is full


# 219590 13-Mar-2011 adrian

Fix the TX underrun status reset; remove a now unused variable.

Submitted by: Luiz Otavio O Souza


# 211511 19-Aug-2010 adrian

Migrate if_arge to use the PLL cpuops.

This has been lightly tested on the AR7161 and AR9132.


# 211479 19-Aug-2010 adrian

Remove the now-unused DDR flush register value.


# 209809 08-Jul-2010 adrian

Add TX-path aligned/unaligned stats for if_arge.


# 209802 08-Jul-2010 adrian

Introduce a sysctl block for if_arge and, for now, a blank debug sysctl
placeholder for later.

Add in a missing FreeBSD ID string.


# 202175 12-Jan-2010 imp

Set the svn:eol-style = native and svn:mime-type = text/plain
properties on all files in this tree.

Submitted by: rpaulo@


# 202173 12-Jan-2010 imp

Place proper svn:keywords tag on all these files. They were created
somehow without them on projects/mips, and that mistake was propigated
over to head.

Submitted by: rpaulo@


# 201906 09-Jan-2010 imp

Merge from projects/mips to head by hand:

Merge support files for the Atheros AR71xx (and soon AR9xxx)
processors, except files from sys/conf and sys/mips/conf. This work
was done primarily by Olecksandr Tymoshenko and works on the
RouterStation and RouterStation PRO. Other AR71xx-based boards have
been reported as working as well (RouterBoard, for example).


# 199234 12-Nov-2009 gonzo

- Handle multiphy MAC case: create interface with
fixed-state media with parameters set via hints
and configure MAC accordingly to these parameters.
All the underlying PHY magic is done by boot manager
on startup. At the moment there is no proper way
to make active and control all PHYs simultaneously
from one MII bus and there is no way to associate
incoming/outgoing packet with specific PHY.


# 199038 08-Nov-2009 gonzo

- Access to all 5 PHYs goes through registers in MAC0 memory
space, rewrite miibus accessors respectively


# 198970 06-Nov-2009 gonzo

- Fix initialization of PLL registers (different shifts for
arge0/arge1)
- Use base MAC address to generate MACs for arge1 and above


# 198932 04-Nov-2009 gonzo

- Remove noisy "Implement me" stubs
- Handle SIOCSIFFLAGS ioctl


# 191079 14-Apr-2009 gonzo

- Revert changes accidentally killed by merge operation


# 188808 19-Feb-2009 gonzo

- Driver for on-board AR71XX ethernet