1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include "skeleton.dtsi" 14#include "imx51-pinfunc.h" 15#include <dt-bindings/clock/imx5-clock.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/input/input.h> 18#include <dt-bindings/interrupt-controller/irq.h> 19 20/ { 21 aliases { 22 ethernet0 = &fec; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 i2c0 = &i2c1; 28 i2c1 = &i2c2; 29 mmc0 = &esdhc1; 30 mmc1 = &esdhc2; 31 mmc2 = &esdhc3; 32 mmc3 = &esdhc4; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 spi0 = &ecspi1; 37 spi1 = &ecspi2; 38 spi2 = &cspi; 39 }; 40 41 tzic: tz-interrupt-controller@e0000000 { 42 compatible = "fsl,imx51-tzic", "fsl,tzic"; 43 interrupt-controller; 44 #interrupt-cells = <1>; 45 reg = <0xe0000000 0x4000>; 46 }; 47 48 clocks { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 ckil { 53 compatible = "fsl,imx-ckil", "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <32768>; 56 }; 57 58 ckih1 { 59 compatible = "fsl,imx-ckih1", "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <0>; 62 }; 63 64 ckih2 { 65 compatible = "fsl,imx-ckih2", "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <0>; 68 }; 69 70 osc { 71 compatible = "fsl,imx-osc", "fixed-clock"; 72 #clock-cells = <0>; 73 clock-frequency = <24000000>; 74 }; 75 }; 76 77 cpus { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 cpu: cpu@0 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a8"; 83 reg = <0>; 84 clock-latency = <62500>; 85 clocks = <&clks IMX5_CLK_CPU_PODF>; 86 clock-names = "cpu"; 87 operating-points = < 88 166000 1000000 89 600000 1050000 90 800000 1100000 91 >; 92 voltage-tolerance = <5>; 93 }; 94 }; 95 96 usbphy { 97 #address-cells = <1>; 98 #size-cells = <0>; 99 compatible = "simple-bus"; 100 101 usbphy0: usbphy@0 { 102 compatible = "usb-nop-xceiv"; 103 reg = <0>; 104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>; 105 clock-names = "main_clk"; 106 }; 107 }; 108 109 display-subsystem { 110 compatible = "fsl,imx-display-subsystem"; 111 ports = <&ipu_di0>, <&ipu_di1>; 112 }; 113 114 soc { 115 #address-cells = <1>; 116 #size-cells = <1>; 117 compatible = "simple-bus"; 118 interrupt-parent = <&tzic>; 119 ranges; 120 121 iram: iram@1ffe0000 { 122 compatible = "mmio-sram"; 123 reg = <0x1ffe0000 0x20000>; 124 }; 125 126 ipu: ipu@40000000 { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 compatible = "fsl,imx51-ipu"; 130 reg = <0x40000000 0x20000000>; 131 interrupts = <11 10>; 132 clocks = <&clks IMX5_CLK_IPU_GATE>, 133 <&clks IMX5_CLK_IPU_DI0_GATE>, 134 <&clks IMX5_CLK_IPU_DI1_GATE>; 135 clock-names = "bus", "di0", "di1"; 136 resets = <&src 2>; 137 138 ipu_di0: port@2 { 139 reg = <2>; 140 141 ipu_di0_disp0: endpoint { 142 }; 143 }; 144 145 ipu_di1: port@3 { 146 reg = <3>; 147 148 ipu_di1_disp1: endpoint { 149 }; 150 }; 151 }; 152 153 aips@70000000 { /* AIPS1 */ 154 compatible = "fsl,aips-bus", "simple-bus"; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 reg = <0x70000000 0x10000000>; 158 ranges; 159 160 spba@70000000 { 161 compatible = "fsl,spba-bus", "simple-bus"; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 reg = <0x70000000 0x40000>; 165 ranges; 166 167 esdhc1: esdhc@70004000 { 168 compatible = "fsl,imx51-esdhc"; 169 reg = <0x70004000 0x4000>; 170 interrupts = <1>; 171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 172 <&clks IMX5_CLK_DUMMY>, 173 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 174 clock-names = "ipg", "ahb", "per"; 175 status = "disabled"; 176 }; 177 178 esdhc2: esdhc@70008000 { 179 compatible = "fsl,imx51-esdhc"; 180 reg = <0x70008000 0x4000>; 181 interrupts = <2>; 182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 183 <&clks IMX5_CLK_DUMMY>, 184 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 185 clock-names = "ipg", "ahb", "per"; 186 bus-width = <4>; 187 status = "disabled"; 188 }; 189 190 uart3: serial@7000c000 { 191 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 192 reg = <0x7000c000 0x4000>; 193 interrupts = <33>; 194 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 195 <&clks IMX5_CLK_UART3_PER_GATE>; 196 clock-names = "ipg", "per"; 197 status = "disabled"; 198 }; 199 200 ecspi1: ecspi@70010000 { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 compatible = "fsl,imx51-ecspi"; 204 reg = <0x70010000 0x4000>; 205 interrupts = <36>; 206 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 207 <&clks IMX5_CLK_ECSPI1_PER_GATE>; 208 clock-names = "ipg", "per"; 209 status = "disabled"; 210 }; 211 212 ssi2: ssi@70014000 { 213 #sound-dai-cells = <0>; 214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 215 reg = <0x70014000 0x4000>; 216 interrupts = <30>; 217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, 218 <&clks IMX5_CLK_SSI2_ROOT_GATE>; 219 clock-names = "ipg", "baud"; 220 dmas = <&sdma 24 1 0>, 221 <&sdma 25 1 0>; 222 dma-names = "rx", "tx"; 223 fsl,fifo-depth = <15>; 224 status = "disabled"; 225 }; 226 227 esdhc3: esdhc@70020000 { 228 compatible = "fsl,imx51-esdhc"; 229 reg = <0x70020000 0x4000>; 230 interrupts = <3>; 231 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, 232 <&clks IMX5_CLK_DUMMY>, 233 <&clks IMX5_CLK_ESDHC3_PER_GATE>; 234 clock-names = "ipg", "ahb", "per"; 235 bus-width = <4>; 236 status = "disabled"; 237 }; 238 239 esdhc4: esdhc@70024000 { 240 compatible = "fsl,imx51-esdhc"; 241 reg = <0x70024000 0x4000>; 242 interrupts = <4>; 243 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, 244 <&clks IMX5_CLK_DUMMY>, 245 <&clks IMX5_CLK_ESDHC4_PER_GATE>; 246 clock-names = "ipg", "ahb", "per"; 247 bus-width = <4>; 248 status = "disabled"; 249 }; 250 }; 251 252 usbotg: usb@73f80000 { 253 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 254 reg = <0x73f80000 0x0200>; 255 interrupts = <18>; 256 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 257 fsl,usbmisc = <&usbmisc 0>; 258 fsl,usbphy = <&usbphy0>; 259 status = "disabled"; 260 }; 261 262 usbh1: usb@73f80200 { 263 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 264 reg = <0x73f80200 0x0200>; 265 interrupts = <14>; 266 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 267 fsl,usbmisc = <&usbmisc 1>; 268 status = "disabled"; 269 }; 270 271 usbh2: usb@73f80400 { 272 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 273 reg = <0x73f80400 0x0200>; 274 interrupts = <16>; 275 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 276 fsl,usbmisc = <&usbmisc 2>; 277 status = "disabled"; 278 }; 279 280 usbh3: usb@73f80600 { 281 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 282 reg = <0x73f80600 0x0200>; 283 interrupts = <17>; 284 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 285 fsl,usbmisc = <&usbmisc 3>; 286 status = "disabled"; 287 }; 288 289 usbmisc: usbmisc@73f80800 { 290 #index-cells = <1>; 291 compatible = "fsl,imx51-usbmisc"; 292 reg = <0x73f80800 0x200>; 293 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 294 }; 295 296 gpio1: gpio@73f84000 { 297 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 298 reg = <0x73f84000 0x4000>; 299 interrupts = <50 51>; 300 gpio-controller; 301 #gpio-cells = <2>; 302 interrupt-controller; 303 #interrupt-cells = <2>; 304 }; 305 306 gpio2: gpio@73f88000 { 307 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 308 reg = <0x73f88000 0x4000>; 309 interrupts = <52 53>; 310 gpio-controller; 311 #gpio-cells = <2>; 312 interrupt-controller; 313 #interrupt-cells = <2>; 314 }; 315 316 gpio3: gpio@73f8c000 { 317 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 318 reg = <0x73f8c000 0x4000>; 319 interrupts = <54 55>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 }; 325 326 gpio4: gpio@73f90000 { 327 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 328 reg = <0x73f90000 0x4000>; 329 interrupts = <56 57>; 330 gpio-controller; 331 #gpio-cells = <2>; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 }; 335 336 kpp: kpp@73f94000 { 337 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; 338 reg = <0x73f94000 0x4000>; 339 interrupts = <60>; 340 clocks = <&clks IMX5_CLK_DUMMY>; 341 status = "disabled"; 342 }; 343 344 wdog1: wdog@73f98000 { 345 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 346 reg = <0x73f98000 0x4000>; 347 interrupts = <58>; 348 clocks = <&clks IMX5_CLK_DUMMY>; 349 }; 350 351 wdog2: wdog@73f9c000 { 352 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 353 reg = <0x73f9c000 0x4000>; 354 interrupts = <59>; 355 clocks = <&clks IMX5_CLK_DUMMY>; 356 status = "disabled"; 357 }; 358 359 gpt: timer@73fa0000 { 360 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; 361 reg = <0x73fa0000 0x4000>; 362 interrupts = <39>; 363 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, 364 <&clks IMX5_CLK_GPT_HF_GATE>; 365 clock-names = "ipg", "per"; 366 }; 367 368 iomuxc: iomuxc@73fa8000 { 369 compatible = "fsl,imx51-iomuxc"; 370 reg = <0x73fa8000 0x4000>; 371 }; 372 373 pwm1: pwm@73fb4000 { 374 #pwm-cells = <2>; 375 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 376 reg = <0x73fb4000 0x4000>; 377 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, 378 <&clks IMX5_CLK_PWM1_HF_GATE>; 379 clock-names = "ipg", "per"; 380 interrupts = <61>; 381 }; 382 383 pwm2: pwm@73fb8000 { 384 #pwm-cells = <2>; 385 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 386 reg = <0x73fb8000 0x4000>; 387 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, 388 <&clks IMX5_CLK_PWM2_HF_GATE>; 389 clock-names = "ipg", "per"; 390 interrupts = <94>; 391 }; 392 393 uart1: serial@73fbc000 { 394 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 395 reg = <0x73fbc000 0x4000>; 396 interrupts = <31>; 397 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, 398 <&clks IMX5_CLK_UART1_PER_GATE>; 399 clock-names = "ipg", "per"; 400 status = "disabled"; 401 }; 402 403 uart2: serial@73fc0000 { 404 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 405 reg = <0x73fc0000 0x4000>; 406 interrupts = <32>; 407 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, 408 <&clks IMX5_CLK_UART2_PER_GATE>; 409 clock-names = "ipg", "per"; 410 status = "disabled"; 411 }; 412 413 src: src@73fd0000 { 414 compatible = "fsl,imx51-src"; 415 reg = <0x73fd0000 0x4000>; 416 #reset-cells = <1>; 417 }; 418 419 clks: ccm@73fd4000{ 420 compatible = "fsl,imx51-ccm"; 421 reg = <0x73fd4000 0x4000>; 422 interrupts = <0 71 0x04 0 72 0x04>; 423 #clock-cells = <1>; 424 }; 425 }; 426 427 aips@80000000 { /* AIPS2 */ 428 compatible = "fsl,aips-bus", "simple-bus"; 429 #address-cells = <1>; 430 #size-cells = <1>; 431 reg = <0x80000000 0x10000000>; 432 ranges; 433 434 iim: iim@83f98000 { 435 compatible = "fsl,imx51-iim", "fsl,imx27-iim"; 436 reg = <0x83f98000 0x4000>; 437 interrupts = <69>; 438 clocks = <&clks IMX5_CLK_IIM_GATE>; 439 }; 440 441 owire: owire@83fa4000 { 442 compatible = "fsl,imx51-owire", "fsl,imx21-owire"; 443 reg = <0x83fa4000 0x4000>; 444 interrupts = <88>; 445 clocks = <&clks IMX5_CLK_OWIRE_GATE>; 446 status = "disabled"; 447 }; 448 449 ecspi2: ecspi@83fac000 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 compatible = "fsl,imx51-ecspi"; 453 reg = <0x83fac000 0x4000>; 454 interrupts = <37>; 455 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, 456 <&clks IMX5_CLK_ECSPI2_PER_GATE>; 457 clock-names = "ipg", "per"; 458 status = "disabled"; 459 }; 460 461 sdma: sdma@83fb0000 { 462 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 463 reg = <0x83fb0000 0x4000>; 464 interrupts = <6>; 465 clocks = <&clks IMX5_CLK_SDMA_GATE>, 466 <&clks IMX5_CLK_SDMA_GATE>; 467 clock-names = "ipg", "ahb"; 468 #dma-cells = <3>; 469 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 470 }; 471 472 cspi: cspi@83fc0000 { 473 #address-cells = <1>; 474 #size-cells = <0>; 475 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 476 reg = <0x83fc0000 0x4000>; 477 interrupts = <38>; 478 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, 479 <&clks IMX5_CLK_CSPI_IPG_GATE>; 480 clock-names = "ipg", "per"; 481 status = "disabled"; 482 }; 483 484 i2c2: i2c@83fc4000 { 485 #address-cells = <1>; 486 #size-cells = <0>; 487 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 488 reg = <0x83fc4000 0x4000>; 489 interrupts = <63>; 490 clocks = <&clks IMX5_CLK_I2C2_GATE>; 491 status = "disabled"; 492 }; 493 494 i2c1: i2c@83fc8000 { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 498 reg = <0x83fc8000 0x4000>; 499 interrupts = <62>; 500 clocks = <&clks IMX5_CLK_I2C1_GATE>; 501 status = "disabled"; 502 }; 503 504 ssi1: ssi@83fcc000 { 505 #sound-dai-cells = <0>; 506 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 507 reg = <0x83fcc000 0x4000>; 508 interrupts = <29>; 509 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, 510 <&clks IMX5_CLK_SSI1_ROOT_GATE>; 511 clock-names = "ipg", "baud"; 512 dmas = <&sdma 28 0 0>, 513 <&sdma 29 0 0>; 514 dma-names = "rx", "tx"; 515 fsl,fifo-depth = <15>; 516 status = "disabled"; 517 }; 518 519 audmux: audmux@83fd0000 { 520 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; 521 reg = <0x83fd0000 0x4000>; 522 clocks = <&clks IMX5_CLK_DUMMY>; 523 clock-names = "audmux"; 524 status = "disabled"; 525 }; 526 527 weim: weim@83fda000 { 528 #address-cells = <2>; 529 #size-cells = <1>; 530 compatible = "fsl,imx51-weim"; 531 reg = <0x83fda000 0x1000>; 532 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; 533 ranges = < 534 0 0 0xb0000000 0x08000000 535 1 0 0xb8000000 0x08000000 536 2 0 0xc0000000 0x08000000 537 3 0 0xc8000000 0x04000000 538 4 0 0xcc000000 0x02000000 539 5 0 0xce000000 0x02000000 540 >; 541 status = "disabled"; 542 }; 543 544 nfc: nand@83fdb000 { 545 #address-cells = <1>; 546 #size-cells = <1>; 547 compatible = "fsl,imx51-nand"; 548 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 549 interrupts = <8>; 550 clocks = <&clks IMX5_CLK_NFC_GATE>; 551 status = "disabled"; 552 }; 553 554 pata: pata@83fe0000 { 555 compatible = "fsl,imx51-pata", "fsl,imx27-pata"; 556 reg = <0x83fe0000 0x4000>; 557 interrupts = <70>; 558 clocks = <&clks IMX5_CLK_PATA_GATE>; 559 status = "disabled"; 560 }; 561 562 ssi3: ssi@83fe8000 { 563 #sound-dai-cells = <0>; 564 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 565 reg = <0x83fe8000 0x4000>; 566 interrupts = <96>; 567 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, 568 <&clks IMX5_CLK_SSI3_ROOT_GATE>; 569 clock-names = "ipg", "baud"; 570 dmas = <&sdma 46 0 0>, 571 <&sdma 47 0 0>; 572 dma-names = "rx", "tx"; 573 fsl,fifo-depth = <15>; 574 status = "disabled"; 575 }; 576 577 fec: ethernet@83fec000 { 578 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 579 reg = <0x83fec000 0x4000>; 580 interrupts = <87>; 581 clocks = <&clks IMX5_CLK_FEC_GATE>, 582 <&clks IMX5_CLK_FEC_GATE>, 583 <&clks IMX5_CLK_FEC_GATE>; 584 clock-names = "ipg", "ahb", "ptp"; 585 status = "disabled"; 586 }; 587 }; 588 }; 589}; 590