at91sam9260.dtsi revision 262573
1238384Sjkim/*
2238384Sjkim * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
3238384Sjkim *
4238384Sjkim *  Copyright (C) 2011 Atmel,
5238384Sjkim *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6238384Sjkim *                2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7238384Sjkim *
8238384Sjkim * Licensed under GPLv2 or later.
9238384Sjkim */
10238384Sjkim
11238384Sjkim#include "skeleton.dtsi"
12238384Sjkim#include <dt-bindings/pinctrl/at91.h>
13238384Sjkim#include <dt-bindings/interrupt-controller/irq.h>
14238384Sjkim#include <dt-bindings/gpio/gpio.h>
15238384Sjkim
16238384Sjkim/ {
17238384Sjkim	model = "Atmel AT91SAM9260 family SoC";
18238384Sjkim	compatible = "atmel,at91sam9260";
19238384Sjkim	interrupt-parent = <&aic>;
20238384Sjkim
21238384Sjkim	aliases {
22238384Sjkim		serial0 = &dbgu;
23238384Sjkim		serial1 = &usart0;
24238384Sjkim		serial2 = &usart1;
25238384Sjkim		serial3 = &usart2;
26238384Sjkim		serial4 = &usart3;
27238384Sjkim		serial5 = &uart0;
28238384Sjkim		serial6 = &uart1;
29238384Sjkim		gpio0 = &pioA;
30238384Sjkim		gpio1 = &pioB;
31238384Sjkim		gpio2 = &pioC;
32296341Sdelphij		tcb0 = &tcb0;
33296341Sdelphij		tcb1 = &tcb1;
34296341Sdelphij		i2c0 = &i2c0;
35296341Sdelphij		ssc0 = &ssc0;
36296341Sdelphij	};
37238384Sjkim	cpus {
38296341Sdelphij		#address-cells = <0>;
39296341Sdelphij		#size-cells = <0>;
40296341Sdelphij
41238384Sjkim		cpu {
42296341Sdelphij			compatible = "arm,arm926ej-s";
43238384Sjkim			device_type = "cpu";
44296341Sdelphij		};
45296341Sdelphij	};
46296341Sdelphij
47296341Sdelphij	memory {
48296341Sdelphij		reg = <0x20000000 0x04000000>;
49238384Sjkim	};
50238384Sjkim
51238384Sjkim	ahb {
52238384Sjkim		compatible = "simple-bus";
53238384Sjkim		#address-cells = <1>;
54296341Sdelphij		#size-cells = <1>;
55296341Sdelphij		ranges;
56296341Sdelphij
57296341Sdelphij		apb {
58296341Sdelphij			compatible = "simple-bus";
59238384Sjkim			#address-cells = <1>;
60238384Sjkim			#size-cells = <1>;
61238384Sjkim			ranges;
62296341Sdelphij
63296341Sdelphij			aic: interrupt-controller@fffff000 {
64296341Sdelphij				#interrupt-cells = <3>;
65296341Sdelphij				compatible = "atmel,at91rm9200-aic";
66296341Sdelphij				interrupt-controller;
67296341Sdelphij				reg = <0xfffff000 0x200>;
68296341Sdelphij				atmel,external-irqs = <29 30 31>;
69296341Sdelphij			};
70296341Sdelphij
71296341Sdelphij			ramc0: ramc@ffffea00 {
72296341Sdelphij				compatible = "atmel,at91sam9260-sdramc";
73296341Sdelphij				reg = <0xffffea00 0x200>;
74296341Sdelphij			};
75296341Sdelphij
76296341Sdelphij			pmc: pmc@fffffc00 {
77296341Sdelphij				compatible = "atmel,at91rm9200-pmc";
78296341Sdelphij				reg = <0xfffffc00 0x100>;
79296341Sdelphij			};
80296341Sdelphij
81296341Sdelphij			rstc@fffffd00 {
82296341Sdelphij				compatible = "atmel,at91sam9260-rstc";
83296341Sdelphij				reg = <0xfffffd00 0x10>;
84296341Sdelphij			};
85296341Sdelphij
86296341Sdelphij			shdwc@fffffd10 {
87296341Sdelphij				compatible = "atmel,at91sam9260-shdwc";
88296341Sdelphij				reg = <0xfffffd10 0x10>;
89296341Sdelphij			};
90296341Sdelphij
91296341Sdelphij			pit: timer@fffffd30 {
92296341Sdelphij				compatible = "atmel,at91sam9260-pit";
93296341Sdelphij				reg = <0xfffffd30 0xf>;
94296341Sdelphij				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
95296341Sdelphij			};
96296341Sdelphij
97296341Sdelphij			tcb0: timer@fffa0000 {
98296341Sdelphij				compatible = "atmel,at91rm9200-tcb";
99296341Sdelphij				reg = <0xfffa0000 0x100>;
100296341Sdelphij				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
101296341Sdelphij					      18 IRQ_TYPE_LEVEL_HIGH 0
102296341Sdelphij					      19 IRQ_TYPE_LEVEL_HIGH 0>;
103296341Sdelphij			};
104296341Sdelphij
105296341Sdelphij			tcb1: timer@fffdc000 {
106296341Sdelphij				compatible = "atmel,at91rm9200-tcb";
107296341Sdelphij				reg = <0xfffdc000 0x100>;
108296341Sdelphij				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
109296341Sdelphij					      27 IRQ_TYPE_LEVEL_HIGH 0
110296341Sdelphij					      28 IRQ_TYPE_LEVEL_HIGH 0>;
111296341Sdelphij			};
112296341Sdelphij
113238384Sjkim			pinctrl@fffff400 {
114296341Sdelphij				#address-cells = <1>;
115296341Sdelphij				#size-cells = <1>;
116238384Sjkim				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
117238384Sjkim				ranges = <0xfffff400 0xfffff400 0x600>;
118238384Sjkim
119238384Sjkim				atmel,mux-mask = <
120238384Sjkim				      /*    A         B     */
121238384Sjkim				       0xffffffff 0xffc00c3b  /* pioA */
122238384Sjkim				       0xffffffff 0x7fff3ccf  /* pioB */
123238384Sjkim				       0xffffffff 0x007fffff  /* pioC */
124238384Sjkim				      >;
125238384Sjkim
126238384Sjkim				/* shared pinctrl settings */
127238384Sjkim				dbgu {
128296341Sdelphij					pinctrl_dbgu: dbgu-0 {
129238384Sjkim						atmel,pins =
130238384Sjkim							<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A */
131238384Sjkim							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PB15 periph with pullup */
132238384Sjkim					};
133238384Sjkim				};
134238384Sjkim
135238384Sjkim				usart0 {
136238384Sjkim					pinctrl_usart0: usart0-0 {
137296341Sdelphij						atmel,pins =
138296341Sdelphij							<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
139296341Sdelphij							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB5 periph A */
140296341Sdelphij					};
141238384Sjkim
142296341Sdelphij					pinctrl_usart0_rts: usart0_rts-0 {
143296341Sdelphij						atmel,pins =
144296341Sdelphij							<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB26 periph A */
145296341Sdelphij					};
146296341Sdelphij
147296341Sdelphij					pinctrl_usart0_cts: usart0_cts-0 {
148296341Sdelphij						atmel,pins =
149296341Sdelphij							<AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB27 periph A */
150296341Sdelphij					};
151296341Sdelphij
152296341Sdelphij					pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
153238384Sjkim						atmel,pins =
154296341Sdelphij							<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB24 periph A */
155296341Sdelphij							 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB22 periph A */
156296341Sdelphij					};
157296341Sdelphij
158238384Sjkim					pinctrl_usart0_dcd: usart0_dcd-0 {
159296341Sdelphij						atmel,pins =
160296341Sdelphij							<AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB23 periph A */
161296341Sdelphij					};
162296341Sdelphij
163296341Sdelphij					pinctrl_usart0_ri: usart0_ri-0 {
164296341Sdelphij						atmel,pins =
165296341Sdelphij							<AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB25 periph A */
166296341Sdelphij					};
167296341Sdelphij				};
168296341Sdelphij
169296341Sdelphij				usart1 {
170296341Sdelphij					pinctrl_usart1: usart1-0 {
171238384Sjkim						atmel,pins =
172238384Sjkim							<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB6 periph A with pullup */
173238384Sjkim							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB7 periph A */
174296341Sdelphij					};
175296341Sdelphij
176296341Sdelphij					pinctrl_usart1_rts: usart1_rts-0 {
177296341Sdelphij						atmel,pins =
178296341Sdelphij							<AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB28 periph A */
179238384Sjkim					};
180238384Sjkim
181238384Sjkim					pinctrl_usart1_cts: usart1_cts-0 {
182296341Sdelphij						atmel,pins =
183296341Sdelphij							<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB29 periph A */
184296341Sdelphij					};
185296341Sdelphij				};
186238384Sjkim
187296341Sdelphij				usart2 {
188296341Sdelphij					pinctrl_usart2: usart2-0 {
189296341Sdelphij						atmel,pins =
190296341Sdelphij							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB8 periph A with pullup */
191296341Sdelphij							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB9 periph A */
192296341Sdelphij					};
193296341Sdelphij
194296341Sdelphij					pinctrl_usart2_rts: usart2_rts-0 {
195296341Sdelphij						atmel,pins =
196296341Sdelphij							<AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA4 periph A */
197296341Sdelphij					};
198296341Sdelphij
199296341Sdelphij					pinctrl_usart2_cts: usart2_cts-0 {
200296341Sdelphij						atmel,pins =
201296341Sdelphij							<AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA5 periph A */
202296341Sdelphij					};
203238384Sjkim				};
204238384Sjkim
205238384Sjkim				usart3 {
206296341Sdelphij					pinctrl_usart3: usart3-0 {
207296341Sdelphij						atmel,pins =
208296341Sdelphij							<AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB10 periph A with pullup */
209296341Sdelphij							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB11 periph A */
210296341Sdelphij					};
211296341Sdelphij
212238384Sjkim					pinctrl_usart3_rts: usart3_rts-0 {
213296341Sdelphij						atmel,pins =
214296341Sdelphij							<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC8 periph B */
215296341Sdelphij					};
216296341Sdelphij
217238384Sjkim					pinctrl_usart3_cts: usart3_cts-0 {
218238384Sjkim						atmel,pins =
219296341Sdelphij							<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC10 periph B */
220296341Sdelphij					};
221296341Sdelphij				};
222296341Sdelphij
223296341Sdelphij				uart0 {
224296341Sdelphij					pinctrl_uart0: uart0-0 {
225296341Sdelphij						atmel,pins =
226296341Sdelphij							<AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA31 periph B with pullup */
227296341Sdelphij							 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA30 periph B */
228296341Sdelphij					};
229296341Sdelphij				};
230238384Sjkim
231238384Sjkim				uart1 {
232296341Sdelphij					pinctrl_uart1: uart1-0 {
233296341Sdelphij						atmel,pins =
234296341Sdelphij							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB12 periph A with pullup */
235296341Sdelphij							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB13 periph A */
236296341Sdelphij					};
237296341Sdelphij				};
238296341Sdelphij
239296341Sdelphij				nand {
240296341Sdelphij					pinctrl_nand: nand-0 {
241296341Sdelphij						atmel,pins =
242296341Sdelphij							<AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP	/* PC13 gpio RDY pin pull_up */
243238384Sjkim							 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;	/* PC14 gpio enable pin pull_up */
244238384Sjkim					};
245238384Sjkim				};
246296341Sdelphij
247296341Sdelphij				macb {
248296341Sdelphij					pinctrl_macb_rmii: macb_rmii-0 {
249296341Sdelphij						atmel,pins =
250296341Sdelphij							<AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA12 periph A */
251296341Sdelphij							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA13 periph A */
252296341Sdelphij							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA14 periph A */
253296341Sdelphij							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA15 periph A */
254296341Sdelphij							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA16 periph A */
255296341Sdelphij							 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA17 periph A */
256296341Sdelphij							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA18 periph A */
257238384Sjkim							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA19 periph A */
258238384Sjkim							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA20 periph A */
259238384Sjkim							 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA21 periph A */
260296341Sdelphij					};
261296341Sdelphij
262296341Sdelphij					pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
263296341Sdelphij						atmel,pins =
264296341Sdelphij							<AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA22 periph B */
265296341Sdelphij							 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA23 periph B */
266296341Sdelphij							 AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA24 periph B */
267296341Sdelphij							 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA25 periph B */
268296341Sdelphij							 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA26 periph B */
269296341Sdelphij							 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
270296341Sdelphij							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
271238384Sjkim							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA29 periph B */
272238384Sjkim					};
273238384Sjkim
274296341Sdelphij					pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
275296341Sdelphij						atmel,pins =
276296341Sdelphij							<AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA10 periph B */
277296341Sdelphij							 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA11 periph B */
278296341Sdelphij							 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA22 periph B */
279296341Sdelphij							 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA25 periph B */
280296341Sdelphij							 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA26 periph B */
281296341Sdelphij							 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
282296341Sdelphij							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
283296341Sdelphij							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA29 periph B */
284296341Sdelphij					};
285238384Sjkim				};
286238384Sjkim
287238384Sjkim				mmc0 {
288296341Sdelphij					pinctrl_mmc0_clk: mmc0_clk-0 {
289296341Sdelphij						atmel,pins =
290296341Sdelphij							<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA8 periph A */
291296341Sdelphij					};
292296341Sdelphij
293296341Sdelphij					pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
294296341Sdelphij						atmel,pins =
295296341Sdelphij							<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA7 periph A with pullup */
296296341Sdelphij							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA6 periph A with pullup */
297296341Sdelphij					};
298296341Sdelphij
299238384Sjkim					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
300296341Sdelphij						atmel,pins =
301296341Sdelphij							<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA9 periph A with pullup */
302238384Sjkim							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA10 periph A with pullup */
303238384Sjkim							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA11 periph A with pullup */
304238384Sjkim					};
305238384Sjkim
306238384Sjkim					pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
307238384Sjkim						atmel,pins =
308296341Sdelphij							<AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA1 periph B with pullup */
309296341Sdelphij							 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA0 periph B with pullup */
310296341Sdelphij					};
311296341Sdelphij
312238384Sjkim					pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
313296341Sdelphij						atmel,pins =
314296341Sdelphij							<AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA5 periph B with pullup */
315296341Sdelphij							 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA4 periph B with pullup */
316296341Sdelphij							 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA3 periph B with pullup */
317296341Sdelphij					};
318296341Sdelphij				};
319296341Sdelphij
320296341Sdelphij				ssc0 {
321296341Sdelphij					pinctrl_ssc0_tx: ssc0_tx-0 {
322296341Sdelphij						atmel,pins =
323238384Sjkim							<AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
324296341Sdelphij							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB17 periph A */
325296341Sdelphij							 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB18 periph A */
326238384Sjkim					};
327238384Sjkim
328238384Sjkim					pinctrl_ssc0_rx: ssc0_rx-0 {
329238384Sjkim						atmel,pins =
330238384Sjkim							<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB19 periph A */
331238384Sjkim							 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB20 periph A */
332296341Sdelphij							 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB21 periph A */
333296341Sdelphij					};
334296341Sdelphij				};
335296341Sdelphij
336296341Sdelphij				spi0 {
337296341Sdelphij					pinctrl_spi0: spi0-0 {
338238384Sjkim						atmel,pins =
339296341Sdelphij							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA0 periph A SPI0_MISO pin */
340296341Sdelphij							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA1 periph A SPI0_MOSI pin */
341296341Sdelphij							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA2 periph A SPI0_SPCK pin */
342296341Sdelphij					};
343296341Sdelphij				};
344296341Sdelphij
345296341Sdelphij				spi1 {
346296341Sdelphij					pinctrl_spi1: spi1-0 {
347296341Sdelphij						atmel,pins =
348296341Sdelphij							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A SPI1_MISO pin */
349238384Sjkim							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A SPI1_MOSI pin */
350296341Sdelphij							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB2 periph A SPI1_SPCK pin */
351296341Sdelphij					};
352238384Sjkim				};
353238384Sjkim
354238384Sjkim				i2c_gpio0 {
355238384Sjkim					pinctrl_i2c_gpio0: i2c_gpio0-0 {
356238384Sjkim						atmel,pins =
357238384Sjkim							<AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
358296341Sdelphij							 AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
359296341Sdelphij					};
360296341Sdelphij				};
361296341Sdelphij
362296341Sdelphij				tcb0 {
363296341Sdelphij					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
364238384Sjkim						atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
365296341Sdelphij					};
366296341Sdelphij
367296341Sdelphij					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
368296341Sdelphij						atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
369296341Sdelphij					};
370296341Sdelphij
371296341Sdelphij					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
372296341Sdelphij						atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
373296341Sdelphij					};
374296341Sdelphij
375238384Sjkim					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
376296341Sdelphij						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
377296341Sdelphij					};
378238384Sjkim
379238384Sjkim					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
380238384Sjkim						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
381238384Sjkim					};
382238384Sjkim
383238384Sjkim					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
384296341Sdelphij						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
385296341Sdelphij					};
386296341Sdelphij
387296341Sdelphij					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
388296341Sdelphij						atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
389296341Sdelphij					};
390296341Sdelphij
391296341Sdelphij					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
392238384Sjkim						atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
393296341Sdelphij					};
394296341Sdelphij
395296341Sdelphij					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
396296341Sdelphij						atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
397296341Sdelphij					};
398296341Sdelphij				};
399296341Sdelphij
400296341Sdelphij				tcb1 {
401296341Sdelphij					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
402296341Sdelphij						atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
403238384Sjkim					};
404296341Sdelphij
405296341Sdelphij					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
406238384Sjkim						atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
407238384Sjkim					};
408238384Sjkim
409238384Sjkim					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
410238384Sjkim						atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
411238384Sjkim					};
412296341Sdelphij
413296341Sdelphij					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
414296341Sdelphij						atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
415296341Sdelphij					};
416238384Sjkim
417296341Sdelphij					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
418296341Sdelphij						atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
419296341Sdelphij					};
420296341Sdelphij
421296341Sdelphij					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
422296341Sdelphij						atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
423296341Sdelphij					};
424296341Sdelphij
425296341Sdelphij					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
426296341Sdelphij						atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
427238384Sjkim					};
428296341Sdelphij
429296341Sdelphij					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
430296341Sdelphij						atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
431296341Sdelphij					};
432296341Sdelphij
433296341Sdelphij					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
434296341Sdelphij						atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
435296341Sdelphij					};
436296341Sdelphij				};
437296341Sdelphij
438296341Sdelphij				pioA: gpio@fffff400 {
439296341Sdelphij					compatible = "atmel,at91rm9200-gpio";
440296341Sdelphij					reg = <0xfffff400 0x200>;
441296341Sdelphij					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
442296341Sdelphij					#gpio-cells = <2>;
443296341Sdelphij					gpio-controller;
444296341Sdelphij					interrupt-controller;
445296341Sdelphij					#interrupt-cells = <2>;
446238384Sjkim				};
447296341Sdelphij
448296341Sdelphij				pioB: gpio@fffff600 {
449296341Sdelphij					compatible = "atmel,at91rm9200-gpio";
450296341Sdelphij					reg = <0xfffff600 0x200>;
451296341Sdelphij					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
452296341Sdelphij					#gpio-cells = <2>;
453296341Sdelphij					gpio-controller;
454296341Sdelphij					interrupt-controller;
455238384Sjkim					#interrupt-cells = <2>;
456296341Sdelphij				};
457296341Sdelphij
458296341Sdelphij				pioC: gpio@fffff800 {
459296341Sdelphij					compatible = "atmel,at91rm9200-gpio";
460238384Sjkim					reg = <0xfffff800 0x200>;
461296341Sdelphij					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
462296341Sdelphij					#gpio-cells = <2>;
463296341Sdelphij					gpio-controller;
464296341Sdelphij					interrupt-controller;
465238384Sjkim					#interrupt-cells = <2>;
466296341Sdelphij				};
467296341Sdelphij			};
468296341Sdelphij
469238384Sjkim			dbgu: serial@fffff200 {
470296341Sdelphij				compatible = "atmel,at91sam9260-usart";
471296341Sdelphij				reg = <0xfffff200 0x200>;
472296341Sdelphij				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
473238384Sjkim				pinctrl-names = "default";
474296341Sdelphij				pinctrl-0 = <&pinctrl_dbgu>;
475296341Sdelphij				status = "disabled";
476238384Sjkim			};
477296341Sdelphij
478296341Sdelphij			usart0: serial@fffb0000 {
479238384Sjkim				compatible = "atmel,at91sam9260-usart";
480296341Sdelphij				reg = <0xfffb0000 0x200>;
481296341Sdelphij				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
482238384Sjkim				atmel,use-dma-rx;
483296341Sdelphij				atmel,use-dma-tx;
484296341Sdelphij				pinctrl-names = "default";
485296341Sdelphij				pinctrl-0 = <&pinctrl_usart0>;
486238384Sjkim				status = "disabled";
487296341Sdelphij			};
488296341Sdelphij
489238384Sjkim			usart1: serial@fffb4000 {
490238384Sjkim				compatible = "atmel,at91sam9260-usart";
491238384Sjkim				reg = <0xfffb4000 0x200>;
492238384Sjkim				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
493238384Sjkim				atmel,use-dma-rx;
494238384Sjkim				atmel,use-dma-tx;
495238384Sjkim				pinctrl-names = "default";
496296341Sdelphij				pinctrl-0 = <&pinctrl_usart1>;
497296341Sdelphij				status = "disabled";
498296341Sdelphij			};
499238384Sjkim
500296341Sdelphij			usart2: serial@fffb8000 {
501238384Sjkim				compatible = "atmel,at91sam9260-usart";
502296341Sdelphij				reg = <0xfffb8000 0x200>;
503238384Sjkim				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
504296341Sdelphij				atmel,use-dma-rx;
505296341Sdelphij				atmel,use-dma-tx;
506238384Sjkim				pinctrl-names = "default";
507296341Sdelphij				pinctrl-0 = <&pinctrl_usart2>;
508296341Sdelphij				status = "disabled";
509296341Sdelphij			};
510238384Sjkim
511296341Sdelphij			usart3: serial@fffd0000 {
512296341Sdelphij				compatible = "atmel,at91sam9260-usart";
513296341Sdelphij				reg = <0xfffd0000 0x200>;
514296341Sdelphij				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
515238384Sjkim				atmel,use-dma-rx;
516296341Sdelphij				atmel,use-dma-tx;
517296341Sdelphij				pinctrl-names = "default";
518296341Sdelphij				pinctrl-0 = <&pinctrl_usart3>;
519296341Sdelphij				status = "disabled";
520296341Sdelphij			};
521238384Sjkim
522296341Sdelphij			uart0: serial@fffd4000 {
523296341Sdelphij				compatible = "atmel,at91sam9260-usart";
524296341Sdelphij				reg = <0xfffd4000 0x200>;
525296341Sdelphij				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
526296341Sdelphij				atmel,use-dma-rx;
527296341Sdelphij				atmel,use-dma-tx;
528238384Sjkim				pinctrl-names = "default";
529296341Sdelphij				pinctrl-0 = <&pinctrl_uart0>;
530296341Sdelphij				status = "disabled";
531296341Sdelphij			};
532296341Sdelphij
533296341Sdelphij			uart1: serial@fffd8000 {
534296341Sdelphij				compatible = "atmel,at91sam9260-usart";
535296341Sdelphij				reg = <0xfffd8000 0x200>;
536238384Sjkim				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
537296341Sdelphij				atmel,use-dma-rx;
538296341Sdelphij				atmel,use-dma-tx;
539296341Sdelphij				pinctrl-names = "default";
540296341Sdelphij				pinctrl-0 = <&pinctrl_uart1>;
541296341Sdelphij				status = "disabled";
542296341Sdelphij			};
543296341Sdelphij
544296341Sdelphij			macb0: ethernet@fffc4000 {
545238384Sjkim				compatible = "cdns,at32ap7000-macb", "cdns,macb";
546296341Sdelphij				reg = <0xfffc4000 0x100>;
547238384Sjkim				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
548296341Sdelphij				pinctrl-names = "default";
549296341Sdelphij				pinctrl-0 = <&pinctrl_macb_rmii>;
550296341Sdelphij				status = "disabled";
551296341Sdelphij			};
552296341Sdelphij
553296341Sdelphij			usb1: gadget@fffa4000 {
554296341Sdelphij				compatible = "atmel,at91rm9200-udc";
555238384Sjkim				reg = <0xfffa4000 0x4000>;
556296341Sdelphij				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
557296341Sdelphij				status = "disabled";
558296341Sdelphij			};
559296341Sdelphij
560296341Sdelphij			i2c0: i2c@fffac000 {
561296341Sdelphij				compatible = "atmel,at91sam9260-i2c";
562238384Sjkim				reg = <0xfffac000 0x100>;
563296341Sdelphij				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
564296341Sdelphij				#address-cells = <1>;
565296341Sdelphij				#size-cells = <0>;
566296341Sdelphij				status = "disabled";
567296341Sdelphij			};
568238384Sjkim
569296341Sdelphij			mmc0: mmc@fffa8000 {
570296341Sdelphij				compatible = "atmel,hsmci";
571296341Sdelphij				reg = <0xfffa8000 0x600>;
572296341Sdelphij				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
573238384Sjkim				#address-cells = <1>;
574296341Sdelphij				#size-cells = <0>;
575296341Sdelphij				pinctrl-names = "default";
576296341Sdelphij				status = "disabled";
577238384Sjkim			};
578296341Sdelphij
579296341Sdelphij			ssc0: ssc@fffbc000 {
580238384Sjkim				compatible = "atmel,at91rm9200-ssc";
581296341Sdelphij				reg = <0xfffbc000 0x4000>;
582296341Sdelphij				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
583238384Sjkim				pinctrl-names = "default";
584296341Sdelphij				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
585296341Sdelphij				status = "disabled";
586238384Sjkim			};
587238384Sjkim
588238384Sjkim			spi0: spi@fffc8000 {
589296341Sdelphij				#address-cells = <1>;
590296341Sdelphij				#size-cells = <0>;
591238384Sjkim				compatible = "atmel,at91rm9200-spi";
592238384Sjkim				reg = <0xfffc8000 0x200>;
593238384Sjkim				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
594238384Sjkim				pinctrl-names = "default";
595238384Sjkim				pinctrl-0 = <&pinctrl_spi0>;
596238384Sjkim				status = "disabled";
597296341Sdelphij			};
598296341Sdelphij
599238384Sjkim			spi1: spi@fffcc000 {
600296341Sdelphij				#address-cells = <1>;
601296341Sdelphij				#size-cells = <0>;
602296341Sdelphij				compatible = "atmel,at91rm9200-spi";
603296341Sdelphij				reg = <0xfffcc000 0x200>;
604296341Sdelphij				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
605296341Sdelphij				pinctrl-names = "default";
606296341Sdelphij				pinctrl-0 = <&pinctrl_spi1>;
607296341Sdelphij				status = "disabled";
608296341Sdelphij			};
609238384Sjkim
610296341Sdelphij			adc0: adc@fffe0000 {
611238384Sjkim				compatible = "atmel,at91sam9260-adc";
612296341Sdelphij				reg = <0xfffe0000 0x100>;
613296341Sdelphij				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
614296341Sdelphij				atmel,adc-use-external-triggers;
615296341Sdelphij				atmel,adc-channels-used = <0xf>;
616296341Sdelphij				atmel,adc-vref = <3300>;
617296341Sdelphij				atmel,adc-num-channels = <4>;
618296341Sdelphij				atmel,adc-startup-time = <15>;
619238384Sjkim				atmel,adc-channel-base = <0x30>;
620296341Sdelphij				atmel,adc-drdy-mask = <0x10000>;
621296341Sdelphij				atmel,adc-status-register = <0x1c>;
622296341Sdelphij				atmel,adc-trigger-register = <0x04>;
623238384Sjkim				atmel,adc-res = <8 10>;
624296341Sdelphij				atmel,adc-res-names = "lowres", "highres";
625296341Sdelphij				atmel,adc-use-res = "highres";
626296341Sdelphij
627238384Sjkim				trigger@0 {
628296341Sdelphij					trigger-name = "timer-counter-0";
629296341Sdelphij					trigger-value = <0x1>;
630296341Sdelphij				};
631238384Sjkim				trigger@1 {
632296341Sdelphij					trigger-name = "timer-counter-1";
633296341Sdelphij					trigger-value = <0x3>;
634296341Sdelphij				};
635238384Sjkim
636296341Sdelphij				trigger@2 {
637296341Sdelphij					trigger-name = "timer-counter-2";
638296341Sdelphij					trigger-value = <0x5>;
639238384Sjkim				};
640296341Sdelphij
641296341Sdelphij				trigger@3 {
642296341Sdelphij					trigger-name = "external";
643238384Sjkim					trigger-value = <0x13>;
644296341Sdelphij					trigger-external;
645296341Sdelphij				};
646296341Sdelphij			};
647296341Sdelphij
648296341Sdelphij			watchdog@fffffd40 {
649296341Sdelphij				compatible = "atmel,at91sam9260-wdt";
650296341Sdelphij				reg = <0xfffffd40 0x10>;
651238384Sjkim				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
652296341Sdelphij				atmel,watchdog-type = "hardware";
653296341Sdelphij				atmel,reset-type = "all";
654296341Sdelphij				atmel,dbg-halt;
655238384Sjkim				atmel,idle-halt;
656296341Sdelphij				status = "disabled";
657296341Sdelphij			};
658238384Sjkim		};
659296341Sdelphij
660296341Sdelphij		nand0: nand@40000000 {
661238384Sjkim			compatible = "atmel,at91rm9200-nand";
662296341Sdelphij			#address-cells = <1>;
663296341Sdelphij			#size-cells = <1>;
664296341Sdelphij			reg = <0x40000000 0x10000000
665296341Sdelphij			       0xffffe800 0x200
666296341Sdelphij			      >;
667296341Sdelphij			atmel,nand-addr-offset = <21>;
668296341Sdelphij			atmel,nand-cmd-offset = <22>;
669296341Sdelphij			pinctrl-names = "default";
670238384Sjkim			pinctrl-0 = <&pinctrl_nand>;
671238384Sjkim			gpios = <&pioC 13 GPIO_ACTIVE_HIGH
672296341Sdelphij				 &pioC 14 GPIO_ACTIVE_HIGH
673296341Sdelphij				 0
674296341Sdelphij				>;
675296341Sdelphij			status = "disabled";
676296341Sdelphij		};
677238384Sjkim
678238384Sjkim		usb0: ohci@00500000 {
679296341Sdelphij			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
680296341Sdelphij			reg = <0x00500000 0x100000>;
681296341Sdelphij			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
682296341Sdelphij			status = "disabled";
683296341Sdelphij		};
684238384Sjkim	};
685296341Sdelphij
686296341Sdelphij	i2c@0 {
687238384Sjkim		compatible = "i2c-gpio";
688238384Sjkim		gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
689238384Sjkim			 &pioA 24 GPIO_ACTIVE_HIGH /* scl */
690238384Sjkim			>;
691238384Sjkim		i2c-gpio,sda-open-drain;
692238384Sjkim		i2c-gpio,scl-open-drain;
693238384Sjkim		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
694296341Sdelphij		#address-cells = <1>;
695296341Sdelphij		#size-cells = <0>;
696296341Sdelphij		pinctrl-names = "default";
697296341Sdelphij		pinctrl-0 = <&pinctrl_i2c_gpio0>;
698238384Sjkim		status = "disabled";
699296341Sdelphij	};
700296341Sdelphij};
701296341Sdelphij