1/* 2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC 3 * 4 * Copyright (C) 2011 Atmel, 5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>, 6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 * 8 * Licensed under GPLv2 or later. 9 */ 10 11#include "skeleton.dtsi" 12#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/clock/at91.h> 16 17/ { 18 model = "Atmel AT91SAM9260 family SoC"; 19 compatible = "atmel,at91sam9260"; 20 interrupt-parent = <&aic>; 21 22 aliases { 23 serial0 = &dbgu; 24 serial1 = &usart0; 25 serial2 = &usart1; 26 serial3 = &usart2; 27 serial4 = &usart3; 28 serial5 = &uart0; 29 serial6 = &uart1; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 tcb0 = &tcb0; 34 tcb1 = &tcb1; 35 i2c0 = &i2c0; 36 ssc0 = &ssc0; 37 }; 38 cpus { 39 #address-cells = <0>; 40 #size-cells = <0>; 41 42 cpu { 43 compatible = "arm,arm926ej-s"; 44 device_type = "cpu"; 45 }; 46 }; 47 48 memory { 49 reg = <0x20000000 0x04000000>; 50 }; 51 52 clocks { 53 slow_xtal: slow_xtal { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <0>; 57 }; 58 59 main_xtal: main_xtal { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <0>; 63 }; 64 65 adc_op_clk: adc_op_clk{ 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <5000000>; 69 }; 70 }; 71 72 sram0: sram@002ff000 { 73 compatible = "mmio-sram"; 74 reg = <0x002ff000 0x2000>; 75 }; 76 77 ahb { 78 compatible = "simple-bus"; 79 #address-cells = <1>; 80 #size-cells = <1>; 81 ranges; 82 83 apb { 84 compatible = "simple-bus"; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges; 88 89 aic: interrupt-controller@fffff000 { 90 #interrupt-cells = <3>; 91 compatible = "atmel,at91rm9200-aic"; 92 interrupt-controller; 93 reg = <0xfffff000 0x200>; 94 atmel,external-irqs = <29 30 31>; 95 }; 96 97 ramc0: ramc@ffffea00 { 98 compatible = "atmel,at91sam9260-sdramc"; 99 reg = <0xffffea00 0x200>; 100 }; 101 102 pmc: pmc@fffffc00 { 103 compatible = "atmel,at91sam9260-pmc"; 104 reg = <0xfffffc00 0x100>; 105 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 106 interrupt-controller; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 #interrupt-cells = <1>; 110 111 main_osc: main_osc { 112 compatible = "atmel,at91rm9200-clk-main-osc"; 113 #clock-cells = <0>; 114 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 115 clocks = <&main_xtal>; 116 }; 117 118 main: mainck { 119 compatible = "atmel,at91rm9200-clk-main"; 120 #clock-cells = <0>; 121 clocks = <&main_osc>; 122 }; 123 124 slow_rc_osc: slow_rc_osc { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <32768>; 128 clock-accuracy = <50000000>; 129 }; 130 131 clk32k: slck { 132 compatible = "atmel,at91sam9260-clk-slow"; 133 #clock-cells = <0>; 134 clocks = <&slow_rc_osc>, <&slow_xtal>; 135 }; 136 137 plla: pllack { 138 compatible = "atmel,at91rm9200-clk-pll"; 139 #clock-cells = <0>; 140 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 141 clocks = <&main>; 142 reg = <0>; 143 atmel,clk-input-range = <1000000 32000000>; 144 #atmel,pll-clk-output-range-cells = <4>; 145 atmel,pll-clk-output-ranges = <80000000 160000000 0 1>, 146 <150000000 240000000 2 1>; 147 }; 148 149 pllb: pllbck { 150 compatible = "atmel,at91rm9200-clk-pll"; 151 #clock-cells = <0>; 152 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 153 clocks = <&main>; 154 reg = <1>; 155 atmel,clk-input-range = <1000000 5000000>; 156 #atmel,pll-clk-output-range-cells = <4>; 157 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; 158 }; 159 160 mck: masterck { 161 compatible = "atmel,at91rm9200-clk-master"; 162 #clock-cells = <0>; 163 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 164 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; 165 atmel,clk-output-range = <0 105000000>; 166 atmel,clk-divisors = <1 2 4 0>; 167 }; 168 169 usb: usbck { 170 compatible = "atmel,at91rm9200-clk-usb"; 171 #clock-cells = <0>; 172 atmel,clk-divisors = <1 2 4 0>; 173 clocks = <&pllb>; 174 }; 175 176 prog: progck { 177 compatible = "atmel,at91rm9200-clk-programmable"; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 interrupt-parent = <&pmc>; 181 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; 182 183 prog0: prog0 { 184 #clock-cells = <0>; 185 reg = <0>; 186 interrupts = <AT91_PMC_PCKRDY(0)>; 187 }; 188 189 prog1: prog1 { 190 #clock-cells = <0>; 191 reg = <1>; 192 interrupts = <AT91_PMC_PCKRDY(1)>; 193 }; 194 }; 195 196 systemck { 197 compatible = "atmel,at91rm9200-clk-system"; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 201 uhpck: uhpck { 202 #clock-cells = <0>; 203 reg = <6>; 204 clocks = <&usb>; 205 }; 206 207 udpck: udpck { 208 #clock-cells = <0>; 209 reg = <7>; 210 clocks = <&usb>; 211 }; 212 213 pck0: pck0 { 214 #clock-cells = <0>; 215 reg = <8>; 216 clocks = <&prog0>; 217 }; 218 219 pck1: pck1 { 220 #clock-cells = <0>; 221 reg = <9>; 222 clocks = <&prog1>; 223 }; 224 }; 225 226 periphck { 227 compatible = "atmel,at91rm9200-clk-peripheral"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 clocks = <&mck>; 231 232 pioA_clk: pioA_clk { 233 #clock-cells = <0>; 234 reg = <2>; 235 }; 236 237 pioB_clk: pioB_clk { 238 #clock-cells = <0>; 239 reg = <3>; 240 }; 241 242 pioC_clk: pioC_clk { 243 #clock-cells = <0>; 244 reg = <4>; 245 }; 246 247 adc_clk: adc_clk { 248 #clock-cells = <0>; 249 reg = <5>; 250 }; 251 252 usart0_clk: usart0_clk { 253 #clock-cells = <0>; 254 reg = <6>; 255 }; 256 257 usart1_clk: usart1_clk { 258 #clock-cells = <0>; 259 reg = <7>; 260 }; 261 262 usart2_clk: usart2_clk { 263 #clock-cells = <0>; 264 reg = <8>; 265 }; 266 267 mci0_clk: mci0_clk { 268 #clock-cells = <0>; 269 reg = <9>; 270 }; 271 272 udc_clk: udc_clk { 273 #clock-cells = <0>; 274 reg = <10>; 275 }; 276 277 twi0_clk: twi0_clk { 278 reg = <11>; 279 #clock-cells = <0>; 280 }; 281 282 spi0_clk: spi0_clk { 283 #clock-cells = <0>; 284 reg = <12>; 285 }; 286 287 spi1_clk: spi1_clk { 288 #clock-cells = <0>; 289 reg = <13>; 290 }; 291 292 ssc0_clk: ssc0_clk { 293 #clock-cells = <0>; 294 reg = <14>; 295 }; 296 297 tc0_clk: tc0_clk { 298 #clock-cells = <0>; 299 reg = <17>; 300 }; 301 302 tc1_clk: tc1_clk { 303 #clock-cells = <0>; 304 reg = <18>; 305 }; 306 307 tc2_clk: tc2_clk { 308 #clock-cells = <0>; 309 reg = <19>; 310 }; 311 312 ohci_clk: ohci_clk { 313 #clock-cells = <0>; 314 reg = <20>; 315 }; 316 317 macb0_clk: macb0_clk { 318 #clock-cells = <0>; 319 reg = <21>; 320 }; 321 322 isi_clk: isi_clk { 323 #clock-cells = <0>; 324 reg = <22>; 325 }; 326 327 usart3_clk: usart3_clk { 328 #clock-cells = <0>; 329 reg = <23>; 330 }; 331 332 uart0_clk: uart0_clk { 333 #clock-cells = <0>; 334 reg = <24>; 335 }; 336 337 uart1_clk: uart1_clk { 338 #clock-cells = <0>; 339 reg = <25>; 340 }; 341 342 tc3_clk: tc3_clk { 343 #clock-cells = <0>; 344 reg = <26>; 345 }; 346 347 tc4_clk: tc4_clk { 348 #clock-cells = <0>; 349 reg = <27>; 350 }; 351 352 tc5_clk: tc5_clk { 353 #clock-cells = <0>; 354 reg = <28>; 355 }; 356 }; 357 }; 358 359 rstc@fffffd00 { 360 compatible = "atmel,at91sam9260-rstc"; 361 reg = <0xfffffd00 0x10>; 362 }; 363 364 shdwc@fffffd10 { 365 compatible = "atmel,at91sam9260-shdwc"; 366 reg = <0xfffffd10 0x10>; 367 }; 368 369 pit: timer@fffffd30 { 370 compatible = "atmel,at91sam9260-pit"; 371 reg = <0xfffffd30 0xf>; 372 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 373 clocks = <&mck>; 374 }; 375 376 tcb0: timer@fffa0000 { 377 compatible = "atmel,at91rm9200-tcb"; 378 reg = <0xfffa0000 0x100>; 379 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 380 18 IRQ_TYPE_LEVEL_HIGH 0 381 19 IRQ_TYPE_LEVEL_HIGH 0>; 382 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; 383 clock-names = "t0_clk", "t1_clk", "t2_clk"; 384 }; 385 386 tcb1: timer@fffdc000 { 387 compatible = "atmel,at91rm9200-tcb"; 388 reg = <0xfffdc000 0x100>; 389 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 390 27 IRQ_TYPE_LEVEL_HIGH 0 391 28 IRQ_TYPE_LEVEL_HIGH 0>; 392 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; 393 clock-names = "t0_clk", "t1_clk", "t2_clk"; 394 }; 395 396 pinctrl@fffff400 { 397 #address-cells = <1>; 398 #size-cells = <1>; 399 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 400 ranges = <0xfffff400 0xfffff400 0x600>; 401 402 atmel,mux-mask = < 403 /* A B */ 404 0xffffffff 0xffc00c3b /* pioA */ 405 0xffffffff 0x7fff3ccf /* pioB */ 406 0xffffffff 0x007fffff /* pioC */ 407 >; 408 409 /* shared pinctrl settings */ 410 dbgu { 411 pinctrl_dbgu: dbgu-0 { 412 atmel,pins = 413 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ 414 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */ 415 }; 416 }; 417 418 usart0 { 419 pinctrl_usart0: usart0-0 { 420 atmel,pins = 421 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ 422 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ 423 }; 424 425 pinctrl_usart0_rts: usart0_rts-0 { 426 atmel,pins = 427 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ 428 }; 429 430 pinctrl_usart0_cts: usart0_cts-0 { 431 atmel,pins = 432 <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */ 433 }; 434 435 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { 436 atmel,pins = 437 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */ 438 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */ 439 }; 440 441 pinctrl_usart0_dcd: usart0_dcd-0 { 442 atmel,pins = 443 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ 444 }; 445 446 pinctrl_usart0_ri: usart0_ri-0 { 447 atmel,pins = 448 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ 449 }; 450 }; 451 452 usart1 { 453 pinctrl_usart1: usart1-0 { 454 atmel,pins = 455 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ 456 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ 457 }; 458 459 pinctrl_usart1_rts: usart1_rts-0 { 460 atmel,pins = 461 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */ 462 }; 463 464 pinctrl_usart1_cts: usart1_cts-0 { 465 atmel,pins = 466 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */ 467 }; 468 }; 469 470 usart2 { 471 pinctrl_usart2: usart2-0 { 472 atmel,pins = 473 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */ 474 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */ 475 }; 476 477 pinctrl_usart2_rts: usart2_rts-0 { 478 atmel,pins = 479 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ 480 }; 481 482 pinctrl_usart2_cts: usart2_cts-0 { 483 atmel,pins = 484 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ 485 }; 486 }; 487 488 usart3 { 489 pinctrl_usart3: usart3-0 { 490 atmel,pins = 491 <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */ 492 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ 493 }; 494 495 pinctrl_usart3_rts: usart3_rts-0 { 496 atmel,pins = 497 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */ 498 }; 499 500 pinctrl_usart3_cts: usart3_cts-0 { 501 atmel,pins = 502 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */ 503 }; 504 }; 505 506 uart0 { 507 pinctrl_uart0: uart0-0 { 508 atmel,pins = 509 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */ 510 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ 511 }; 512 }; 513 514 uart1 { 515 pinctrl_uart1: uart1-0 { 516 atmel,pins = 517 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */ 518 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ 519 }; 520 }; 521 522 nand { 523 pinctrl_nand: nand-0 { 524 atmel,pins = 525 <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */ 526 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ 527 }; 528 }; 529 530 macb { 531 pinctrl_macb_rmii: macb_rmii-0 { 532 atmel,pins = 533 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ 534 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ 535 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ 536 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ 537 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ 538 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ 539 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ 540 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */ 541 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */ 542 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ 543 }; 544 545 pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 546 atmel,pins = 547 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ 548 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */ 549 AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ 550 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ 551 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ 552 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 553 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 554 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ 555 }; 556 557 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { 558 atmel,pins = 559 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */ 560 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */ 561 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ 562 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ 563 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ 564 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 565 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 566 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ 567 }; 568 }; 569 570 mmc0 { 571 pinctrl_mmc0_clk: mmc0_clk-0 { 572 atmel,pins = 573 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ 574 }; 575 576 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { 577 atmel,pins = 578 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ 579 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */ 580 }; 581 582 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 583 atmel,pins = 584 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ 585 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ 586 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ 587 }; 588 589 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { 590 atmel,pins = 591 <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */ 592 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */ 593 }; 594 595 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { 596 atmel,pins = 597 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ 598 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */ 599 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */ 600 }; 601 }; 602 603 ssc0 { 604 pinctrl_ssc0_tx: ssc0_tx-0 { 605 atmel,pins = 606 <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ 607 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */ 608 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ 609 }; 610 611 pinctrl_ssc0_rx: ssc0_rx-0 { 612 atmel,pins = 613 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ 614 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */ 615 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ 616 }; 617 }; 618 619 spi0 { 620 pinctrl_spi0: spi0-0 { 621 atmel,pins = 622 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ 623 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ 624 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ 625 }; 626 }; 627 628 spi1 { 629 pinctrl_spi1: spi1-0 { 630 atmel,pins = 631 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */ 632 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */ 633 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */ 634 }; 635 }; 636 637 i2c_gpio0 { 638 pinctrl_i2c_gpio0: i2c_gpio0-0 { 639 atmel,pins = 640 <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE 641 AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; 642 }; 643 }; 644 645 tcb0 { 646 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 647 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; 648 }; 649 650 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 651 atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; 652 }; 653 654 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 655 atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; 656 }; 657 658 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 659 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 660 }; 661 662 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 663 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 664 }; 665 666 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 667 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 668 }; 669 670 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 671 atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 672 }; 673 674 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 675 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; 676 }; 677 678 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 679 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; 680 }; 681 }; 682 683 tcb1 { 684 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 685 atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; 686 }; 687 688 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 689 atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; 690 }; 691 692 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 693 atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; 694 }; 695 696 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 697 atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; 698 }; 699 700 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 701 atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 702 }; 703 704 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 705 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 706 }; 707 708 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 709 atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; 710 }; 711 712 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 713 atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 714 }; 715 716 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 717 atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; 718 }; 719 }; 720 721 pioA: gpio@fffff400 { 722 compatible = "atmel,at91rm9200-gpio"; 723 reg = <0xfffff400 0x200>; 724 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 725 #gpio-cells = <2>; 726 gpio-controller; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 clocks = <&pioA_clk>; 730 }; 731 732 pioB: gpio@fffff600 { 733 compatible = "atmel,at91rm9200-gpio"; 734 reg = <0xfffff600 0x200>; 735 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 736 #gpio-cells = <2>; 737 gpio-controller; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 clocks = <&pioB_clk>; 741 }; 742 743 pioC: gpio@fffff800 { 744 compatible = "atmel,at91rm9200-gpio"; 745 reg = <0xfffff800 0x200>; 746 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 747 #gpio-cells = <2>; 748 gpio-controller; 749 interrupt-controller; 750 #interrupt-cells = <2>; 751 clocks = <&pioC_clk>; 752 }; 753 }; 754 755 dbgu: serial@fffff200 { 756 compatible = "atmel,at91sam9260-usart"; 757 reg = <0xfffff200 0x200>; 758 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 759 pinctrl-names = "default"; 760 pinctrl-0 = <&pinctrl_dbgu>; 761 clocks = <&mck>; 762 clock-names = "usart"; 763 status = "disabled"; 764 }; 765 766 usart0: serial@fffb0000 { 767 compatible = "atmel,at91sam9260-usart"; 768 reg = <0xfffb0000 0x200>; 769 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 770 atmel,use-dma-rx; 771 atmel,use-dma-tx; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&pinctrl_usart0>; 774 clocks = <&usart0_clk>; 775 clock-names = "usart"; 776 status = "disabled"; 777 }; 778 779 usart1: serial@fffb4000 { 780 compatible = "atmel,at91sam9260-usart"; 781 reg = <0xfffb4000 0x200>; 782 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 783 atmel,use-dma-rx; 784 atmel,use-dma-tx; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&pinctrl_usart1>; 787 clocks = <&usart1_clk>; 788 clock-names = "usart"; 789 status = "disabled"; 790 }; 791 792 usart2: serial@fffb8000 { 793 compatible = "atmel,at91sam9260-usart"; 794 reg = <0xfffb8000 0x200>; 795 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 796 atmel,use-dma-rx; 797 atmel,use-dma-tx; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_usart2>; 800 clocks = <&usart2_clk>; 801 clock-names = "usart"; 802 status = "disabled"; 803 }; 804 805 usart3: serial@fffd0000 { 806 compatible = "atmel,at91sam9260-usart"; 807 reg = <0xfffd0000 0x200>; 808 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; 809 atmel,use-dma-rx; 810 atmel,use-dma-tx; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&pinctrl_usart3>; 813 clocks = <&usart3_clk>; 814 clock-names = "usart"; 815 status = "disabled"; 816 }; 817 818 uart0: serial@fffd4000 { 819 compatible = "atmel,at91sam9260-usart"; 820 reg = <0xfffd4000 0x200>; 821 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; 822 atmel,use-dma-rx; 823 atmel,use-dma-tx; 824 pinctrl-names = "default"; 825 pinctrl-0 = <&pinctrl_uart0>; 826 clocks = <&uart0_clk>; 827 clock-names = "usart"; 828 status = "disabled"; 829 }; 830 831 uart1: serial@fffd8000 { 832 compatible = "atmel,at91sam9260-usart"; 833 reg = <0xfffd8000 0x200>; 834 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; 835 atmel,use-dma-rx; 836 atmel,use-dma-tx; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&pinctrl_uart1>; 839 clocks = <&uart1_clk>; 840 clock-names = "usart"; 841 status = "disabled"; 842 }; 843 844 macb0: ethernet@fffc4000 { 845 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 846 reg = <0xfffc4000 0x100>; 847 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; 848 pinctrl-names = "default"; 849 pinctrl-0 = <&pinctrl_macb_rmii>; 850 clocks = <&macb0_clk>, <&macb0_clk>; 851 clock-names = "hclk", "pclk"; 852 status = "disabled"; 853 }; 854 855 usb1: gadget@fffa4000 { 856 compatible = "atmel,at91rm9200-udc"; 857 reg = <0xfffa4000 0x4000>; 858 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 859 clocks = <&udc_clk>, <&udpck>; 860 clock-names = "pclk", "hclk"; 861 status = "disabled"; 862 }; 863 864 i2c0: i2c@fffac000 { 865 compatible = "atmel,at91sam9260-i2c"; 866 reg = <0xfffac000 0x100>; 867 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 clocks = <&twi0_clk>; 871 status = "disabled"; 872 }; 873 874 mmc0: mmc@fffa8000 { 875 compatible = "atmel,hsmci"; 876 reg = <0xfffa8000 0x600>; 877 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 pinctrl-names = "default"; 881 clocks = <&mci0_clk>; 882 clock-names = "mci_clk"; 883 status = "disabled"; 884 }; 885 886 ssc0: ssc@fffbc000 { 887 compatible = "atmel,at91rm9200-ssc"; 888 reg = <0xfffbc000 0x4000>; 889 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 892 clocks = <&ssc0_clk>; 893 clock-names = "pclk"; 894 status = "disabled"; 895 }; 896 897 spi0: spi@fffc8000 { 898 #address-cells = <1>; 899 #size-cells = <0>; 900 compatible = "atmel,at91rm9200-spi"; 901 reg = <0xfffc8000 0x200>; 902 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&pinctrl_spi0>; 905 clocks = <&spi0_clk>; 906 clock-names = "spi_clk"; 907 status = "disabled"; 908 }; 909 910 spi1: spi@fffcc000 { 911 #address-cells = <1>; 912 #size-cells = <0>; 913 compatible = "atmel,at91rm9200-spi"; 914 reg = <0xfffcc000 0x200>; 915 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&pinctrl_spi1>; 918 clocks = <&spi1_clk>; 919 clock-names = "spi_clk"; 920 status = "disabled"; 921 }; 922 923 adc0: adc@fffe0000 { 924 #address-cells = <1>; 925 #size-cells = <0>; 926 compatible = "atmel,at91sam9260-adc"; 927 reg = <0xfffe0000 0x100>; 928 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; 929 clocks = <&adc_clk>, <&adc_op_clk>; 930 clock-names = "adc_clk", "adc_op_clk"; 931 atmel,adc-use-external-triggers; 932 atmel,adc-channels-used = <0xf>; 933 atmel,adc-vref = <3300>; 934 atmel,adc-startup-time = <15>; 935 atmel,adc-res = <8 10>; 936 atmel,adc-res-names = "lowres", "highres"; 937 atmel,adc-use-res = "highres"; 938 939 trigger@0 { 940 reg = <0>; 941 trigger-name = "timer-counter-0"; 942 trigger-value = <0x1>; 943 }; 944 trigger@1 { 945 reg = <1>; 946 trigger-name = "timer-counter-1"; 947 trigger-value = <0x3>; 948 }; 949 950 trigger@2 { 951 reg = <2>; 952 trigger-name = "timer-counter-2"; 953 trigger-value = <0x5>; 954 }; 955 956 trigger@3 { 957 reg = <3>; 958 trigger-name = "external"; 959 trigger-value = <0xd>; 960 trigger-external; 961 }; 962 }; 963 964 rtc@fffffd20 { 965 compatible = "atmel,at91sam9260-rtt"; 966 reg = <0xfffffd20 0x10>; 967 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 968 clocks = <&clk32k>; 969 status = "disabled"; 970 }; 971 972 watchdog@fffffd40 { 973 compatible = "atmel,at91sam9260-wdt"; 974 reg = <0xfffffd40 0x10>; 975 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 976 atmel,watchdog-type = "hardware"; 977 atmel,reset-type = "all"; 978 atmel,dbg-halt; 979 atmel,idle-halt; 980 status = "disabled"; 981 }; 982 983 gpbr: syscon@fffffd50 { 984 compatible = "atmel,at91sam9260-gpbr", "syscon"; 985 reg = <0xfffffd50 0x10>; 986 status = "disabled"; 987 }; 988 }; 989 990 nand0: nand@40000000 { 991 compatible = "atmel,at91rm9200-nand"; 992 #address-cells = <1>; 993 #size-cells = <1>; 994 reg = <0x40000000 0x10000000 995 0xffffe800 0x200 996 >; 997 atmel,nand-addr-offset = <21>; 998 atmel,nand-cmd-offset = <22>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&pinctrl_nand>; 1001 gpios = <&pioC 13 GPIO_ACTIVE_HIGH 1002 &pioC 14 GPIO_ACTIVE_HIGH 1003 0 1004 >; 1005 status = "disabled"; 1006 }; 1007 1008 usb0: ohci@00500000 { 1009 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1010 reg = <0x00500000 0x100000>; 1011 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; 1012 clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; 1013 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; 1014 status = "disabled"; 1015 }; 1016 }; 1017 1018 i2c@0 { 1019 compatible = "i2c-gpio"; 1020 gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ 1021 &pioA 24 GPIO_ACTIVE_HIGH /* scl */ 1022 >; 1023 i2c-gpio,sda-open-drain; 1024 i2c-gpio,scl-open-drain; 1025 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&pinctrl_i2c_gpio0>; 1030 status = "disabled"; 1031 }; 1032}; 1033