1/* $FreeBSD: releng/10.3/sys/dev/usb/controller/xhci.c 290331 2015-11-03 10:24:54Z hselasky $ */ 2/*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36/* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43#ifdef USB_GLOBAL_INCLUDE_FILE 44#include USB_GLOBAL_INCLUDE_FILE 45#else 46#include <sys/stdint.h> 47#include <sys/stddef.h> 48#include <sys/param.h> 49#include <sys/queue.h> 50#include <sys/types.h> 51#include <sys/systm.h> 52#include <sys/kernel.h> 53#include <sys/bus.h> 54#include <sys/module.h> 55#include <sys/lock.h> 56#include <sys/mutex.h> 57#include <sys/condvar.h> 58#include <sys/sysctl.h> 59#include <sys/sx.h> 60#include <sys/unistd.h> 61#include <sys/callout.h> 62#include <sys/malloc.h> 63#include <sys/priv.h> 64 65#include <dev/usb/usb.h> 66#include <dev/usb/usbdi.h> 67 68#define USB_DEBUG_VAR xhcidebug 69 70#include <dev/usb/usb_core.h> 71#include <dev/usb/usb_debug.h> 72#include <dev/usb/usb_busdma.h> 73#include <dev/usb/usb_process.h> 74#include <dev/usb/usb_transfer.h> 75#include <dev/usb/usb_device.h> 76#include <dev/usb/usb_hub.h> 77#include <dev/usb/usb_util.h> 78 79#include <dev/usb/usb_controller.h> 80#include <dev/usb/usb_bus.h> 81#endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83#include <dev/usb/controller/xhci.h> 84#include <dev/usb/controller/xhcireg.h> 85 86#define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92static int xhcistreams; 93SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 96 97#ifdef USB_DEBUG 98static int xhcidebug; 99static int xhciroute; 100static int xhcipolling; 101static int xhcidma32; 102 103SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 104 &xhcidebug, 0, "Debug level"); 105TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 106SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 107 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 108TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 109SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN, 110 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 111TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 112SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 113 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 114TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32); 115#else 116#define xhciroute 0 117#define xhcidma32 0 118#endif 119 120#define XHCI_INTR_ENDPT 1 121 122struct xhci_std_temp { 123 struct xhci_softc *sc; 124 struct usb_page_cache *pc; 125 struct xhci_td *td; 126 struct xhci_td *td_next; 127 uint32_t len; 128 uint32_t offset; 129 uint32_t max_packet_size; 130 uint32_t average; 131 uint16_t isoc_delta; 132 uint16_t isoc_frame; 133 uint8_t shortpkt; 134 uint8_t multishort; 135 uint8_t last_frame; 136 uint8_t trb_type; 137 uint8_t direction; 138 uint8_t tbc; 139 uint8_t tlbpc; 140 uint8_t step_td; 141 uint8_t do_isoc_sync; 142}; 143 144static void xhci_do_poll(struct usb_bus *); 145static void xhci_device_done(struct usb_xfer *, usb_error_t); 146static void xhci_root_intr(struct xhci_softc *); 147static void xhci_free_device_ext(struct usb_device *); 148static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 149 struct usb_endpoint_descriptor *); 150static usb_proc_callback_t xhci_configure_msg; 151static usb_error_t xhci_configure_device(struct usb_device *); 152static usb_error_t xhci_configure_endpoint(struct usb_device *, 153 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 154 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 155 uint8_t); 156static usb_error_t xhci_configure_mask(struct usb_device *, 157 uint32_t, uint8_t); 158static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 159 uint64_t, uint8_t); 160static void xhci_endpoint_doorbell(struct usb_xfer *); 161static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 162static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 163static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 164#ifdef USB_DEBUG 165static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 166#endif 167 168extern struct usb_bus_methods xhci_bus_methods; 169 170#ifdef USB_DEBUG 171static void 172xhci_dump_trb(struct xhci_trb *trb) 173{ 174 DPRINTFN(5, "trb = %p\n", trb); 175 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 176 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 177 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 178} 179 180static void 181xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 182{ 183 DPRINTFN(5, "pep = %p\n", pep); 184 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 185 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 186 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 187 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 188 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 189 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 190 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 191} 192 193static void 194xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 195{ 196 DPRINTFN(5, "psl = %p\n", psl); 197 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 198 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 199 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 200 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 201} 202#endif 203 204uint8_t 205xhci_use_polling(void) 206{ 207#ifdef USB_DEBUG 208 return (xhcipolling != 0); 209#else 210 return (0); 211#endif 212} 213 214static void 215xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 216{ 217 struct xhci_softc *sc = XHCI_BUS2SC(bus); 218 uint8_t i; 219 220 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 221 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 222 223 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 224 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 225 226 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 227 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 228 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 229 } 230} 231 232static void 233xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 234{ 235 if (sc->sc_ctx_is_64_byte) { 236 uint32_t offset; 237 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 238 /* all contexts are initially 32-bytes */ 239 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 240 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 241 } 242 *ptr = htole32(val); 243} 244 245static uint32_t 246xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 247{ 248 if (sc->sc_ctx_is_64_byte) { 249 uint32_t offset; 250 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 251 /* all contexts are initially 32-bytes */ 252 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 253 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 254 } 255 return (le32toh(*ptr)); 256} 257 258static void 259xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 260{ 261 if (sc->sc_ctx_is_64_byte) { 262 uint32_t offset; 263 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 264 /* all contexts are initially 32-bytes */ 265 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 266 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 267 } 268 *ptr = htole64(val); 269} 270 271#ifdef USB_DEBUG 272static uint64_t 273xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 274{ 275 if (sc->sc_ctx_is_64_byte) { 276 uint32_t offset; 277 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 278 /* all contexts are initially 32-bytes */ 279 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 280 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 281 } 282 return (le64toh(*ptr)); 283} 284#endif 285 286static int 287xhci_reset_command_queue_locked(struct xhci_softc *sc) 288{ 289 struct usb_page_search buf_res; 290 struct xhci_hw_root *phwr; 291 uint64_t addr; 292 uint32_t temp; 293 294 DPRINTF("\n"); 295 296 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 297 if (temp & XHCI_CRCR_LO_CRR) { 298 DPRINTF("Command ring running\n"); 299 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 300 301 /* 302 * Try to abort the last command as per section 303 * 4.6.1.2 "Aborting a Command" of the XHCI 304 * specification: 305 */ 306 307 /* stop and cancel */ 308 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 309 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 310 311 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 312 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 313 314 /* wait 250ms */ 315 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 316 317 /* check if command ring is still running */ 318 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 319 if (temp & XHCI_CRCR_LO_CRR) { 320 DPRINTF("Comand ring still running\n"); 321 return (USB_ERR_IOERROR); 322 } 323 } 324 325 /* reset command ring */ 326 sc->sc_command_ccs = 1; 327 sc->sc_command_idx = 0; 328 329 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 330 331 /* set up command ring control base address */ 332 addr = buf_res.physaddr; 333 phwr = buf_res.buffer; 334 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 335 336 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 337 338 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 339 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 340 341 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 342 343 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 344 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 345 346 return (0); 347} 348 349usb_error_t 350xhci_start_controller(struct xhci_softc *sc) 351{ 352 struct usb_page_search buf_res; 353 struct xhci_hw_root *phwr; 354 struct xhci_dev_ctx_addr *pdctxa; 355 uint64_t addr; 356 uint32_t temp; 357 uint16_t i; 358 359 DPRINTF("\n"); 360 361 sc->sc_event_ccs = 1; 362 sc->sc_event_idx = 0; 363 sc->sc_command_ccs = 1; 364 sc->sc_command_idx = 0; 365 366 /* Reset controller */ 367 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 368 369 for (i = 0; i != 100; i++) { 370 usb_pause_mtx(NULL, hz / 100); 371 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 372 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 373 if (!temp) 374 break; 375 } 376 377 if (temp) { 378 device_printf(sc->sc_bus.parent, "Controller " 379 "reset timeout.\n"); 380 return (USB_ERR_IOERROR); 381 } 382 383 /* set up number of device slots */ 384 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 385 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 386 387 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 388 389 temp = XREAD4(sc, oper, XHCI_USBSTS); 390 391 /* clear interrupts */ 392 XWRITE4(sc, oper, XHCI_USBSTS, temp); 393 /* disable all device notifications */ 394 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 395 396 /* set up device context base address */ 397 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 398 pdctxa = buf_res.buffer; 399 memset(pdctxa, 0, sizeof(*pdctxa)); 400 401 addr = buf_res.physaddr; 402 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 403 404 /* slot 0 points to the table of scratchpad pointers */ 405 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 406 407 for (i = 0; i != sc->sc_noscratch; i++) { 408 struct usb_page_search buf_scp; 409 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 410 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 411 } 412 413 addr = buf_res.physaddr; 414 415 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 416 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 417 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 418 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 419 420 /* set up event table size */ 421 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 422 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 423 424 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 425 426 /* set up interrupt rate */ 427 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 428 429 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 430 431 phwr = buf_res.buffer; 432 addr = buf_res.physaddr; 433 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 434 435 /* reset hardware root structure */ 436 memset(phwr, 0, sizeof(*phwr)); 437 438 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 439 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 440 441 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 442 443 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 444 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 445 446 addr = buf_res.physaddr; 447 448 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 449 450 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 451 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 452 453 /* set up interrupter registers */ 454 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 455 temp |= XHCI_IMAN_INTR_ENA; 456 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 457 458 /* set up command ring control base address */ 459 addr = buf_res.physaddr; 460 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 461 462 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 463 464 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 465 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 466 467 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 468 469 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 470 471 /* Go! */ 472 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 473 XHCI_CMD_INTE | XHCI_CMD_HSEE); 474 475 for (i = 0; i != 100; i++) { 476 usb_pause_mtx(NULL, hz / 100); 477 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 478 if (!temp) 479 break; 480 } 481 if (temp) { 482 XWRITE4(sc, oper, XHCI_USBCMD, 0); 483 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 484 return (USB_ERR_IOERROR); 485 } 486 487 /* catch any lost interrupts */ 488 xhci_do_poll(&sc->sc_bus); 489 490 if (sc->sc_port_route != NULL) { 491 /* Route all ports to the XHCI by default */ 492 sc->sc_port_route(sc->sc_bus.parent, 493 ~xhciroute, xhciroute); 494 } 495 return (0); 496} 497 498usb_error_t 499xhci_halt_controller(struct xhci_softc *sc) 500{ 501 uint32_t temp; 502 uint16_t i; 503 504 DPRINTF("\n"); 505 506 sc->sc_capa_off = 0; 507 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 508 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 509 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 510 511 /* Halt controller */ 512 XWRITE4(sc, oper, XHCI_USBCMD, 0); 513 514 for (i = 0; i != 100; i++) { 515 usb_pause_mtx(NULL, hz / 100); 516 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 517 if (temp) 518 break; 519 } 520 521 if (!temp) { 522 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 523 return (USB_ERR_IOERROR); 524 } 525 return (0); 526} 527 528usb_error_t 529xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 530{ 531 uint32_t temp; 532 533 DPRINTF("\n"); 534 535 /* initialize some bus fields */ 536 sc->sc_bus.parent = self; 537 538 /* set the bus revision */ 539 sc->sc_bus.usbrev = USB_REV_3_0; 540 541 /* set up the bus struct */ 542 sc->sc_bus.methods = &xhci_bus_methods; 543 544 /* set up devices array */ 545 sc->sc_bus.devices = sc->sc_devices; 546 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 547 548 /* set default cycle state in case of early interrupts */ 549 sc->sc_event_ccs = 1; 550 sc->sc_command_ccs = 1; 551 552 /* set up bus space offsets */ 553 sc->sc_capa_off = 0; 554 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 555 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 556 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 557 558 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 559 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 560 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 561 562 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 563 564 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 565 device_printf(sc->sc_bus.parent, "Controller does " 566 "not support 4K page size.\n"); 567 return (ENXIO); 568 } 569 570 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 571 572 DPRINTF("HCS0 = 0x%08x\n", temp); 573 574 /* set up context size */ 575 if (XHCI_HCS0_CSZ(temp)) { 576 sc->sc_ctx_is_64_byte = 1; 577 } else { 578 sc->sc_ctx_is_64_byte = 0; 579 } 580 581 /* get DMA bits */ 582 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 583 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 584 585 device_printf(self, "%d bytes context size, %d-bit DMA\n", 586 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 587 588 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 589 590 /* get number of device slots */ 591 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 592 593 if (sc->sc_noport == 0) { 594 device_printf(sc->sc_bus.parent, "Invalid number " 595 "of ports: %u\n", sc->sc_noport); 596 return (ENXIO); 597 } 598 599 sc->sc_noport = sc->sc_noport; 600 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 601 602 DPRINTF("Max slots: %u\n", sc->sc_noslot); 603 604 if (sc->sc_noslot > XHCI_MAX_DEVICES) 605 sc->sc_noslot = XHCI_MAX_DEVICES; 606 607 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 608 609 DPRINTF("HCS2=0x%08x\n", temp); 610 611 /* get number of scratchpads */ 612 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 613 614 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 615 device_printf(sc->sc_bus.parent, "XHCI request " 616 "too many scratchpads\n"); 617 return (ENOMEM); 618 } 619 620 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 621 622 /* get event table size */ 623 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 624 if (sc->sc_erst_max > XHCI_MAX_RSEG) 625 sc->sc_erst_max = XHCI_MAX_RSEG; 626 627 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 628 629 /* get maximum exit latency */ 630 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 631 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 632 633 /* Check if we should use the default IMOD value. */ 634 if (sc->sc_imod_default == 0) 635 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 636 637 /* get all DMA memory */ 638 if (usb_bus_mem_alloc_all(&sc->sc_bus, 639 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 640 return (ENOMEM); 641 } 642 643 /* set up command queue mutex and condition varible */ 644 cv_init(&sc->sc_cmd_cv, "CMDQ"); 645 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 646 647 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 648 sc->sc_config_msg[0].bus = &sc->sc_bus; 649 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 650 sc->sc_config_msg[1].bus = &sc->sc_bus; 651 652 return (0); 653} 654 655void 656xhci_uninit(struct xhci_softc *sc) 657{ 658 /* 659 * NOTE: At this point the control transfer process is gone 660 * and "xhci_configure_msg" is no longer called. Consequently 661 * waiting for the configuration messages to complete is not 662 * needed. 663 */ 664 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 665 666 cv_destroy(&sc->sc_cmd_cv); 667 sx_destroy(&sc->sc_cmd_sx); 668} 669 670static void 671xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 672{ 673 struct xhci_softc *sc = XHCI_BUS2SC(bus); 674 675 switch (state) { 676 case USB_HW_POWER_SUSPEND: 677 DPRINTF("Stopping the XHCI\n"); 678 xhci_halt_controller(sc); 679 break; 680 case USB_HW_POWER_SHUTDOWN: 681 DPRINTF("Stopping the XHCI\n"); 682 xhci_halt_controller(sc); 683 break; 684 case USB_HW_POWER_RESUME: 685 DPRINTF("Starting the XHCI\n"); 686 xhci_start_controller(sc); 687 break; 688 default: 689 break; 690 } 691} 692 693static usb_error_t 694xhci_generic_done_sub(struct usb_xfer *xfer) 695{ 696 struct xhci_td *td; 697 struct xhci_td *td_alt_next; 698 uint32_t len; 699 uint8_t status; 700 701 td = xfer->td_transfer_cache; 702 td_alt_next = td->alt_next; 703 704 if (xfer->aframes != xfer->nframes) 705 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 706 707 while (1) { 708 709 usb_pc_cpu_invalidate(td->page_cache); 710 711 status = td->status; 712 len = td->remainder; 713 714 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 715 xfer, (unsigned int)xfer->aframes, 716 (unsigned int)xfer->nframes, 717 (unsigned int)len, (unsigned int)td->len, 718 (unsigned int)status); 719 720 /* 721 * Verify the status length and 722 * add the length to "frlengths[]": 723 */ 724 if (len > td->len) { 725 /* should not happen */ 726 DPRINTF("Invalid status length, " 727 "0x%04x/0x%04x bytes\n", len, td->len); 728 status = XHCI_TRB_ERROR_LENGTH; 729 } else if (xfer->aframes != xfer->nframes) { 730 xfer->frlengths[xfer->aframes] += td->len - len; 731 } 732 /* Check for last transfer */ 733 if (((void *)td) == xfer->td_transfer_last) { 734 td = NULL; 735 break; 736 } 737 /* Check for transfer error */ 738 if (status != XHCI_TRB_ERROR_SHORT_PKT && 739 status != XHCI_TRB_ERROR_SUCCESS) { 740 /* the transfer is finished */ 741 td = NULL; 742 break; 743 } 744 /* Check for short transfer */ 745 if (len > 0) { 746 if (xfer->flags_int.short_frames_ok || 747 xfer->flags_int.isochronous_xfr || 748 xfer->flags_int.control_xfr) { 749 /* follow alt next */ 750 td = td->alt_next; 751 } else { 752 /* the transfer is finished */ 753 td = NULL; 754 } 755 break; 756 } 757 td = td->obj_next; 758 759 if (td->alt_next != td_alt_next) { 760 /* this USB frame is complete */ 761 break; 762 } 763 } 764 765 /* update transfer cache */ 766 767 xfer->td_transfer_cache = td; 768 769 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 770 (status != XHCI_TRB_ERROR_SHORT_PKT && 771 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 772 USB_ERR_NORMAL_COMPLETION); 773} 774 775static void 776xhci_generic_done(struct usb_xfer *xfer) 777{ 778 usb_error_t err = 0; 779 780 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 781 xfer, xfer->endpoint); 782 783 /* reset scanner */ 784 785 xfer->td_transfer_cache = xfer->td_transfer_first; 786 787 if (xfer->flags_int.control_xfr) { 788 789 if (xfer->flags_int.control_hdr) 790 err = xhci_generic_done_sub(xfer); 791 792 xfer->aframes = 1; 793 794 if (xfer->td_transfer_cache == NULL) 795 goto done; 796 } 797 798 while (xfer->aframes != xfer->nframes) { 799 800 err = xhci_generic_done_sub(xfer); 801 xfer->aframes++; 802 803 if (xfer->td_transfer_cache == NULL) 804 goto done; 805 } 806 807 if (xfer->flags_int.control_xfr && 808 !xfer->flags_int.control_act) 809 err = xhci_generic_done_sub(xfer); 810done: 811 /* transfer is complete */ 812 xhci_device_done(xfer, err); 813} 814 815static void 816xhci_activate_transfer(struct usb_xfer *xfer) 817{ 818 struct xhci_td *td; 819 820 td = xfer->td_transfer_cache; 821 822 usb_pc_cpu_invalidate(td->page_cache); 823 824 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 825 826 /* activate the transfer */ 827 828 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 829 usb_pc_cpu_flush(td->page_cache); 830 831 xhci_endpoint_doorbell(xfer); 832 } 833} 834 835static void 836xhci_skip_transfer(struct usb_xfer *xfer) 837{ 838 struct xhci_td *td; 839 struct xhci_td *td_last; 840 841 td = xfer->td_transfer_cache; 842 td_last = xfer->td_transfer_last; 843 844 td = td->alt_next; 845 846 usb_pc_cpu_invalidate(td->page_cache); 847 848 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 849 850 usb_pc_cpu_invalidate(td_last->page_cache); 851 852 /* copy LINK TRB to current waiting location */ 853 854 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 855 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 856 usb_pc_cpu_flush(td->page_cache); 857 858 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 859 usb_pc_cpu_flush(td->page_cache); 860 861 xhci_endpoint_doorbell(xfer); 862 } 863} 864 865/*------------------------------------------------------------------------* 866 * xhci_check_transfer 867 *------------------------------------------------------------------------*/ 868static void 869xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 870{ 871 struct xhci_endpoint_ext *pepext; 872 int64_t offset; 873 uint64_t td_event; 874 uint32_t temp; 875 uint32_t remainder; 876 uint16_t stream_id; 877 uint16_t i; 878 uint8_t status; 879 uint8_t halted; 880 uint8_t epno; 881 uint8_t index; 882 883 /* decode TRB */ 884 td_event = le64toh(trb->qwTrb0); 885 temp = le32toh(trb->dwTrb2); 886 887 remainder = XHCI_TRB_2_REM_GET(temp); 888 status = XHCI_TRB_2_ERROR_GET(temp); 889 stream_id = XHCI_TRB_2_STREAM_GET(temp); 890 891 temp = le32toh(trb->dwTrb3); 892 epno = XHCI_TRB_3_EP_GET(temp); 893 index = XHCI_TRB_3_SLOT_GET(temp); 894 895 /* check if error means halted */ 896 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 897 status != XHCI_TRB_ERROR_SUCCESS); 898 899 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 900 index, epno, stream_id, remainder, status); 901 902 if (index > sc->sc_noslot) { 903 DPRINTF("Invalid slot.\n"); 904 return; 905 } 906 907 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 908 DPRINTF("Invalid endpoint.\n"); 909 return; 910 } 911 912 pepext = &sc->sc_hw.devs[index].endp[epno]; 913 914 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 915 stream_id = 0; 916 DPRINTF("stream_id=0\n"); 917 } else if (stream_id >= XHCI_MAX_STREAMS) { 918 DPRINTF("Invalid stream ID.\n"); 919 return; 920 } 921 922 /* try to find the USB transfer that generated the event */ 923 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 924 struct usb_xfer *xfer; 925 struct xhci_td *td; 926 927 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 928 if (xfer == NULL) 929 continue; 930 931 td = xfer->td_transfer_cache; 932 933 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 934 (long long)td_event, 935 (long long)td->td_self, 936 (long long)td->td_self + sizeof(td->td_trb)); 937 938 /* 939 * NOTE: Some XHCI implementations might not trigger 940 * an event on the last LINK TRB so we need to 941 * consider both the last and second last event 942 * address as conditions for a successful transfer. 943 * 944 * NOTE: We assume that the XHCI will only trigger one 945 * event per chain of TRBs. 946 */ 947 948 offset = td_event - td->td_self; 949 950 if (offset >= 0 && 951 offset < (int64_t)sizeof(td->td_trb)) { 952 953 usb_pc_cpu_invalidate(td->page_cache); 954 955 /* compute rest of remainder, if any */ 956 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 957 temp = le32toh(td->td_trb[i].dwTrb2); 958 remainder += XHCI_TRB_2_BYTES_GET(temp); 959 } 960 961 DPRINTFN(5, "New remainder: %u\n", remainder); 962 963 /* clear isochronous transfer errors */ 964 if (xfer->flags_int.isochronous_xfr) { 965 if (halted) { 966 halted = 0; 967 status = XHCI_TRB_ERROR_SUCCESS; 968 remainder = td->len; 969 } 970 } 971 972 /* "td->remainder" is verified later */ 973 td->remainder = remainder; 974 td->status = status; 975 976 usb_pc_cpu_flush(td->page_cache); 977 978 /* 979 * 1) Last transfer descriptor makes the 980 * transfer done 981 */ 982 if (((void *)td) == xfer->td_transfer_last) { 983 DPRINTF("TD is last\n"); 984 xhci_generic_done(xfer); 985 break; 986 } 987 988 /* 989 * 2) Any kind of error makes the transfer 990 * done 991 */ 992 if (halted) { 993 DPRINTF("TD has I/O error\n"); 994 xhci_generic_done(xfer); 995 break; 996 } 997 998 /* 999 * 3) If there is no alternate next transfer, 1000 * a short packet also makes the transfer done 1001 */ 1002 if (td->remainder > 0) { 1003 if (td->alt_next == NULL) { 1004 DPRINTF( 1005 "short TD has no alternate next\n"); 1006 xhci_generic_done(xfer); 1007 break; 1008 } 1009 DPRINTF("TD has short pkt\n"); 1010 if (xfer->flags_int.short_frames_ok || 1011 xfer->flags_int.isochronous_xfr || 1012 xfer->flags_int.control_xfr) { 1013 /* follow the alt next */ 1014 xfer->td_transfer_cache = td->alt_next; 1015 xhci_activate_transfer(xfer); 1016 break; 1017 } 1018 xhci_skip_transfer(xfer); 1019 xhci_generic_done(xfer); 1020 break; 1021 } 1022 1023 /* 1024 * 4) Transfer complete - go to next TD 1025 */ 1026 DPRINTF("Following next TD\n"); 1027 xfer->td_transfer_cache = td->obj_next; 1028 xhci_activate_transfer(xfer); 1029 break; /* there should only be one match */ 1030 } 1031 } 1032} 1033 1034static int 1035xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1036{ 1037 if (sc->sc_cmd_addr == trb->qwTrb0) { 1038 DPRINTF("Received command event\n"); 1039 sc->sc_cmd_result[0] = trb->dwTrb2; 1040 sc->sc_cmd_result[1] = trb->dwTrb3; 1041 cv_signal(&sc->sc_cmd_cv); 1042 return (1); /* command match */ 1043 } 1044 return (0); 1045} 1046 1047static int 1048xhci_interrupt_poll(struct xhci_softc *sc) 1049{ 1050 struct usb_page_search buf_res; 1051 struct xhci_hw_root *phwr; 1052 uint64_t addr; 1053 uint32_t temp; 1054 int retval = 0; 1055 uint16_t i; 1056 uint8_t event; 1057 uint8_t j; 1058 uint8_t k; 1059 uint8_t t; 1060 1061 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1062 1063 phwr = buf_res.buffer; 1064 1065 /* Receive any events */ 1066 1067 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1068 1069 i = sc->sc_event_idx; 1070 j = sc->sc_event_ccs; 1071 t = 2; 1072 1073 while (1) { 1074 1075 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1076 1077 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1078 1079 if (j != k) 1080 break; 1081 1082 event = XHCI_TRB_3_TYPE_GET(temp); 1083 1084 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1085 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1086 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1087 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1088 1089 switch (event) { 1090 case XHCI_TRB_EVENT_TRANSFER: 1091 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1092 break; 1093 case XHCI_TRB_EVENT_CMD_COMPLETE: 1094 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1095 break; 1096 default: 1097 DPRINTF("Unhandled event = %u\n", event); 1098 break; 1099 } 1100 1101 i++; 1102 1103 if (i == XHCI_MAX_EVENTS) { 1104 i = 0; 1105 j ^= 1; 1106 1107 /* check for timeout */ 1108 if (!--t) 1109 break; 1110 } 1111 } 1112 1113 sc->sc_event_idx = i; 1114 sc->sc_event_ccs = j; 1115 1116 /* 1117 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1118 * latched. That means to activate the register we need to 1119 * write both the low and high double word of the 64-bit 1120 * register. 1121 */ 1122 1123 addr = buf_res.physaddr; 1124 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1125 1126 /* try to clear busy bit */ 1127 addr |= XHCI_ERDP_LO_BUSY; 1128 1129 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1130 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1131 1132 return (retval); 1133} 1134 1135static usb_error_t 1136xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1137 uint16_t timeout_ms) 1138{ 1139 struct usb_page_search buf_res; 1140 struct xhci_hw_root *phwr; 1141 uint64_t addr; 1142 uint32_t temp; 1143 uint8_t i; 1144 uint8_t j; 1145 uint8_t timeout = 0; 1146 int err; 1147 1148 XHCI_CMD_ASSERT_LOCKED(sc); 1149 1150 /* get hardware root structure */ 1151 1152 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1153 1154 phwr = buf_res.buffer; 1155 1156 /* Queue command */ 1157 1158 USB_BUS_LOCK(&sc->sc_bus); 1159retry: 1160 i = sc->sc_command_idx; 1161 j = sc->sc_command_ccs; 1162 1163 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1164 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1165 (long long)le64toh(trb->qwTrb0), 1166 (long)le32toh(trb->dwTrb2), 1167 (long)le32toh(trb->dwTrb3)); 1168 1169 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1170 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1171 1172 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1173 1174 temp = trb->dwTrb3; 1175 1176 if (j) 1177 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1178 else 1179 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1180 1181 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1182 1183 phwr->hwr_commands[i].dwTrb3 = temp; 1184 1185 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1186 1187 addr = buf_res.physaddr; 1188 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1189 1190 sc->sc_cmd_addr = htole64(addr); 1191 1192 i++; 1193 1194 if (i == (XHCI_MAX_COMMANDS - 1)) { 1195 1196 if (j) { 1197 temp = htole32(XHCI_TRB_3_TC_BIT | 1198 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1199 XHCI_TRB_3_CYCLE_BIT); 1200 } else { 1201 temp = htole32(XHCI_TRB_3_TC_BIT | 1202 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1203 } 1204 1205 phwr->hwr_commands[i].dwTrb3 = temp; 1206 1207 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1208 1209 i = 0; 1210 j ^= 1; 1211 } 1212 1213 sc->sc_command_idx = i; 1214 sc->sc_command_ccs = j; 1215 1216 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1217 1218 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1219 USB_MS_TO_TICKS(timeout_ms)); 1220 1221 /* 1222 * In some error cases event interrupts are not generated. 1223 * Poll one time to see if the command has completed. 1224 */ 1225 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1226 DPRINTF("Command was completed when polling\n"); 1227 err = 0; 1228 } 1229 if (err != 0) { 1230 DPRINTF("Command timeout!\n"); 1231 /* 1232 * After some weeks of continuous operation, it has 1233 * been observed that the ASMedia Technology, ASM1042 1234 * SuperSpeed USB Host Controller can suddenly stop 1235 * accepting commands via the command queue. Try to 1236 * first reset the command queue. If that fails do a 1237 * host controller reset. 1238 */ 1239 if (timeout == 0 && 1240 xhci_reset_command_queue_locked(sc) == 0) { 1241 temp = le32toh(trb->dwTrb3); 1242 1243 /* 1244 * Avoid infinite XHCI reset loops if the set 1245 * address command fails to respond due to a 1246 * non-enumerating device: 1247 */ 1248 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1249 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1250 DPRINTF("Set address timeout\n"); 1251 } else { 1252 timeout = 1; 1253 goto retry; 1254 } 1255 } else { 1256 DPRINTF("Controller reset!\n"); 1257 usb_bus_reset_async_locked(&sc->sc_bus); 1258 } 1259 err = USB_ERR_TIMEOUT; 1260 trb->dwTrb2 = 0; 1261 trb->dwTrb3 = 0; 1262 } else { 1263 temp = le32toh(sc->sc_cmd_result[0]); 1264 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1265 err = USB_ERR_IOERROR; 1266 1267 trb->dwTrb2 = sc->sc_cmd_result[0]; 1268 trb->dwTrb3 = sc->sc_cmd_result[1]; 1269 } 1270 1271 USB_BUS_UNLOCK(&sc->sc_bus); 1272 1273 return (err); 1274} 1275 1276#if 0 1277static usb_error_t 1278xhci_cmd_nop(struct xhci_softc *sc) 1279{ 1280 struct xhci_trb trb; 1281 uint32_t temp; 1282 1283 DPRINTF("\n"); 1284 1285 trb.qwTrb0 = 0; 1286 trb.dwTrb2 = 0; 1287 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1288 1289 trb.dwTrb3 = htole32(temp); 1290 1291 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1292} 1293#endif 1294 1295static usb_error_t 1296xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1297{ 1298 struct xhci_trb trb; 1299 uint32_t temp; 1300 usb_error_t err; 1301 1302 DPRINTF("\n"); 1303 1304 trb.qwTrb0 = 0; 1305 trb.dwTrb2 = 0; 1306 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1307 1308 err = xhci_do_command(sc, &trb, 100 /* ms */); 1309 if (err) 1310 goto done; 1311 1312 temp = le32toh(trb.dwTrb3); 1313 1314 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1315 1316done: 1317 return (err); 1318} 1319 1320static usb_error_t 1321xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1322{ 1323 struct xhci_trb trb; 1324 uint32_t temp; 1325 1326 DPRINTF("\n"); 1327 1328 trb.qwTrb0 = 0; 1329 trb.dwTrb2 = 0; 1330 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1331 XHCI_TRB_3_SLOT_SET(slot_id); 1332 1333 trb.dwTrb3 = htole32(temp); 1334 1335 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1336} 1337 1338static usb_error_t 1339xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1340 uint8_t bsr, uint8_t slot_id) 1341{ 1342 struct xhci_trb trb; 1343 uint32_t temp; 1344 1345 DPRINTF("\n"); 1346 1347 trb.qwTrb0 = htole64(input_ctx); 1348 trb.dwTrb2 = 0; 1349 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1350 XHCI_TRB_3_SLOT_SET(slot_id); 1351 1352 if (bsr) 1353 temp |= XHCI_TRB_3_BSR_BIT; 1354 1355 trb.dwTrb3 = htole32(temp); 1356 1357 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1358} 1359 1360static usb_error_t 1361xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1362{ 1363 struct usb_page_search buf_inp; 1364 struct usb_page_search buf_dev; 1365 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1366 struct xhci_hw_dev *hdev; 1367 struct xhci_dev_ctx *pdev; 1368 struct xhci_endpoint_ext *pepext; 1369 uint32_t temp; 1370 uint16_t mps; 1371 usb_error_t err; 1372 uint8_t index; 1373 1374 /* the root HUB case is not handled here */ 1375 if (udev->parent_hub == NULL) 1376 return (USB_ERR_INVAL); 1377 1378 index = udev->controller_slot_id; 1379 1380 hdev = &sc->sc_hw.devs[index]; 1381 1382 if (mtx != NULL) 1383 mtx_unlock(mtx); 1384 1385 XHCI_CMD_LOCK(sc); 1386 1387 switch (hdev->state) { 1388 case XHCI_ST_DEFAULT: 1389 case XHCI_ST_ENABLED: 1390 1391 hdev->state = XHCI_ST_ENABLED; 1392 1393 /* set configure mask to slot and EP0 */ 1394 xhci_configure_mask(udev, 3, 0); 1395 1396 /* configure input slot context structure */ 1397 err = xhci_configure_device(udev); 1398 1399 if (err != 0) { 1400 DPRINTF("Could not configure device\n"); 1401 break; 1402 } 1403 1404 /* configure input endpoint context structure */ 1405 switch (udev->speed) { 1406 case USB_SPEED_LOW: 1407 case USB_SPEED_FULL: 1408 mps = 8; 1409 break; 1410 case USB_SPEED_HIGH: 1411 mps = 64; 1412 break; 1413 default: 1414 mps = 512; 1415 break; 1416 } 1417 1418 pepext = xhci_get_endpoint_ext(udev, 1419 &udev->ctrl_ep_desc); 1420 1421 /* ensure the control endpoint is setup again */ 1422 USB_BUS_LOCK(udev->bus); 1423 pepext->trb_halted = 1; 1424 pepext->trb_running = 0; 1425 USB_BUS_UNLOCK(udev->bus); 1426 1427 err = xhci_configure_endpoint(udev, 1428 &udev->ctrl_ep_desc, pepext, 1429 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1430 1431 if (err != 0) { 1432 DPRINTF("Could not configure default endpoint\n"); 1433 break; 1434 } 1435 1436 /* execute set address command */ 1437 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1438 1439 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1440 (address == 0), index); 1441 1442 if (err != 0) { 1443 temp = le32toh(sc->sc_cmd_result[0]); 1444 if (address == 0 && sc->sc_port_route != NULL && 1445 XHCI_TRB_2_ERROR_GET(temp) == 1446 XHCI_TRB_ERROR_PARAMETER) { 1447 /* LynxPoint XHCI - ports are not switchable */ 1448 /* Un-route all ports from the XHCI */ 1449 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1450 } 1451 DPRINTF("Could not set address " 1452 "for slot %u.\n", index); 1453 if (address != 0) 1454 break; 1455 } 1456 1457 /* update device address to new value */ 1458 1459 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1460 pdev = buf_dev.buffer; 1461 usb_pc_cpu_invalidate(&hdev->device_pc); 1462 1463 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1464 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1465 1466 /* update device state to new value */ 1467 1468 if (address != 0) 1469 hdev->state = XHCI_ST_ADDRESSED; 1470 else 1471 hdev->state = XHCI_ST_DEFAULT; 1472 break; 1473 1474 default: 1475 DPRINTF("Wrong state for set address.\n"); 1476 err = USB_ERR_IOERROR; 1477 break; 1478 } 1479 XHCI_CMD_UNLOCK(sc); 1480 1481 if (mtx != NULL) 1482 mtx_lock(mtx); 1483 1484 return (err); 1485} 1486 1487static usb_error_t 1488xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1489 uint8_t deconfigure, uint8_t slot_id) 1490{ 1491 struct xhci_trb trb; 1492 uint32_t temp; 1493 1494 DPRINTF("\n"); 1495 1496 trb.qwTrb0 = htole64(input_ctx); 1497 trb.dwTrb2 = 0; 1498 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1499 XHCI_TRB_3_SLOT_SET(slot_id); 1500 1501 if (deconfigure) 1502 temp |= XHCI_TRB_3_DCEP_BIT; 1503 1504 trb.dwTrb3 = htole32(temp); 1505 1506 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1507} 1508 1509static usb_error_t 1510xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1511 uint8_t slot_id) 1512{ 1513 struct xhci_trb trb; 1514 uint32_t temp; 1515 1516 DPRINTF("\n"); 1517 1518 trb.qwTrb0 = htole64(input_ctx); 1519 trb.dwTrb2 = 0; 1520 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1521 XHCI_TRB_3_SLOT_SET(slot_id); 1522 trb.dwTrb3 = htole32(temp); 1523 1524 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1525} 1526 1527static usb_error_t 1528xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1529 uint8_t ep_id, uint8_t slot_id) 1530{ 1531 struct xhci_trb trb; 1532 uint32_t temp; 1533 1534 DPRINTF("\n"); 1535 1536 trb.qwTrb0 = 0; 1537 trb.dwTrb2 = 0; 1538 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1539 XHCI_TRB_3_SLOT_SET(slot_id) | 1540 XHCI_TRB_3_EP_SET(ep_id); 1541 1542 if (preserve) 1543 temp |= XHCI_TRB_3_PRSV_BIT; 1544 1545 trb.dwTrb3 = htole32(temp); 1546 1547 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1548} 1549 1550static usb_error_t 1551xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1552 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1553{ 1554 struct xhci_trb trb; 1555 uint32_t temp; 1556 1557 DPRINTF("\n"); 1558 1559 trb.qwTrb0 = htole64(dequeue_ptr); 1560 1561 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1562 trb.dwTrb2 = htole32(temp); 1563 1564 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1565 XHCI_TRB_3_SLOT_SET(slot_id) | 1566 XHCI_TRB_3_EP_SET(ep_id); 1567 trb.dwTrb3 = htole32(temp); 1568 1569 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1570} 1571 1572static usb_error_t 1573xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1574 uint8_t ep_id, uint8_t slot_id) 1575{ 1576 struct xhci_trb trb; 1577 uint32_t temp; 1578 1579 DPRINTF("\n"); 1580 1581 trb.qwTrb0 = 0; 1582 trb.dwTrb2 = 0; 1583 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1584 XHCI_TRB_3_SLOT_SET(slot_id) | 1585 XHCI_TRB_3_EP_SET(ep_id); 1586 1587 if (suspend) 1588 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1589 1590 trb.dwTrb3 = htole32(temp); 1591 1592 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1593} 1594 1595static usb_error_t 1596xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1597{ 1598 struct xhci_trb trb; 1599 uint32_t temp; 1600 1601 DPRINTF("\n"); 1602 1603 trb.qwTrb0 = 0; 1604 trb.dwTrb2 = 0; 1605 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1606 XHCI_TRB_3_SLOT_SET(slot_id); 1607 1608 trb.dwTrb3 = htole32(temp); 1609 1610 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1611} 1612 1613/*------------------------------------------------------------------------* 1614 * xhci_interrupt - XHCI interrupt handler 1615 *------------------------------------------------------------------------*/ 1616void 1617xhci_interrupt(struct xhci_softc *sc) 1618{ 1619 uint32_t status; 1620 uint32_t temp; 1621 1622 USB_BUS_LOCK(&sc->sc_bus); 1623 1624 status = XREAD4(sc, oper, XHCI_USBSTS); 1625 1626 /* acknowledge interrupts, if any */ 1627 if (status != 0) { 1628 XWRITE4(sc, oper, XHCI_USBSTS, status); 1629 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1630 } 1631 1632 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1633 1634 /* force clearing of pending interrupts */ 1635 if (temp & XHCI_IMAN_INTR_PEND) 1636 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1637 1638 /* check for event(s) */ 1639 xhci_interrupt_poll(sc); 1640 1641 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1642 XHCI_STS_HSE | XHCI_STS_HCE)) { 1643 1644 if (status & XHCI_STS_PCD) { 1645 xhci_root_intr(sc); 1646 } 1647 1648 if (status & XHCI_STS_HCH) { 1649 printf("%s: host controller halted\n", 1650 __FUNCTION__); 1651 } 1652 1653 if (status & XHCI_STS_HSE) { 1654 printf("%s: host system error\n", 1655 __FUNCTION__); 1656 } 1657 1658 if (status & XHCI_STS_HCE) { 1659 printf("%s: host controller error\n", 1660 __FUNCTION__); 1661 } 1662 } 1663 USB_BUS_UNLOCK(&sc->sc_bus); 1664} 1665 1666/*------------------------------------------------------------------------* 1667 * xhci_timeout - XHCI timeout handler 1668 *------------------------------------------------------------------------*/ 1669static void 1670xhci_timeout(void *arg) 1671{ 1672 struct usb_xfer *xfer = arg; 1673 1674 DPRINTF("xfer=%p\n", xfer); 1675 1676 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1677 1678 /* transfer is transferred */ 1679 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1680} 1681 1682static void 1683xhci_do_poll(struct usb_bus *bus) 1684{ 1685 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1686 1687 USB_BUS_LOCK(&sc->sc_bus); 1688 xhci_interrupt_poll(sc); 1689 USB_BUS_UNLOCK(&sc->sc_bus); 1690} 1691 1692static void 1693xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1694{ 1695 struct usb_page_search buf_res; 1696 struct xhci_td *td; 1697 struct xhci_td *td_next; 1698 struct xhci_td *td_alt_next; 1699 struct xhci_td *td_first; 1700 uint32_t buf_offset; 1701 uint32_t average; 1702 uint32_t len_old; 1703 uint32_t npkt_off; 1704 uint32_t dword; 1705 uint8_t shortpkt_old; 1706 uint8_t precompute; 1707 uint8_t x; 1708 1709 td_alt_next = NULL; 1710 buf_offset = 0; 1711 shortpkt_old = temp->shortpkt; 1712 len_old = temp->len; 1713 npkt_off = 0; 1714 precompute = 1; 1715 1716restart: 1717 1718 td = temp->td; 1719 td_next = td_first = temp->td_next; 1720 1721 while (1) { 1722 1723 if (temp->len == 0) { 1724 1725 if (temp->shortpkt) 1726 break; 1727 1728 /* send a Zero Length Packet, ZLP, last */ 1729 1730 temp->shortpkt = 1; 1731 average = 0; 1732 1733 } else { 1734 1735 average = temp->average; 1736 1737 if (temp->len < average) { 1738 if (temp->len % temp->max_packet_size) { 1739 temp->shortpkt = 1; 1740 } 1741 average = temp->len; 1742 } 1743 } 1744 1745 if (td_next == NULL) 1746 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1747 1748 /* get next TD */ 1749 1750 td = td_next; 1751 td_next = td->obj_next; 1752 1753 /* check if we are pre-computing */ 1754 1755 if (precompute) { 1756 1757 /* update remaining length */ 1758 1759 temp->len -= average; 1760 1761 continue; 1762 } 1763 /* fill out current TD */ 1764 1765 td->len = average; 1766 td->remainder = 0; 1767 td->status = 0; 1768 1769 /* update remaining length */ 1770 1771 temp->len -= average; 1772 1773 /* reset TRB index */ 1774 1775 x = 0; 1776 1777 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1778 /* immediate data */ 1779 1780 if (average > 8) 1781 average = 8; 1782 1783 td->td_trb[0].qwTrb0 = 0; 1784 1785 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1786 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1787 average); 1788 1789 dword = XHCI_TRB_2_BYTES_SET(8) | 1790 XHCI_TRB_2_TDSZ_SET(0) | 1791 XHCI_TRB_2_IRQ_SET(0); 1792 1793 td->td_trb[0].dwTrb2 = htole32(dword); 1794 1795 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1796 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1797 1798 /* check wLength */ 1799 if (td->td_trb[0].qwTrb0 & 1800 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1801 if (td->td_trb[0].qwTrb0 & 1802 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1803 dword |= XHCI_TRB_3_TRT_IN; 1804 else 1805 dword |= XHCI_TRB_3_TRT_OUT; 1806 } 1807 1808 td->td_trb[0].dwTrb3 = htole32(dword); 1809#ifdef USB_DEBUG 1810 xhci_dump_trb(&td->td_trb[x]); 1811#endif 1812 x++; 1813 1814 } else do { 1815 1816 uint32_t npkt; 1817 1818 /* fill out buffer pointers */ 1819 1820 if (average == 0) { 1821 memset(&buf_res, 0, sizeof(buf_res)); 1822 } else { 1823 usbd_get_page(temp->pc, temp->offset + 1824 buf_offset, &buf_res); 1825 1826 /* get length to end of page */ 1827 if (buf_res.length > average) 1828 buf_res.length = average; 1829 1830 /* check for maximum length */ 1831 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1832 buf_res.length = XHCI_TD_PAGE_SIZE; 1833 1834 npkt_off += buf_res.length; 1835 } 1836 1837 /* set up npkt */ 1838 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1839 temp->max_packet_size; 1840 1841 if (npkt == 0) 1842 npkt = 1; 1843 else if (npkt > 31) 1844 npkt = 31; 1845 1846 /* fill out TRB's */ 1847 td->td_trb[x].qwTrb0 = 1848 htole64((uint64_t)buf_res.physaddr); 1849 1850 dword = 1851 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1852 XHCI_TRB_2_TDSZ_SET(npkt) | 1853 XHCI_TRB_2_IRQ_SET(0); 1854 1855 td->td_trb[x].dwTrb2 = htole32(dword); 1856 1857 switch (temp->trb_type) { 1858 case XHCI_TRB_TYPE_ISOCH: 1859 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1860 XHCI_TRB_3_TBC_SET(temp->tbc) | 1861 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1862 if (td != td_first) { 1863 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1864 } else if (temp->do_isoc_sync != 0) { 1865 temp->do_isoc_sync = 0; 1866 /* wait until "isoc_frame" */ 1867 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1868 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1869 } else { 1870 /* start data transfer at next interval */ 1871 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1872 XHCI_TRB_3_ISO_SIA_BIT; 1873 } 1874 if (temp->direction == UE_DIR_IN) 1875 dword |= XHCI_TRB_3_ISP_BIT; 1876 break; 1877 case XHCI_TRB_TYPE_DATA_STAGE: 1878 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1879 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1880 if (temp->direction == UE_DIR_IN) 1881 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1882 /* 1883 * Section 3.2.9 in the XHCI 1884 * specification about control 1885 * transfers says that we should use a 1886 * normal-TRB if there are more TRBs 1887 * extending the data-stage 1888 * TRB. Update the "trb_type". 1889 */ 1890 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1891 break; 1892 case XHCI_TRB_TYPE_STATUS_STAGE: 1893 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1894 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1895 if (temp->direction == UE_DIR_IN) 1896 dword |= XHCI_TRB_3_DIR_IN; 1897 break; 1898 default: /* XHCI_TRB_TYPE_NORMAL */ 1899 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1900 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1901 if (temp->direction == UE_DIR_IN) 1902 dword |= XHCI_TRB_3_ISP_BIT; 1903 break; 1904 } 1905 td->td_trb[x].dwTrb3 = htole32(dword); 1906 1907 average -= buf_res.length; 1908 buf_offset += buf_res.length; 1909#ifdef USB_DEBUG 1910 xhci_dump_trb(&td->td_trb[x]); 1911#endif 1912 x++; 1913 1914 } while (average != 0); 1915 1916 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1917 1918 /* store number of data TRB's */ 1919 1920 td->ntrb = x; 1921 1922 DPRINTF("NTRB=%u\n", x); 1923 1924 /* fill out link TRB */ 1925 1926 if (td_next != NULL) { 1927 /* link the current TD with the next one */ 1928 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1929 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1930 } else { 1931 /* this field will get updated later */ 1932 DPRINTF("NOLINK\n"); 1933 } 1934 1935 dword = XHCI_TRB_2_IRQ_SET(0); 1936 1937 td->td_trb[x].dwTrb2 = htole32(dword); 1938 1939 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1940 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1941 /* 1942 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1943 * frame only receives a single short packet event 1944 * by setting the CHAIN bit in the LINK field. In 1945 * addition some XHCI controllers have problems 1946 * sending a ZLP unless the CHAIN-BIT is set in 1947 * the LINK TRB. 1948 */ 1949 XHCI_TRB_3_CHAIN_BIT; 1950 1951 td->td_trb[x].dwTrb3 = htole32(dword); 1952 1953 td->alt_next = td_alt_next; 1954#ifdef USB_DEBUG 1955 xhci_dump_trb(&td->td_trb[x]); 1956#endif 1957 usb_pc_cpu_flush(td->page_cache); 1958 } 1959 1960 if (precompute) { 1961 precompute = 0; 1962 1963 /* set up alt next pointer, if any */ 1964 if (temp->last_frame) { 1965 td_alt_next = NULL; 1966 } else { 1967 /* we use this field internally */ 1968 td_alt_next = td_next; 1969 } 1970 1971 /* restore */ 1972 temp->shortpkt = shortpkt_old; 1973 temp->len = len_old; 1974 goto restart; 1975 } 1976 1977 /* 1978 * Remove cycle bit from the first TRB if we are 1979 * stepping them: 1980 */ 1981 if (temp->step_td != 0) { 1982 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1983 usb_pc_cpu_flush(td_first->page_cache); 1984 } 1985 1986 /* clear TD SIZE to zero, hence this is the last TRB */ 1987 /* remove chain bit because this is the last data TRB in the chain */ 1988 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1989 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1990 /* remove CHAIN-BIT from last LINK TRB */ 1991 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1992 1993 usb_pc_cpu_flush(td->page_cache); 1994 1995 temp->td = td; 1996 temp->td_next = td_next; 1997} 1998 1999static void 2000xhci_setup_generic_chain(struct usb_xfer *xfer) 2001{ 2002 struct xhci_std_temp temp; 2003 struct xhci_td *td; 2004 uint32_t x; 2005 uint32_t y; 2006 uint8_t mult; 2007 2008 temp.do_isoc_sync = 0; 2009 temp.step_td = 0; 2010 temp.tbc = 0; 2011 temp.tlbpc = 0; 2012 temp.average = xfer->max_hc_frame_size; 2013 temp.max_packet_size = xfer->max_packet_size; 2014 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 2015 temp.pc = NULL; 2016 temp.last_frame = 0; 2017 temp.offset = 0; 2018 temp.multishort = xfer->flags_int.isochronous_xfr || 2019 xfer->flags_int.control_xfr || 2020 xfer->flags_int.short_frames_ok; 2021 2022 /* toggle the DMA set we are using */ 2023 xfer->flags_int.curr_dma_set ^= 1; 2024 2025 /* get next DMA set */ 2026 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2027 2028 temp.td = NULL; 2029 temp.td_next = td; 2030 2031 xfer->td_transfer_first = td; 2032 xfer->td_transfer_cache = td; 2033 2034 if (xfer->flags_int.isochronous_xfr) { 2035 uint8_t shift; 2036 2037 /* compute multiplier for ISOCHRONOUS transfers */ 2038 mult = xfer->endpoint->ecomp ? 2039 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2040 : 0; 2041 /* check for USB 2.0 multiplier */ 2042 if (mult == 0) { 2043 mult = (xfer->endpoint->edesc-> 2044 wMaxPacketSize[1] >> 3) & 3; 2045 } 2046 /* range check */ 2047 if (mult > 2) 2048 mult = 3; 2049 else 2050 mult++; 2051 2052 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2053 2054 DPRINTF("MFINDEX=0x%08x\n", x); 2055 2056 switch (usbd_get_speed(xfer->xroot->udev)) { 2057 case USB_SPEED_FULL: 2058 shift = 3; 2059 temp.isoc_delta = 8; /* 1ms */ 2060 x += temp.isoc_delta - 1; 2061 x &= ~(temp.isoc_delta - 1); 2062 break; 2063 default: 2064 shift = usbd_xfer_get_fps_shift(xfer); 2065 temp.isoc_delta = 1U << shift; 2066 x += temp.isoc_delta - 1; 2067 x &= ~(temp.isoc_delta - 1); 2068 /* simple frame load balancing */ 2069 x += xfer->endpoint->usb_uframe; 2070 break; 2071 } 2072 2073 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2074 2075 if ((xfer->endpoint->is_synced == 0) || 2076 (y < (xfer->nframes << shift)) || 2077 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2078 /* 2079 * If there is data underflow or the pipe 2080 * queue is empty we schedule the transfer a 2081 * few frames ahead of the current frame 2082 * position. Else two isochronous transfers 2083 * might overlap. 2084 */ 2085 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2086 xfer->endpoint->is_synced = 1; 2087 temp.do_isoc_sync = 1; 2088 2089 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2090 } 2091 2092 /* compute isochronous completion time */ 2093 2094 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2095 2096 xfer->isoc_time_complete = 2097 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2098 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2099 2100 x = 0; 2101 temp.isoc_frame = xfer->endpoint->isoc_next; 2102 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2103 2104 xfer->endpoint->isoc_next += xfer->nframes << shift; 2105 2106 } else if (xfer->flags_int.control_xfr) { 2107 2108 /* check if we should prepend a setup message */ 2109 2110 if (xfer->flags_int.control_hdr) { 2111 2112 temp.len = xfer->frlengths[0]; 2113 temp.pc = xfer->frbuffers + 0; 2114 temp.shortpkt = temp.len ? 1 : 0; 2115 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2116 temp.direction = 0; 2117 2118 /* check for last frame */ 2119 if (xfer->nframes == 1) { 2120 /* no STATUS stage yet, SETUP is last */ 2121 if (xfer->flags_int.control_act) 2122 temp.last_frame = 1; 2123 } 2124 2125 xhci_setup_generic_chain_sub(&temp); 2126 } 2127 x = 1; 2128 mult = 1; 2129 temp.isoc_delta = 0; 2130 temp.isoc_frame = 0; 2131 temp.trb_type = xfer->flags_int.control_did_data ? 2132 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2133 } else { 2134 x = 0; 2135 mult = 1; 2136 temp.isoc_delta = 0; 2137 temp.isoc_frame = 0; 2138 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2139 } 2140 2141 if (x != xfer->nframes) { 2142 /* set up page_cache pointer */ 2143 temp.pc = xfer->frbuffers + x; 2144 /* set endpoint direction */ 2145 temp.direction = UE_GET_DIR(xfer->endpointno); 2146 } 2147 2148 while (x != xfer->nframes) { 2149 2150 /* DATA0 / DATA1 message */ 2151 2152 temp.len = xfer->frlengths[x]; 2153 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2154 x != 0 && temp.multishort == 0); 2155 2156 x++; 2157 2158 if (x == xfer->nframes) { 2159 if (xfer->flags_int.control_xfr) { 2160 /* no STATUS stage yet, DATA is last */ 2161 if (xfer->flags_int.control_act) 2162 temp.last_frame = 1; 2163 } else { 2164 temp.last_frame = 1; 2165 } 2166 } 2167 if (temp.len == 0) { 2168 2169 /* make sure that we send an USB packet */ 2170 2171 temp.shortpkt = 0; 2172 2173 temp.tbc = 0; 2174 temp.tlbpc = mult - 1; 2175 2176 } else if (xfer->flags_int.isochronous_xfr) { 2177 2178 uint8_t tdpc; 2179 2180 /* 2181 * Isochronous transfers don't have short 2182 * packet termination: 2183 */ 2184 2185 temp.shortpkt = 1; 2186 2187 /* isochronous transfers have a transfer limit */ 2188 2189 if (temp.len > xfer->max_frame_size) 2190 temp.len = xfer->max_frame_size; 2191 2192 /* compute TD packet count */ 2193 tdpc = (temp.len + xfer->max_packet_size - 1) / 2194 xfer->max_packet_size; 2195 2196 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2197 temp.tlbpc = (tdpc % mult); 2198 2199 if (temp.tlbpc == 0) 2200 temp.tlbpc = mult - 1; 2201 else 2202 temp.tlbpc--; 2203 } else { 2204 2205 /* regular data transfer */ 2206 2207 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2208 } 2209 2210 xhci_setup_generic_chain_sub(&temp); 2211 2212 if (xfer->flags_int.isochronous_xfr) { 2213 temp.offset += xfer->frlengths[x - 1]; 2214 temp.isoc_frame += temp.isoc_delta; 2215 } else { 2216 /* get next Page Cache pointer */ 2217 temp.pc = xfer->frbuffers + x; 2218 } 2219 } 2220 2221 /* check if we should append a status stage */ 2222 2223 if (xfer->flags_int.control_xfr && 2224 !xfer->flags_int.control_act) { 2225 2226 /* 2227 * Send a DATA1 message and invert the current 2228 * endpoint direction. 2229 */ 2230 temp.step_td = (xfer->nframes != 0); 2231 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2232 temp.len = 0; 2233 temp.pc = NULL; 2234 temp.shortpkt = 0; 2235 temp.last_frame = 1; 2236 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2237 2238 xhci_setup_generic_chain_sub(&temp); 2239 } 2240 2241 td = temp.td; 2242 2243 /* must have at least one frame! */ 2244 2245 xfer->td_transfer_last = td; 2246 2247 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2248} 2249 2250static void 2251xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2252{ 2253 struct usb_page_search buf_res; 2254 struct xhci_dev_ctx_addr *pdctxa; 2255 2256 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2257 2258 pdctxa = buf_res.buffer; 2259 2260 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2261 2262 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2263 2264 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2265} 2266 2267static usb_error_t 2268xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2269{ 2270 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2271 struct usb_page_search buf_inp; 2272 struct xhci_input_dev_ctx *pinp; 2273 uint32_t temp; 2274 uint8_t index; 2275 uint8_t x; 2276 2277 index = udev->controller_slot_id; 2278 2279 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2280 2281 pinp = buf_inp.buffer; 2282 2283 if (drop) { 2284 mask &= XHCI_INCTX_NON_CTRL_MASK; 2285 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2286 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2287 } else { 2288 /* 2289 * Some hardware requires that we drop the endpoint 2290 * context before adding it again: 2291 */ 2292 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2293 mask & XHCI_INCTX_NON_CTRL_MASK); 2294 2295 /* Add new endpoint context */ 2296 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2297 2298 /* find most significant set bit */ 2299 for (x = 31; x != 1; x--) { 2300 if (mask & (1 << x)) 2301 break; 2302 } 2303 2304 /* adjust */ 2305 x--; 2306 2307 /* figure out the maximum number of contexts */ 2308 if (x > sc->sc_hw.devs[index].context_num) 2309 sc->sc_hw.devs[index].context_num = x; 2310 else 2311 x = sc->sc_hw.devs[index].context_num; 2312 2313 /* update number of contexts */ 2314 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2315 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2316 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2317 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2318 } 2319 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2320 return (0); 2321} 2322 2323static usb_error_t 2324xhci_configure_endpoint(struct usb_device *udev, 2325 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2326 uint16_t interval, uint8_t max_packet_count, 2327 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2328 uint16_t max_frame_size, uint8_t ep_mode) 2329{ 2330 struct usb_page_search buf_inp; 2331 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2332 struct xhci_input_dev_ctx *pinp; 2333 uint64_t ring_addr = pepext->physaddr; 2334 uint32_t temp; 2335 uint8_t index; 2336 uint8_t epno; 2337 uint8_t type; 2338 2339 index = udev->controller_slot_id; 2340 2341 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2342 2343 pinp = buf_inp.buffer; 2344 2345 epno = edesc->bEndpointAddress; 2346 type = edesc->bmAttributes & UE_XFERTYPE; 2347 2348 if (type == UE_CONTROL) 2349 epno |= UE_DIR_IN; 2350 2351 epno = XHCI_EPNO2EPID(epno); 2352 2353 if (epno == 0) 2354 return (USB_ERR_NO_PIPE); /* invalid */ 2355 2356 if (max_packet_count == 0) 2357 return (USB_ERR_BAD_BUFSIZE); 2358 2359 max_packet_count--; 2360 2361 if (mult == 0) 2362 return (USB_ERR_BAD_BUFSIZE); 2363 2364 /* store endpoint mode */ 2365 pepext->trb_ep_mode = ep_mode; 2366 usb_pc_cpu_flush(pepext->page_cache); 2367 2368 if (ep_mode == USB_EP_MODE_STREAMS) { 2369 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2370 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2371 XHCI_EPCTX_0_LSA_SET(1); 2372 2373 ring_addr += sizeof(struct xhci_trb) * 2374 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2375 } else { 2376 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2377 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2378 XHCI_EPCTX_0_LSA_SET(0); 2379 2380 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2381 } 2382 2383 switch (udev->speed) { 2384 case USB_SPEED_FULL: 2385 case USB_SPEED_LOW: 2386 /* 1ms -> 125us */ 2387 fps_shift += 3; 2388 break; 2389 default: 2390 break; 2391 } 2392 2393 switch (type) { 2394 case UE_INTERRUPT: 2395 if (fps_shift > 3) 2396 fps_shift--; 2397 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2398 break; 2399 case UE_ISOCHRONOUS: 2400 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2401 2402 switch (udev->speed) { 2403 case USB_SPEED_SUPER: 2404 if (mult > 3) 2405 mult = 3; 2406 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2407 max_packet_count /= mult; 2408 break; 2409 default: 2410 break; 2411 } 2412 break; 2413 default: 2414 break; 2415 } 2416 2417 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2418 2419 temp = 2420 XHCI_EPCTX_1_HID_SET(0) | 2421 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2422 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2423 2424 /* 2425 * Always enable the "three strikes and you are gone" feature 2426 * except for ISOCHRONOUS endpoints. This is suggested by 2427 * section 4.3.3 in the XHCI specification about device slot 2428 * initialisation. 2429 */ 2430 if (type != UE_ISOCHRONOUS) 2431 temp |= XHCI_EPCTX_1_CERR_SET(3); 2432 2433 switch (type) { 2434 case UE_CONTROL: 2435 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2436 break; 2437 case UE_ISOCHRONOUS: 2438 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2439 break; 2440 case UE_BULK: 2441 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2442 break; 2443 default: 2444 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2445 break; 2446 } 2447 2448 /* check for IN direction */ 2449 if (epno & 1) 2450 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2451 2452 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2453 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2454 2455 switch (edesc->bmAttributes & UE_XFERTYPE) { 2456 case UE_INTERRUPT: 2457 case UE_ISOCHRONOUS: 2458 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2459 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2460 max_frame_size)); 2461 break; 2462 case UE_CONTROL: 2463 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2464 break; 2465 default: 2466 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2467 break; 2468 } 2469 2470 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2471 2472#ifdef USB_DEBUG 2473 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2474#endif 2475 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2476 2477 return (0); /* success */ 2478} 2479 2480static usb_error_t 2481xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2482{ 2483 struct xhci_endpoint_ext *pepext; 2484 struct usb_endpoint_ss_comp_descriptor *ecomp; 2485 usb_stream_t x; 2486 2487 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2488 xfer->endpoint->edesc); 2489 2490 ecomp = xfer->endpoint->ecomp; 2491 2492 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2493 uint64_t temp; 2494 2495 /* halt any transfers */ 2496 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2497 2498 /* compute start of TRB ring for stream "x" */ 2499 temp = pepext->physaddr + 2500 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2501 XHCI_SCTX_0_SCT_SEC_TR_RING; 2502 2503 /* make tree structure */ 2504 pepext->trb[(XHCI_MAX_TRANSFERS * 2505 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2506 2507 /* reserved fields */ 2508 pepext->trb[(XHCI_MAX_TRANSFERS * 2509 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2510 pepext->trb[(XHCI_MAX_TRANSFERS * 2511 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2512 } 2513 usb_pc_cpu_flush(pepext->page_cache); 2514 2515 return (xhci_configure_endpoint(xfer->xroot->udev, 2516 xfer->endpoint->edesc, pepext, 2517 xfer->interval, xfer->max_packet_count, 2518 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2519 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2520 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2521} 2522 2523static usb_error_t 2524xhci_configure_device(struct usb_device *udev) 2525{ 2526 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2527 struct usb_page_search buf_inp; 2528 struct usb_page_cache *pcinp; 2529 struct xhci_input_dev_ctx *pinp; 2530 struct usb_device *hubdev; 2531 uint32_t temp; 2532 uint32_t route; 2533 uint32_t rh_port; 2534 uint8_t is_hub; 2535 uint8_t index; 2536 uint8_t depth; 2537 2538 index = udev->controller_slot_id; 2539 2540 DPRINTF("index=%u\n", index); 2541 2542 pcinp = &sc->sc_hw.devs[index].input_pc; 2543 2544 usbd_get_page(pcinp, 0, &buf_inp); 2545 2546 pinp = buf_inp.buffer; 2547 2548 rh_port = 0; 2549 route = 0; 2550 2551 /* figure out route string and root HUB port number */ 2552 2553 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2554 2555 if (hubdev->parent_hub == NULL) 2556 break; 2557 2558 depth = hubdev->parent_hub->depth; 2559 2560 /* 2561 * NOTE: HS/FS/LS devices and the SS root HUB can have 2562 * more than 15 ports 2563 */ 2564 2565 rh_port = hubdev->port_no; 2566 2567 if (depth == 0) 2568 break; 2569 2570 if (rh_port > 15) 2571 rh_port = 15; 2572 2573 if (depth < 6) 2574 route |= rh_port << (4 * (depth - 1)); 2575 } 2576 2577 DPRINTF("Route=0x%08x\n", route); 2578 2579 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2580 XHCI_SCTX_0_CTX_NUM_SET( 2581 sc->sc_hw.devs[index].context_num + 1); 2582 2583 switch (udev->speed) { 2584 case USB_SPEED_LOW: 2585 temp |= XHCI_SCTX_0_SPEED_SET(2); 2586 if (udev->parent_hs_hub != NULL && 2587 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2588 UDPROTO_HSHUBMTT) { 2589 DPRINTF("Device inherits MTT\n"); 2590 temp |= XHCI_SCTX_0_MTT_SET(1); 2591 } 2592 break; 2593 case USB_SPEED_HIGH: 2594 temp |= XHCI_SCTX_0_SPEED_SET(3); 2595 if (sc->sc_hw.devs[index].nports != 0 && 2596 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2597 DPRINTF("HUB supports MTT\n"); 2598 temp |= XHCI_SCTX_0_MTT_SET(1); 2599 } 2600 break; 2601 case USB_SPEED_FULL: 2602 temp |= XHCI_SCTX_0_SPEED_SET(1); 2603 if (udev->parent_hs_hub != NULL && 2604 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2605 UDPROTO_HSHUBMTT) { 2606 DPRINTF("Device inherits MTT\n"); 2607 temp |= XHCI_SCTX_0_MTT_SET(1); 2608 } 2609 break; 2610 default: 2611 temp |= XHCI_SCTX_0_SPEED_SET(4); 2612 break; 2613 } 2614 2615 is_hub = sc->sc_hw.devs[index].nports != 0 && 2616 (udev->speed == USB_SPEED_SUPER || 2617 udev->speed == USB_SPEED_HIGH); 2618 2619 if (is_hub) 2620 temp |= XHCI_SCTX_0_HUB_SET(1); 2621 2622 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2623 2624 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2625 2626 if (is_hub) { 2627 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2628 sc->sc_hw.devs[index].nports); 2629 } 2630 2631 switch (udev->speed) { 2632 case USB_SPEED_SUPER: 2633 switch (sc->sc_hw.devs[index].state) { 2634 case XHCI_ST_ADDRESSED: 2635 case XHCI_ST_CONFIGURED: 2636 /* enable power save */ 2637 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2638 break; 2639 default: 2640 /* disable power save */ 2641 break; 2642 } 2643 break; 2644 default: 2645 break; 2646 } 2647 2648 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2649 2650 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2651 2652 if (is_hub) { 2653 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2654 sc->sc_hw.devs[index].tt); 2655 } 2656 2657 hubdev = udev->parent_hs_hub; 2658 2659 /* check if we should activate the transaction translator */ 2660 switch (udev->speed) { 2661 case USB_SPEED_FULL: 2662 case USB_SPEED_LOW: 2663 if (hubdev != NULL) { 2664 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2665 hubdev->controller_slot_id); 2666 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2667 udev->hs_port_no); 2668 } 2669 break; 2670 default: 2671 break; 2672 } 2673 2674 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2675 2676 /* 2677 * These fields should be initialized to zero, according to 2678 * XHCI section 6.2.2 - slot context: 2679 */ 2680 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2681 XHCI_SCTX_3_SLOT_STATE_SET(0); 2682 2683 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2684 2685#ifdef USB_DEBUG 2686 xhci_dump_device(sc, &pinp->ctx_slot); 2687#endif 2688 usb_pc_cpu_flush(pcinp); 2689 2690 return (0); /* success */ 2691} 2692 2693static usb_error_t 2694xhci_alloc_device_ext(struct usb_device *udev) 2695{ 2696 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2697 struct usb_page_search buf_dev; 2698 struct usb_page_search buf_ep; 2699 struct xhci_trb *trb; 2700 struct usb_page_cache *pc; 2701 struct usb_page *pg; 2702 uint64_t addr; 2703 uint8_t index; 2704 uint8_t i; 2705 2706 index = udev->controller_slot_id; 2707 2708 pc = &sc->sc_hw.devs[index].device_pc; 2709 pg = &sc->sc_hw.devs[index].device_pg; 2710 2711 /* need to initialize the page cache */ 2712 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2713 2714 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2715 (2 * sizeof(struct xhci_dev_ctx)) : 2716 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2717 goto error; 2718 2719 usbd_get_page(pc, 0, &buf_dev); 2720 2721 pc = &sc->sc_hw.devs[index].input_pc; 2722 pg = &sc->sc_hw.devs[index].input_pg; 2723 2724 /* need to initialize the page cache */ 2725 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2726 2727 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2728 (2 * sizeof(struct xhci_input_dev_ctx)) : 2729 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2730 goto error; 2731 } 2732 2733 /* initialize all endpoint LINK TRBs */ 2734 2735 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2736 2737 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2738 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2739 2740 /* need to initialize the page cache */ 2741 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2742 2743 if (usb_pc_alloc_mem(pc, pg, 2744 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2745 goto error; 2746 } 2747 2748 /* lookup endpoint TRB ring */ 2749 usbd_get_page(pc, 0, &buf_ep); 2750 2751 /* get TRB pointer */ 2752 trb = buf_ep.buffer; 2753 trb += XHCI_MAX_TRANSFERS - 1; 2754 2755 /* get TRB start address */ 2756 addr = buf_ep.physaddr; 2757 2758 /* create LINK TRB */ 2759 trb->qwTrb0 = htole64(addr); 2760 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2761 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2762 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2763 2764 usb_pc_cpu_flush(pc); 2765 } 2766 2767 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2768 2769 return (0); 2770 2771error: 2772 xhci_free_device_ext(udev); 2773 2774 return (USB_ERR_NOMEM); 2775} 2776 2777static void 2778xhci_free_device_ext(struct usb_device *udev) 2779{ 2780 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2781 uint8_t index; 2782 uint8_t i; 2783 2784 index = udev->controller_slot_id; 2785 xhci_set_slot_pointer(sc, index, 0); 2786 2787 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2788 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2789 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2790 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2791} 2792 2793static struct xhci_endpoint_ext * 2794xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2795{ 2796 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2797 struct xhci_endpoint_ext *pepext; 2798 struct usb_page_cache *pc; 2799 struct usb_page_search buf_ep; 2800 uint8_t epno; 2801 uint8_t index; 2802 2803 epno = edesc->bEndpointAddress; 2804 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2805 epno |= UE_DIR_IN; 2806 2807 epno = XHCI_EPNO2EPID(epno); 2808 2809 index = udev->controller_slot_id; 2810 2811 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2812 2813 usbd_get_page(pc, 0, &buf_ep); 2814 2815 pepext = &sc->sc_hw.devs[index].endp[epno]; 2816 pepext->page_cache = pc; 2817 pepext->trb = buf_ep.buffer; 2818 pepext->physaddr = buf_ep.physaddr; 2819 2820 return (pepext); 2821} 2822 2823static void 2824xhci_endpoint_doorbell(struct usb_xfer *xfer) 2825{ 2826 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2827 uint8_t epno; 2828 uint8_t index; 2829 2830 epno = xfer->endpointno; 2831 if (xfer->flags_int.control_xfr) 2832 epno |= UE_DIR_IN; 2833 2834 epno = XHCI_EPNO2EPID(epno); 2835 index = xfer->xroot->udev->controller_slot_id; 2836 2837 if (xfer->xroot->udev->flags.self_suspended == 0) { 2838 XWRITE4(sc, door, XHCI_DOORBELL(index), 2839 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2840 } 2841} 2842 2843static void 2844xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2845{ 2846 struct xhci_endpoint_ext *pepext; 2847 2848 if (xfer->flags_int.bandwidth_reclaimed) { 2849 xfer->flags_int.bandwidth_reclaimed = 0; 2850 2851 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2852 xfer->endpoint->edesc); 2853 2854 pepext->trb_used[xfer->stream_id]--; 2855 2856 pepext->xfer[xfer->qh_pos] = NULL; 2857 2858 if (error && pepext->trb_running != 0) { 2859 pepext->trb_halted = 1; 2860 pepext->trb_running = 0; 2861 } 2862 } 2863} 2864 2865static usb_error_t 2866xhci_transfer_insert(struct usb_xfer *xfer) 2867{ 2868 struct xhci_td *td_first; 2869 struct xhci_td *td_last; 2870 struct xhci_trb *trb_link; 2871 struct xhci_endpoint_ext *pepext; 2872 uint64_t addr; 2873 usb_stream_t id; 2874 uint8_t i; 2875 uint8_t inext; 2876 uint8_t trb_limit; 2877 2878 DPRINTFN(8, "\n"); 2879 2880 id = xfer->stream_id; 2881 2882 /* check if already inserted */ 2883 if (xfer->flags_int.bandwidth_reclaimed) { 2884 DPRINTFN(8, "Already in schedule\n"); 2885 return (0); 2886 } 2887 2888 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2889 xfer->endpoint->edesc); 2890 2891 td_first = xfer->td_transfer_first; 2892 td_last = xfer->td_transfer_last; 2893 addr = pepext->physaddr; 2894 2895 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2896 case UE_CONTROL: 2897 case UE_INTERRUPT: 2898 /* single buffered */ 2899 trb_limit = 1; 2900 break; 2901 default: 2902 /* multi buffered */ 2903 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2904 break; 2905 } 2906 2907 if (pepext->trb_used[id] >= trb_limit) { 2908 DPRINTFN(8, "Too many TDs queued.\n"); 2909 return (USB_ERR_NOMEM); 2910 } 2911 2912 /* check for stopped condition, after putting transfer on interrupt queue */ 2913 if (pepext->trb_running == 0) { 2914 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2915 2916 DPRINTFN(8, "Not running\n"); 2917 2918 /* start configuration */ 2919 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2920 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2921 return (0); 2922 } 2923 2924 pepext->trb_used[id]++; 2925 2926 /* get current TRB index */ 2927 i = pepext->trb_index[id]; 2928 2929 /* get next TRB index */ 2930 inext = (i + 1); 2931 2932 /* the last entry of the ring is a hardcoded link TRB */ 2933 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2934 inext = 0; 2935 2936 /* store next TRB index, before stream ID offset is added */ 2937 pepext->trb_index[id] = inext; 2938 2939 /* offset for stream */ 2940 i += id * XHCI_MAX_TRANSFERS; 2941 inext += id * XHCI_MAX_TRANSFERS; 2942 2943 /* compute terminating return address */ 2944 addr += (inext * sizeof(struct xhci_trb)); 2945 2946 /* compute link TRB pointer */ 2947 trb_link = td_last->td_trb + td_last->ntrb; 2948 2949 /* update next pointer of last link TRB */ 2950 trb_link->qwTrb0 = htole64(addr); 2951 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2952 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2953 XHCI_TRB_3_CYCLE_BIT | 2954 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2955 2956#ifdef USB_DEBUG 2957 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2958#endif 2959 usb_pc_cpu_flush(td_last->page_cache); 2960 2961 /* write ahead chain end marker */ 2962 2963 pepext->trb[inext].qwTrb0 = 0; 2964 pepext->trb[inext].dwTrb2 = 0; 2965 pepext->trb[inext].dwTrb3 = 0; 2966 2967 /* update next pointer of link TRB */ 2968 2969 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2970 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2971 2972#ifdef USB_DEBUG 2973 xhci_dump_trb(&pepext->trb[i]); 2974#endif 2975 usb_pc_cpu_flush(pepext->page_cache); 2976 2977 /* toggle cycle bit which activates the transfer chain */ 2978 2979 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2980 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2981 2982 usb_pc_cpu_flush(pepext->page_cache); 2983 2984 DPRINTF("qh_pos = %u\n", i); 2985 2986 pepext->xfer[i] = xfer; 2987 2988 xfer->qh_pos = i; 2989 2990 xfer->flags_int.bandwidth_reclaimed = 1; 2991 2992 xhci_endpoint_doorbell(xfer); 2993 2994 return (0); 2995} 2996 2997static void 2998xhci_root_intr(struct xhci_softc *sc) 2999{ 3000 uint16_t i; 3001 3002 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3003 3004 /* clear any old interrupt data */ 3005 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 3006 3007 for (i = 1; i <= sc->sc_noport; i++) { 3008 /* pick out CHANGE bits from the status register */ 3009 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 3010 XHCI_PS_CSC | XHCI_PS_PEC | 3011 XHCI_PS_OCC | XHCI_PS_WRC | 3012 XHCI_PS_PRC | XHCI_PS_PLC | 3013 XHCI_PS_CEC)) { 3014 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 3015 DPRINTF("port %d changed\n", i); 3016 } 3017 } 3018 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3019 sizeof(sc->sc_hub_idata)); 3020} 3021 3022/*------------------------------------------------------------------------* 3023 * xhci_device_done - XHCI done handler 3024 * 3025 * NOTE: This function can be called two times in a row on 3026 * the same USB transfer. From close and from interrupt. 3027 *------------------------------------------------------------------------*/ 3028static void 3029xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3030{ 3031 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3032 xfer, xfer->endpoint, error); 3033 3034 /* remove transfer from HW queue */ 3035 xhci_transfer_remove(xfer, error); 3036 3037 /* dequeue transfer and start next transfer */ 3038 usbd_transfer_done(xfer, error); 3039} 3040 3041/*------------------------------------------------------------------------* 3042 * XHCI data transfer support (generic type) 3043 *------------------------------------------------------------------------*/ 3044static void 3045xhci_device_generic_open(struct usb_xfer *xfer) 3046{ 3047 if (xfer->flags_int.isochronous_xfr) { 3048 switch (xfer->xroot->udev->speed) { 3049 case USB_SPEED_FULL: 3050 break; 3051 default: 3052 usb_hs_bandwidth_alloc(xfer); 3053 break; 3054 } 3055 } 3056} 3057 3058static void 3059xhci_device_generic_close(struct usb_xfer *xfer) 3060{ 3061 DPRINTF("\n"); 3062 3063 xhci_device_done(xfer, USB_ERR_CANCELLED); 3064 3065 if (xfer->flags_int.isochronous_xfr) { 3066 switch (xfer->xroot->udev->speed) { 3067 case USB_SPEED_FULL: 3068 break; 3069 default: 3070 usb_hs_bandwidth_free(xfer); 3071 break; 3072 } 3073 } 3074} 3075 3076static void 3077xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3078 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3079{ 3080 struct usb_xfer *xfer; 3081 3082 /* check if there is a current transfer */ 3083 xfer = ep->endpoint_q[stream_id].curr; 3084 if (xfer == NULL) 3085 return; 3086 3087 /* 3088 * Check if the current transfer is started and then pickup 3089 * the next one, if any. Else wait for next start event due to 3090 * block on failure feature. 3091 */ 3092 if (!xfer->flags_int.bandwidth_reclaimed) 3093 return; 3094 3095 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3096 if (xfer == NULL) { 3097 /* 3098 * In case of enter we have to consider that the 3099 * transfer is queued by the USB core after the enter 3100 * method is called. 3101 */ 3102 xfer = enter_xfer; 3103 3104 if (xfer == NULL) 3105 return; 3106 } 3107 3108 /* try to multi buffer */ 3109 xhci_transfer_insert(xfer); 3110} 3111 3112static void 3113xhci_device_generic_enter(struct usb_xfer *xfer) 3114{ 3115 DPRINTF("\n"); 3116 3117 /* set up TD's and QH */ 3118 xhci_setup_generic_chain(xfer); 3119 3120 xhci_device_generic_multi_enter(xfer->endpoint, 3121 xfer->stream_id, xfer); 3122} 3123 3124static void 3125xhci_device_generic_start(struct usb_xfer *xfer) 3126{ 3127 DPRINTF("\n"); 3128 3129 /* try to insert xfer on HW queue */ 3130 xhci_transfer_insert(xfer); 3131 3132 /* try to multi buffer */ 3133 xhci_device_generic_multi_enter(xfer->endpoint, 3134 xfer->stream_id, NULL); 3135 3136 /* add transfer last on interrupt queue */ 3137 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3138 3139 /* start timeout, if any */ 3140 if (xfer->timeout != 0) 3141 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3142} 3143 3144struct usb_pipe_methods xhci_device_generic_methods = 3145{ 3146 .open = xhci_device_generic_open, 3147 .close = xhci_device_generic_close, 3148 .enter = xhci_device_generic_enter, 3149 .start = xhci_device_generic_start, 3150}; 3151 3152/*------------------------------------------------------------------------* 3153 * xhci root HUB support 3154 *------------------------------------------------------------------------* 3155 * Simulate a hardware HUB by handling all the necessary requests. 3156 *------------------------------------------------------------------------*/ 3157 3158#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3159 3160static const 3161struct usb_device_descriptor xhci_devd = 3162{ 3163 .bLength = sizeof(xhci_devd), 3164 .bDescriptorType = UDESC_DEVICE, /* type */ 3165 HSETW(.bcdUSB, 0x0300), /* USB version */ 3166 .bDeviceClass = UDCLASS_HUB, /* class */ 3167 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3168 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3169 .bMaxPacketSize = 9, /* max packet size */ 3170 HSETW(.idVendor, 0x0000), /* vendor */ 3171 HSETW(.idProduct, 0x0000), /* product */ 3172 HSETW(.bcdDevice, 0x0100), /* device version */ 3173 .iManufacturer = 1, 3174 .iProduct = 2, 3175 .iSerialNumber = 0, 3176 .bNumConfigurations = 1, /* # of configurations */ 3177}; 3178 3179static const 3180struct xhci_bos_desc xhci_bosd = { 3181 .bosd = { 3182 .bLength = sizeof(xhci_bosd.bosd), 3183 .bDescriptorType = UDESC_BOS, 3184 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3185 .bNumDeviceCaps = 3, 3186 }, 3187 .usb2extd = { 3188 .bLength = sizeof(xhci_bosd.usb2extd), 3189 .bDescriptorType = 1, 3190 .bDevCapabilityType = 2, 3191 .bmAttributes[0] = 2, 3192 }, 3193 .usbdcd = { 3194 .bLength = sizeof(xhci_bosd.usbdcd), 3195 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3196 .bDevCapabilityType = 3, 3197 .bmAttributes = 0, /* XXX */ 3198 HSETW(.wSpeedsSupported, 0x000C), 3199 .bFunctionalitySupport = 8, 3200 .bU1DevExitLat = 255, /* dummy - not used */ 3201 .wU2DevExitLat = { 0x00, 0x08 }, 3202 }, 3203 .cidd = { 3204 .bLength = sizeof(xhci_bosd.cidd), 3205 .bDescriptorType = 1, 3206 .bDevCapabilityType = 4, 3207 .bReserved = 0, 3208 .bContainerID = 0, /* XXX */ 3209 }, 3210}; 3211 3212static const 3213struct xhci_config_desc xhci_confd = { 3214 .confd = { 3215 .bLength = sizeof(xhci_confd.confd), 3216 .bDescriptorType = UDESC_CONFIG, 3217 .wTotalLength[0] = sizeof(xhci_confd), 3218 .bNumInterface = 1, 3219 .bConfigurationValue = 1, 3220 .iConfiguration = 0, 3221 .bmAttributes = UC_SELF_POWERED, 3222 .bMaxPower = 0 /* max power */ 3223 }, 3224 .ifcd = { 3225 .bLength = sizeof(xhci_confd.ifcd), 3226 .bDescriptorType = UDESC_INTERFACE, 3227 .bNumEndpoints = 1, 3228 .bInterfaceClass = UICLASS_HUB, 3229 .bInterfaceSubClass = UISUBCLASS_HUB, 3230 .bInterfaceProtocol = 0, 3231 }, 3232 .endpd = { 3233 .bLength = sizeof(xhci_confd.endpd), 3234 .bDescriptorType = UDESC_ENDPOINT, 3235 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3236 .bmAttributes = UE_INTERRUPT, 3237 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3238 .bInterval = 255, 3239 }, 3240 .endpcd = { 3241 .bLength = sizeof(xhci_confd.endpcd), 3242 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3243 .bMaxBurst = 0, 3244 .bmAttributes = 0, 3245 }, 3246}; 3247 3248static const 3249struct usb_hub_ss_descriptor xhci_hubd = { 3250 .bLength = sizeof(xhci_hubd), 3251 .bDescriptorType = UDESC_SS_HUB, 3252}; 3253 3254static usb_error_t 3255xhci_roothub_exec(struct usb_device *udev, 3256 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3257{ 3258 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3259 const char *str_ptr; 3260 const void *ptr; 3261 uint32_t port; 3262 uint32_t v; 3263 uint16_t len; 3264 uint16_t i; 3265 uint16_t value; 3266 uint16_t index; 3267 uint8_t j; 3268 usb_error_t err; 3269 3270 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3271 3272 /* buffer reset */ 3273 ptr = (const void *)&sc->sc_hub_desc; 3274 len = 0; 3275 err = 0; 3276 3277 value = UGETW(req->wValue); 3278 index = UGETW(req->wIndex); 3279 3280 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3281 "wValue=0x%04x wIndex=0x%04x\n", 3282 req->bmRequestType, req->bRequest, 3283 UGETW(req->wLength), value, index); 3284 3285#define C(x,y) ((x) | ((y) << 8)) 3286 switch (C(req->bRequest, req->bmRequestType)) { 3287 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3288 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3289 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3290 /* 3291 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3292 * for the integrated root hub. 3293 */ 3294 break; 3295 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3296 len = 1; 3297 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3298 break; 3299 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3300 switch (value >> 8) { 3301 case UDESC_DEVICE: 3302 if ((value & 0xff) != 0) { 3303 err = USB_ERR_IOERROR; 3304 goto done; 3305 } 3306 len = sizeof(xhci_devd); 3307 ptr = (const void *)&xhci_devd; 3308 break; 3309 3310 case UDESC_BOS: 3311 if ((value & 0xff) != 0) { 3312 err = USB_ERR_IOERROR; 3313 goto done; 3314 } 3315 len = sizeof(xhci_bosd); 3316 ptr = (const void *)&xhci_bosd; 3317 break; 3318 3319 case UDESC_CONFIG: 3320 if ((value & 0xff) != 0) { 3321 err = USB_ERR_IOERROR; 3322 goto done; 3323 } 3324 len = sizeof(xhci_confd); 3325 ptr = (const void *)&xhci_confd; 3326 break; 3327 3328 case UDESC_STRING: 3329 switch (value & 0xff) { 3330 case 0: /* Language table */ 3331 str_ptr = "\001"; 3332 break; 3333 3334 case 1: /* Vendor */ 3335 str_ptr = sc->sc_vendor; 3336 break; 3337 3338 case 2: /* Product */ 3339 str_ptr = "XHCI root HUB"; 3340 break; 3341 3342 default: 3343 str_ptr = ""; 3344 break; 3345 } 3346 3347 len = usb_make_str_desc( 3348 sc->sc_hub_desc.temp, 3349 sizeof(sc->sc_hub_desc.temp), 3350 str_ptr); 3351 break; 3352 3353 default: 3354 err = USB_ERR_IOERROR; 3355 goto done; 3356 } 3357 break; 3358 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3359 len = 1; 3360 sc->sc_hub_desc.temp[0] = 0; 3361 break; 3362 case C(UR_GET_STATUS, UT_READ_DEVICE): 3363 len = 2; 3364 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3365 break; 3366 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3367 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3368 len = 2; 3369 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3370 break; 3371 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3372 if (value >= XHCI_MAX_DEVICES) { 3373 err = USB_ERR_IOERROR; 3374 goto done; 3375 } 3376 break; 3377 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3378 if (value != 0 && value != 1) { 3379 err = USB_ERR_IOERROR; 3380 goto done; 3381 } 3382 sc->sc_conf = value; 3383 break; 3384 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3385 break; 3386 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3387 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3388 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3389 err = USB_ERR_IOERROR; 3390 goto done; 3391 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3392 break; 3393 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3394 break; 3395 /* Hub requests */ 3396 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3397 break; 3398 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3399 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3400 3401 if ((index < 1) || 3402 (index > sc->sc_noport)) { 3403 err = USB_ERR_IOERROR; 3404 goto done; 3405 } 3406 port = XHCI_PORTSC(index); 3407 3408 v = XREAD4(sc, oper, port); 3409 i = XHCI_PS_PLS_GET(v); 3410 v &= ~XHCI_PS_CLEAR; 3411 3412 switch (value) { 3413 case UHF_C_BH_PORT_RESET: 3414 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3415 break; 3416 case UHF_C_PORT_CONFIG_ERROR: 3417 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3418 break; 3419 case UHF_C_PORT_SUSPEND: 3420 case UHF_C_PORT_LINK_STATE: 3421 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3422 break; 3423 case UHF_C_PORT_CONNECTION: 3424 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3425 break; 3426 case UHF_C_PORT_ENABLE: 3427 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3428 break; 3429 case UHF_C_PORT_OVER_CURRENT: 3430 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3431 break; 3432 case UHF_C_PORT_RESET: 3433 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3434 break; 3435 case UHF_PORT_ENABLE: 3436 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3437 break; 3438 case UHF_PORT_POWER: 3439 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3440 break; 3441 case UHF_PORT_INDICATOR: 3442 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3443 break; 3444 case UHF_PORT_SUSPEND: 3445 3446 /* U3 -> U15 */ 3447 if (i == 3) { 3448 XWRITE4(sc, oper, port, v | 3449 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3450 } 3451 3452 /* wait 20ms for resume sequence to complete */ 3453 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3454 3455 /* U0 */ 3456 XWRITE4(sc, oper, port, v | 3457 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3458 break; 3459 default: 3460 err = USB_ERR_IOERROR; 3461 goto done; 3462 } 3463 break; 3464 3465 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3466 if ((value & 0xff) != 0) { 3467 err = USB_ERR_IOERROR; 3468 goto done; 3469 } 3470 3471 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3472 3473 sc->sc_hub_desc.hubd = xhci_hubd; 3474 3475 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3476 3477 if (XHCI_HCS0_PPC(v)) 3478 i = UHD_PWR_INDIVIDUAL; 3479 else 3480 i = UHD_PWR_GANGED; 3481 3482 if (XHCI_HCS0_PIND(v)) 3483 i |= UHD_PORT_IND; 3484 3485 i |= UHD_OC_INDIVIDUAL; 3486 3487 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3488 3489 /* see XHCI section 5.4.9: */ 3490 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3491 3492 for (j = 1; j <= sc->sc_noport; j++) { 3493 3494 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3495 if (v & XHCI_PS_DR) { 3496 sc->sc_hub_desc.hubd. 3497 DeviceRemovable[j / 8] |= 1U << (j % 8); 3498 } 3499 } 3500 len = sc->sc_hub_desc.hubd.bLength; 3501 break; 3502 3503 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3504 len = 16; 3505 memset(sc->sc_hub_desc.temp, 0, 16); 3506 break; 3507 3508 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3509 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3510 3511 if ((index < 1) || 3512 (index > sc->sc_noport)) { 3513 err = USB_ERR_IOERROR; 3514 goto done; 3515 } 3516 3517 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3518 3519 DPRINTFN(9, "port status=0x%08x\n", v); 3520 3521 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3522 3523 switch (XHCI_PS_SPEED_GET(v)) { 3524 case 3: 3525 i |= UPS_HIGH_SPEED; 3526 break; 3527 case 2: 3528 i |= UPS_LOW_SPEED; 3529 break; 3530 case 1: 3531 /* FULL speed */ 3532 break; 3533 default: 3534 i |= UPS_OTHER_SPEED; 3535 break; 3536 } 3537 3538 if (v & XHCI_PS_CCS) 3539 i |= UPS_CURRENT_CONNECT_STATUS; 3540 if (v & XHCI_PS_PED) 3541 i |= UPS_PORT_ENABLED; 3542 if (v & XHCI_PS_OCA) 3543 i |= UPS_OVERCURRENT_INDICATOR; 3544 if (v & XHCI_PS_PR) 3545 i |= UPS_RESET; 3546 if (v & XHCI_PS_PP) { 3547 /* 3548 * The USB 3.0 RH is using the 3549 * USB 2.0's power bit 3550 */ 3551 i |= UPS_PORT_POWER; 3552 } 3553 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3554 3555 i = 0; 3556 if (v & XHCI_PS_CSC) 3557 i |= UPS_C_CONNECT_STATUS; 3558 if (v & XHCI_PS_PEC) 3559 i |= UPS_C_PORT_ENABLED; 3560 if (v & XHCI_PS_OCC) 3561 i |= UPS_C_OVERCURRENT_INDICATOR; 3562 if (v & XHCI_PS_WRC) 3563 i |= UPS_C_BH_PORT_RESET; 3564 if (v & XHCI_PS_PRC) 3565 i |= UPS_C_PORT_RESET; 3566 if (v & XHCI_PS_PLC) 3567 i |= UPS_C_PORT_LINK_STATE; 3568 if (v & XHCI_PS_CEC) 3569 i |= UPS_C_PORT_CONFIG_ERROR; 3570 3571 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3572 len = sizeof(sc->sc_hub_desc.ps); 3573 break; 3574 3575 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3576 err = USB_ERR_IOERROR; 3577 goto done; 3578 3579 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3580 break; 3581 3582 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3583 3584 i = index >> 8; 3585 index &= 0x00FF; 3586 3587 if ((index < 1) || 3588 (index > sc->sc_noport)) { 3589 err = USB_ERR_IOERROR; 3590 goto done; 3591 } 3592 3593 port = XHCI_PORTSC(index); 3594 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3595 3596 switch (value) { 3597 case UHF_PORT_U1_TIMEOUT: 3598 if (XHCI_PS_SPEED_GET(v) != 4) { 3599 err = USB_ERR_IOERROR; 3600 goto done; 3601 } 3602 port = XHCI_PORTPMSC(index); 3603 v = XREAD4(sc, oper, port); 3604 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3605 v |= XHCI_PM3_U1TO_SET(i); 3606 XWRITE4(sc, oper, port, v); 3607 break; 3608 case UHF_PORT_U2_TIMEOUT: 3609 if (XHCI_PS_SPEED_GET(v) != 4) { 3610 err = USB_ERR_IOERROR; 3611 goto done; 3612 } 3613 port = XHCI_PORTPMSC(index); 3614 v = XREAD4(sc, oper, port); 3615 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3616 v |= XHCI_PM3_U2TO_SET(i); 3617 XWRITE4(sc, oper, port, v); 3618 break; 3619 case UHF_BH_PORT_RESET: 3620 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3621 break; 3622 case UHF_PORT_LINK_STATE: 3623 XWRITE4(sc, oper, port, v | 3624 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3625 /* 4ms settle time */ 3626 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3627 break; 3628 case UHF_PORT_ENABLE: 3629 DPRINTFN(3, "set port enable %d\n", index); 3630 break; 3631 case UHF_PORT_SUSPEND: 3632 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3633 j = XHCI_PS_SPEED_GET(v); 3634 if ((j < 1) || (j > 3)) { 3635 /* non-supported speed */ 3636 err = USB_ERR_IOERROR; 3637 goto done; 3638 } 3639 XWRITE4(sc, oper, port, v | 3640 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3641 break; 3642 case UHF_PORT_RESET: 3643 DPRINTFN(6, "reset port %d\n", index); 3644 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3645 break; 3646 case UHF_PORT_POWER: 3647 DPRINTFN(3, "set port power %d\n", index); 3648 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3649 break; 3650 case UHF_PORT_TEST: 3651 DPRINTFN(3, "set port test %d\n", index); 3652 break; 3653 case UHF_PORT_INDICATOR: 3654 DPRINTFN(3, "set port indicator %d\n", index); 3655 3656 v &= ~XHCI_PS_PIC_SET(3); 3657 v |= XHCI_PS_PIC_SET(1); 3658 3659 XWRITE4(sc, oper, port, v); 3660 break; 3661 default: 3662 err = USB_ERR_IOERROR; 3663 goto done; 3664 } 3665 break; 3666 3667 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3668 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3669 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3670 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3671 break; 3672 default: 3673 err = USB_ERR_IOERROR; 3674 goto done; 3675 } 3676done: 3677 *plength = len; 3678 *pptr = ptr; 3679 return (err); 3680} 3681 3682static void 3683xhci_xfer_setup(struct usb_setup_params *parm) 3684{ 3685 struct usb_page_search page_info; 3686 struct usb_page_cache *pc; 3687 struct xhci_softc *sc; 3688 struct usb_xfer *xfer; 3689 void *last_obj; 3690 uint32_t ntd; 3691 uint32_t n; 3692 3693 sc = XHCI_BUS2SC(parm->udev->bus); 3694 xfer = parm->curr_xfer; 3695 3696 /* 3697 * The proof for the "ntd" formula is illustrated like this: 3698 * 3699 * +------------------------------------+ 3700 * | | 3701 * | |remainder -> | 3702 * | +-----+---+ | 3703 * | | xxx | x | frm 0 | 3704 * | +-----+---++ | 3705 * | | xxx | xx | frm 1 | 3706 * | +-----+----+ | 3707 * | ... | 3708 * +------------------------------------+ 3709 * 3710 * "xxx" means a completely full USB transfer descriptor 3711 * 3712 * "x" and "xx" means a short USB packet 3713 * 3714 * For the remainder of an USB transfer modulo 3715 * "max_data_length" we need two USB transfer descriptors. 3716 * One to transfer the remaining data and one to finalise with 3717 * a zero length packet in case the "force_short_xfer" flag is 3718 * set. We only need two USB transfer descriptors in the case 3719 * where the transfer length of the first one is a factor of 3720 * "max_frame_size". The rest of the needed USB transfer 3721 * descriptors is given by the buffer size divided by the 3722 * maximum data payload. 3723 */ 3724 parm->hc_max_packet_size = 0x400; 3725 parm->hc_max_packet_count = 16 * 3; 3726 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3727 3728 xfer->flags_int.bdma_enable = 1; 3729 3730 usbd_transfer_setup_sub(parm); 3731 3732 if (xfer->flags_int.isochronous_xfr) { 3733 ntd = ((1 * xfer->nframes) 3734 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3735 } else if (xfer->flags_int.control_xfr) { 3736 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3737 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3738 } else { 3739 ntd = ((2 * xfer->nframes) 3740 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3741 } 3742 3743alloc_dma_set: 3744 3745 if (parm->err) 3746 return; 3747 3748 /* 3749 * Allocate queue heads and transfer descriptors 3750 */ 3751 last_obj = NULL; 3752 3753 if (usbd_transfer_setup_sub_malloc( 3754 parm, &pc, sizeof(struct xhci_td), 3755 XHCI_TD_ALIGN, ntd)) { 3756 parm->err = USB_ERR_NOMEM; 3757 return; 3758 } 3759 if (parm->buf) { 3760 for (n = 0; n != ntd; n++) { 3761 struct xhci_td *td; 3762 3763 usbd_get_page(pc + n, 0, &page_info); 3764 3765 td = page_info.buffer; 3766 3767 /* init TD */ 3768 td->td_self = page_info.physaddr; 3769 td->obj_next = last_obj; 3770 td->page_cache = pc + n; 3771 3772 last_obj = td; 3773 3774 usb_pc_cpu_flush(pc + n); 3775 } 3776 } 3777 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3778 3779 if (!xfer->flags_int.curr_dma_set) { 3780 xfer->flags_int.curr_dma_set = 1; 3781 goto alloc_dma_set; 3782 } 3783} 3784 3785static usb_error_t 3786xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3787{ 3788 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3789 struct usb_page_search buf_inp; 3790 struct usb_device *udev; 3791 struct xhci_endpoint_ext *pepext; 3792 struct usb_endpoint_descriptor *edesc; 3793 struct usb_page_cache *pcinp; 3794 usb_error_t err; 3795 usb_stream_t stream_id; 3796 uint8_t index; 3797 uint8_t epno; 3798 3799 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3800 xfer->endpoint->edesc); 3801 3802 udev = xfer->xroot->udev; 3803 index = udev->controller_slot_id; 3804 3805 pcinp = &sc->sc_hw.devs[index].input_pc; 3806 3807 usbd_get_page(pcinp, 0, &buf_inp); 3808 3809 edesc = xfer->endpoint->edesc; 3810 3811 epno = edesc->bEndpointAddress; 3812 stream_id = xfer->stream_id; 3813 3814 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3815 epno |= UE_DIR_IN; 3816 3817 epno = XHCI_EPNO2EPID(epno); 3818 3819 if (epno == 0) 3820 return (USB_ERR_NO_PIPE); /* invalid */ 3821 3822 XHCI_CMD_LOCK(sc); 3823 3824 /* configure endpoint */ 3825 3826 err = xhci_configure_endpoint_by_xfer(xfer); 3827 3828 if (err != 0) { 3829 XHCI_CMD_UNLOCK(sc); 3830 return (err); 3831 } 3832 3833 /* 3834 * Get the endpoint into the stopped state according to the 3835 * endpoint context state diagram in the XHCI specification: 3836 */ 3837 3838 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3839 3840 if (err != 0) 3841 DPRINTF("Could not stop endpoint %u\n", epno); 3842 3843 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3844 3845 if (err != 0) 3846 DPRINTF("Could not reset endpoint %u\n", epno); 3847 3848 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3849 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3850 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3851 stream_id, epno, index); 3852 3853 if (err != 0) 3854 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3855 3856 /* 3857 * Get the endpoint into the running state according to the 3858 * endpoint context state diagram in the XHCI specification: 3859 */ 3860 3861 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3862 3863 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3864 3865 if (err != 0) 3866 DPRINTF("Could not configure endpoint %u\n", epno); 3867 3868 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3869 3870 if (err != 0) 3871 DPRINTF("Could not configure endpoint %u\n", epno); 3872 3873 XHCI_CMD_UNLOCK(sc); 3874 3875 return (0); 3876} 3877 3878static void 3879xhci_xfer_unsetup(struct usb_xfer *xfer) 3880{ 3881 return; 3882} 3883 3884static void 3885xhci_start_dma_delay(struct usb_xfer *xfer) 3886{ 3887 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3888 3889 /* put transfer on interrupt queue (again) */ 3890 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3891 3892 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3893 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3894} 3895 3896static void 3897xhci_configure_msg(struct usb_proc_msg *pm) 3898{ 3899 struct xhci_softc *sc; 3900 struct xhci_endpoint_ext *pepext; 3901 struct usb_xfer *xfer; 3902 3903 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3904 3905restart: 3906 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3907 3908 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3909 xfer->endpoint->edesc); 3910 3911 if ((pepext->trb_halted != 0) || 3912 (pepext->trb_running == 0)) { 3913 3914 uint16_t i; 3915 3916 /* clear halted and running */ 3917 pepext->trb_halted = 0; 3918 pepext->trb_running = 0; 3919 3920 /* nuke remaining buffered transfers */ 3921 3922 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3923 XHCI_MAX_STREAMS); i++) { 3924 /* 3925 * NOTE: We need to use the timeout 3926 * error code here else existing 3927 * isochronous clients can get 3928 * confused: 3929 */ 3930 if (pepext->xfer[i] != NULL) { 3931 xhci_device_done(pepext->xfer[i], 3932 USB_ERR_TIMEOUT); 3933 } 3934 } 3935 3936 /* 3937 * NOTE: The USB transfer cannot vanish in 3938 * this state! 3939 */ 3940 3941 USB_BUS_UNLOCK(&sc->sc_bus); 3942 3943 xhci_configure_reset_endpoint(xfer); 3944 3945 USB_BUS_LOCK(&sc->sc_bus); 3946 3947 /* check if halted is still cleared */ 3948 if (pepext->trb_halted == 0) { 3949 pepext->trb_running = 1; 3950 memset(pepext->trb_index, 0, 3951 sizeof(pepext->trb_index)); 3952 } 3953 goto restart; 3954 } 3955 3956 if (xfer->flags_int.did_dma_delay) { 3957 3958 /* remove transfer from interrupt queue (again) */ 3959 usbd_transfer_dequeue(xfer); 3960 3961 /* we are finally done */ 3962 usb_dma_delay_done_cb(xfer); 3963 3964 /* queue changed - restart */ 3965 goto restart; 3966 } 3967 } 3968 3969 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3970 3971 /* try to insert xfer on HW queue */ 3972 xhci_transfer_insert(xfer); 3973 3974 /* try to multi buffer */ 3975 xhci_device_generic_multi_enter(xfer->endpoint, 3976 xfer->stream_id, NULL); 3977 } 3978} 3979 3980static void 3981xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3982 struct usb_endpoint *ep) 3983{ 3984 struct xhci_endpoint_ext *pepext; 3985 3986 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3987 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3988 3989 if (udev->parent_hub == NULL) { 3990 /* root HUB has special endpoint handling */ 3991 return; 3992 } 3993 3994 ep->methods = &xhci_device_generic_methods; 3995 3996 pepext = xhci_get_endpoint_ext(udev, edesc); 3997 3998 USB_BUS_LOCK(udev->bus); 3999 pepext->trb_halted = 1; 4000 pepext->trb_running = 0; 4001 USB_BUS_UNLOCK(udev->bus); 4002} 4003 4004static void 4005xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4006{ 4007 4008} 4009 4010static void 4011xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4012{ 4013 struct xhci_endpoint_ext *pepext; 4014 4015 DPRINTF("\n"); 4016 4017 if (udev->flags.usb_mode != USB_MODE_HOST) { 4018 /* not supported */ 4019 return; 4020 } 4021 if (udev->parent_hub == NULL) { 4022 /* root HUB has special endpoint handling */ 4023 return; 4024 } 4025 4026 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4027 4028 USB_BUS_LOCK(udev->bus); 4029 pepext->trb_halted = 1; 4030 pepext->trb_running = 0; 4031 USB_BUS_UNLOCK(udev->bus); 4032} 4033 4034static usb_error_t 4035xhci_device_init(struct usb_device *udev) 4036{ 4037 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4038 usb_error_t err; 4039 uint8_t temp; 4040 4041 /* no init for root HUB */ 4042 if (udev->parent_hub == NULL) 4043 return (0); 4044 4045 XHCI_CMD_LOCK(sc); 4046 4047 /* set invalid default */ 4048 4049 udev->controller_slot_id = sc->sc_noslot + 1; 4050 4051 /* try to get a new slot ID from the XHCI */ 4052 4053 err = xhci_cmd_enable_slot(sc, &temp); 4054 4055 if (err) { 4056 XHCI_CMD_UNLOCK(sc); 4057 return (err); 4058 } 4059 4060 if (temp > sc->sc_noslot) { 4061 XHCI_CMD_UNLOCK(sc); 4062 return (USB_ERR_BAD_ADDRESS); 4063 } 4064 4065 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4066 DPRINTF("slot %u already allocated.\n", temp); 4067 XHCI_CMD_UNLOCK(sc); 4068 return (USB_ERR_BAD_ADDRESS); 4069 } 4070 4071 /* store slot ID for later reference */ 4072 4073 udev->controller_slot_id = temp; 4074 4075 /* reset data structure */ 4076 4077 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4078 4079 /* set mark slot allocated */ 4080 4081 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4082 4083 err = xhci_alloc_device_ext(udev); 4084 4085 XHCI_CMD_UNLOCK(sc); 4086 4087 /* get device into default state */ 4088 4089 if (err == 0) 4090 err = xhci_set_address(udev, NULL, 0); 4091 4092 return (err); 4093} 4094 4095static void 4096xhci_device_uninit(struct usb_device *udev) 4097{ 4098 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4099 uint8_t index; 4100 4101 /* no init for root HUB */ 4102 if (udev->parent_hub == NULL) 4103 return; 4104 4105 XHCI_CMD_LOCK(sc); 4106 4107 index = udev->controller_slot_id; 4108 4109 if (index <= sc->sc_noslot) { 4110 xhci_cmd_disable_slot(sc, index); 4111 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4112 4113 /* free device extension */ 4114 xhci_free_device_ext(udev); 4115 } 4116 4117 XHCI_CMD_UNLOCK(sc); 4118} 4119 4120static void 4121xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4122{ 4123 /* 4124 * Wait until the hardware has finished any possible use of 4125 * the transfer descriptor(s) 4126 */ 4127 *pus = 2048; /* microseconds */ 4128} 4129 4130static void 4131xhci_device_resume(struct usb_device *udev) 4132{ 4133 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4134 uint8_t index; 4135 uint8_t n; 4136 uint8_t p; 4137 4138 DPRINTF("\n"); 4139 4140 /* check for root HUB */ 4141 if (udev->parent_hub == NULL) 4142 return; 4143 4144 index = udev->controller_slot_id; 4145 4146 XHCI_CMD_LOCK(sc); 4147 4148 /* blindly resume all endpoints */ 4149 4150 USB_BUS_LOCK(udev->bus); 4151 4152 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4153 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4154 XWRITE4(sc, door, XHCI_DOORBELL(index), 4155 n | XHCI_DB_SID_SET(p)); 4156 } 4157 } 4158 4159 USB_BUS_UNLOCK(udev->bus); 4160 4161 XHCI_CMD_UNLOCK(sc); 4162} 4163 4164static void 4165xhci_device_suspend(struct usb_device *udev) 4166{ 4167 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4168 uint8_t index; 4169 uint8_t n; 4170 usb_error_t err; 4171 4172 DPRINTF("\n"); 4173 4174 /* check for root HUB */ 4175 if (udev->parent_hub == NULL) 4176 return; 4177 4178 index = udev->controller_slot_id; 4179 4180 XHCI_CMD_LOCK(sc); 4181 4182 /* blindly suspend all endpoints */ 4183 4184 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4185 err = xhci_cmd_stop_ep(sc, 1, n, index); 4186 if (err != 0) { 4187 DPRINTF("Failed to suspend endpoint " 4188 "%u on slot %u (ignored).\n", n, index); 4189 } 4190 } 4191 4192 XHCI_CMD_UNLOCK(sc); 4193} 4194 4195static void 4196xhci_set_hw_power(struct usb_bus *bus) 4197{ 4198 DPRINTF("\n"); 4199} 4200 4201static void 4202xhci_device_state_change(struct usb_device *udev) 4203{ 4204 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4205 struct usb_page_search buf_inp; 4206 usb_error_t err; 4207 uint8_t index; 4208 4209 /* check for root HUB */ 4210 if (udev->parent_hub == NULL) 4211 return; 4212 4213 index = udev->controller_slot_id; 4214 4215 DPRINTF("\n"); 4216 4217 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4218 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4219 &sc->sc_hw.devs[index].tt); 4220 if (err != 0) 4221 sc->sc_hw.devs[index].nports = 0; 4222 } 4223 4224 XHCI_CMD_LOCK(sc); 4225 4226 switch (usb_get_device_state(udev)) { 4227 case USB_STATE_POWERED: 4228 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4229 break; 4230 4231 /* set default state */ 4232 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4233 4234 /* reset number of contexts */ 4235 sc->sc_hw.devs[index].context_num = 0; 4236 4237 err = xhci_cmd_reset_dev(sc, index); 4238 4239 if (err != 0) { 4240 DPRINTF("Device reset failed " 4241 "for slot %u.\n", index); 4242 } 4243 break; 4244 4245 case USB_STATE_ADDRESSED: 4246 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4247 break; 4248 4249 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4250 4251 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4252 4253 if (err) { 4254 DPRINTF("Failed to deconfigure " 4255 "slot %u.\n", index); 4256 } 4257 break; 4258 4259 case USB_STATE_CONFIGURED: 4260 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4261 break; 4262 4263 /* set configured state */ 4264 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4265 4266 /* reset number of contexts */ 4267 sc->sc_hw.devs[index].context_num = 0; 4268 4269 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4270 4271 xhci_configure_mask(udev, 3, 0); 4272 4273 err = xhci_configure_device(udev); 4274 if (err != 0) { 4275 DPRINTF("Could not configure device " 4276 "at slot %u.\n", index); 4277 } 4278 4279 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4280 if (err != 0) { 4281 DPRINTF("Could not evaluate device " 4282 "context at slot %u.\n", index); 4283 } 4284 break; 4285 4286 default: 4287 break; 4288 } 4289 XHCI_CMD_UNLOCK(sc); 4290} 4291 4292static usb_error_t 4293xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4294 uint8_t ep_mode) 4295{ 4296 switch (ep_mode) { 4297 case USB_EP_MODE_DEFAULT: 4298 return (0); 4299 case USB_EP_MODE_STREAMS: 4300 if (xhcistreams == 0 || 4301 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4302 udev->speed != USB_SPEED_SUPER) 4303 return (USB_ERR_INVAL); 4304 return (0); 4305 default: 4306 return (USB_ERR_INVAL); 4307 } 4308} 4309 4310struct usb_bus_methods xhci_bus_methods = { 4311 .endpoint_init = xhci_ep_init, 4312 .endpoint_uninit = xhci_ep_uninit, 4313 .xfer_setup = xhci_xfer_setup, 4314 .xfer_unsetup = xhci_xfer_unsetup, 4315 .get_dma_delay = xhci_get_dma_delay, 4316 .device_init = xhci_device_init, 4317 .device_uninit = xhci_device_uninit, 4318 .device_resume = xhci_device_resume, 4319 .device_suspend = xhci_device_suspend, 4320 .set_hw_power = xhci_set_hw_power, 4321 .roothub_exec = xhci_roothub_exec, 4322 .xfer_poll = xhci_do_poll, 4323 .start_dma_delay = xhci_start_dma_delay, 4324 .set_address = xhci_set_address, 4325 .clear_stall = xhci_ep_clear_stall, 4326 .device_state_change = xhci_device_state_change, 4327 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4328 .set_endpoint_mode = xhci_set_endpoint_mode, 4329}; 4330