1/*-
2 * Copyright (c) 2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: releng/10.3/sys/dev/uart/uart_dev_pl011.c 283327 2015-05-23 20:54:25Z ian $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/bus.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_cpu_fdt.h>
39#include <dev/uart/uart_bus.h>
40#include "uart_if.h"
41
42#include <sys/kdb.h>
43
44/* PL011 UART registers and masks*/
45#define	UART_DR		0x00		/* Data register */
46#define	DR_FE		(1 << 8)	/* Framing error */
47#define	DR_PE		(1 << 9)	/* Parity error */
48#define	DR_BE		(1 << 10)	/* Break error */
49#define	DR_OE		(1 << 11)	/* Overrun error */
50
51#define	UART_FR		0x06		/* Flag register */
52#define	FR_TXFF		(1 << 5)	/* Transmit FIFO/reg full */
53#define	FR_RXFF		(1 << 6)	/* Receive FIFO/reg full */
54#define	FR_TXFE		(1 << 7)	/* Transmit FIFO/reg empty */
55
56#define	UART_IBRD	0x09		/* Integer baud rate register */
57#define	IBRD_BDIVINT	0xffff	/* Significant part of int. divisor value */
58
59#define	UART_FBRD	0x0a		/* Fractional baud rate register */
60#define	FBRD_BDIVFRAC	0x3f	/* Significant part of frac. divisor value */
61
62#define	UART_LCR_H	0x0b		/* Line control register */
63#define	LCR_H_WLEN8	(0x3 << 5)
64#define	LCR_H_WLEN7	(0x2 << 5)
65#define	LCR_H_WLEN6	(0x1 << 5)
66#define	LCR_H_FEN	(1 << 4)	/* FIFO mode enable */
67#define	LCR_H_STP2	(1 << 3)	/* 2 stop frames at the end */
68#define	LCR_H_EPS	(1 << 2)	/* Even parity select */
69#define	LCR_H_PEN	(1 << 1)	/* Parity enable */
70
71#define	UART_CR		0x0c		/* Control register */
72#define	CR_RXE		(1 << 9)	/* Receive enable */
73#define	CR_TXE		(1 << 8)	/* Transmit enable */
74#define	CR_UARTEN	(1 << 0)	/* UART enable */
75
76#define	UART_IMSC	0x0e		/* Interrupt mask set/clear register */
77#define	IMSC_MASK_ALL	0x7ff		/* Mask all interrupts */
78
79#define	UART_RIS	0x0f		/* Raw interrupt status register */
80#define	UART_RXREADY	(1 << 4)	/* RX buffer full */
81#define	UART_TXEMPTY	(1 << 5)	/* TX buffer empty */
82#define	RIS_RTIM	(1 << 6)	/* Receive timeout */
83#define	RIS_FE		(1 << 7)	/* Framing error interrupt status */
84#define	RIS_PE		(1 << 8)	/* Parity error interrupt status */
85#define	RIS_BE		(1 << 9)	/* Break error interrupt status */
86#define	RIS_OE		(1 << 10)	/* Overrun interrupt status */
87
88#define	UART_MIS	0x10		/* Masked interrupt status register */
89#define	UART_ICR	0x11		/* Interrupt clear register */
90
91/*
92 * FIXME: actual register size is SoC-dependent, we need to handle it
93 */
94#define	__uart_getreg(bas, reg)		\
95	bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
96#define	__uart_setreg(bas, reg, value)	\
97	bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
98
99/*
100 * Low-level UART interface.
101 */
102static int uart_pl011_probe(struct uart_bas *bas);
103static void uart_pl011_init(struct uart_bas *bas, int, int, int, int);
104static void uart_pl011_term(struct uart_bas *bas);
105static void uart_pl011_putc(struct uart_bas *bas, int);
106static int uart_pl011_rxready(struct uart_bas *bas);
107static int uart_pl011_getc(struct uart_bas *bas, struct mtx *);
108
109static struct uart_ops uart_pl011_ops = {
110	.probe = uart_pl011_probe,
111	.init = uart_pl011_init,
112	.term = uart_pl011_term,
113	.putc = uart_pl011_putc,
114	.rxready = uart_pl011_rxready,
115	.getc = uart_pl011_getc,
116};
117
118static int
119uart_pl011_probe(struct uart_bas *bas)
120{
121
122	return (0);
123}
124
125static void
126uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
127    int parity)
128{
129	uint32_t ctrl, line;
130	uint32_t baud;
131
132	/*
133	 * Zero all settings to make sure
134	 * UART is disabled and not configured
135	 */
136	ctrl = line = 0x0;
137	__uart_setreg(bas, UART_CR, ctrl);
138
139	/* As we know UART is disabled we may setup the line */
140	switch (databits) {
141	case 7:
142		line |= LCR_H_WLEN7;
143		break;
144	case 6:
145		line |= LCR_H_WLEN6;
146		break;
147	case 8:
148	default:
149		line |= LCR_H_WLEN8;
150		break;
151	}
152
153	if (stopbits == 2)
154		line |= LCR_H_STP2;
155	else
156		line &= ~LCR_H_STP2;
157
158	if (parity)
159		line |= LCR_H_PEN;
160	else
161		line &= ~LCR_H_PEN;
162
163	/* Configure the rest */
164	line &=  ~LCR_H_FEN;
165	ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
166
167	if (bas->rclk != 0 && baudrate != 0) {
168		baud = bas->rclk * 4 / baudrate;
169		__uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT);
170		__uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC);
171	}
172
173	/* Add config. to line before reenabling UART */
174	__uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) &
175	    ~0xff) | line);
176
177	__uart_setreg(bas, UART_CR, ctrl);
178}
179
180static void
181uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
182    int parity)
183{
184	/* Mask all interrupts */
185	__uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) &
186	    ~IMSC_MASK_ALL);
187
188	uart_pl011_param(bas, baudrate, databits, stopbits, parity);
189}
190
191static void
192uart_pl011_term(struct uart_bas *bas)
193{
194}
195
196static void
197uart_pl011_putc(struct uart_bas *bas, int c)
198{
199
200	/* Wait when TX FIFO full. Push character otherwise. */
201	while (__uart_getreg(bas, UART_FR) & FR_TXFF)
202		;
203	__uart_setreg(bas, UART_DR, c & 0xff);
204}
205
206static int
207uart_pl011_rxready(struct uart_bas *bas)
208{
209
210	return (__uart_getreg(bas, UART_FR) & FR_RXFF);
211}
212
213static int
214uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx)
215{
216	int c;
217
218	while (!uart_pl011_rxready(bas))
219		;
220	c = __uart_getreg(bas, UART_DR) & 0xff;
221
222	return (c);
223}
224
225/*
226 * High-level UART interface.
227 */
228struct uart_pl011_softc {
229	struct uart_softc base;
230	uint8_t		fcr;
231	uint8_t		ier;
232	uint8_t		mcr;
233
234	uint8_t		ier_mask;
235	uint8_t		ier_rxbits;
236};
237
238static int uart_pl011_bus_attach(struct uart_softc *);
239static int uart_pl011_bus_detach(struct uart_softc *);
240static int uart_pl011_bus_flush(struct uart_softc *, int);
241static int uart_pl011_bus_getsig(struct uart_softc *);
242static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t);
243static int uart_pl011_bus_ipend(struct uart_softc *);
244static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int);
245static int uart_pl011_bus_probe(struct uart_softc *);
246static int uart_pl011_bus_receive(struct uart_softc *);
247static int uart_pl011_bus_setsig(struct uart_softc *, int);
248static int uart_pl011_bus_transmit(struct uart_softc *);
249static void uart_pl011_bus_grab(struct uart_softc *);
250static void uart_pl011_bus_ungrab(struct uart_softc *);
251
252static kobj_method_t uart_pl011_methods[] = {
253	KOBJMETHOD(uart_attach,		uart_pl011_bus_attach),
254	KOBJMETHOD(uart_detach,		uart_pl011_bus_detach),
255	KOBJMETHOD(uart_flush,		uart_pl011_bus_flush),
256	KOBJMETHOD(uart_getsig,		uart_pl011_bus_getsig),
257	KOBJMETHOD(uart_ioctl,		uart_pl011_bus_ioctl),
258	KOBJMETHOD(uart_ipend,		uart_pl011_bus_ipend),
259	KOBJMETHOD(uart_param,		uart_pl011_bus_param),
260	KOBJMETHOD(uart_probe,		uart_pl011_bus_probe),
261	KOBJMETHOD(uart_receive,	uart_pl011_bus_receive),
262	KOBJMETHOD(uart_setsig,		uart_pl011_bus_setsig),
263	KOBJMETHOD(uart_transmit,	uart_pl011_bus_transmit),
264	KOBJMETHOD(uart_grab,		uart_pl011_bus_grab),
265	KOBJMETHOD(uart_ungrab,		uart_pl011_bus_ungrab),
266
267	{ 0, 0 }
268};
269
270static struct uart_class uart_pl011_class = {
271	"uart_pl011",
272	uart_pl011_methods,
273	sizeof(struct uart_pl011_softc),
274	.uc_ops = &uart_pl011_ops,
275	.uc_range = 0x48,
276	.uc_rclk = 0
277};
278
279static struct ofw_compat_data compat_data[] = {
280	{"arm,pl011",		(uintptr_t)&uart_pl011_class},
281	{NULL,			(uintptr_t)NULL},
282};
283UART_FDT_CLASS_AND_DEVICE(compat_data);
284
285static int
286uart_pl011_bus_attach(struct uart_softc *sc)
287{
288	struct uart_bas *bas;
289	int reg;
290
291	bas = &sc->sc_bas;
292
293	/* Enable interrupts */
294	reg = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY);
295	__uart_setreg(bas, UART_IMSC, reg);
296
297	/* Clear interrupts */
298	__uart_setreg(bas, UART_ICR, IMSC_MASK_ALL);
299
300	return (0);
301}
302
303static int
304uart_pl011_bus_detach(struct uart_softc *sc)
305{
306
307	return (0);
308}
309
310static int
311uart_pl011_bus_flush(struct uart_softc *sc, int what)
312{
313
314	return (0);
315}
316
317static int
318uart_pl011_bus_getsig(struct uart_softc *sc)
319{
320
321	return (0);
322}
323
324static int
325uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
326{
327	struct uart_bas *bas;
328	int error;
329
330	bas = &sc->sc_bas;
331	error = 0;
332	uart_lock(sc->sc_hwmtx);
333	switch (request) {
334	case UART_IOCTL_BREAK:
335		break;
336	case UART_IOCTL_BAUD:
337		*(int*)data = 115200;
338		break;
339	default:
340		error = EINVAL;
341		break;
342	}
343	uart_unlock(sc->sc_hwmtx);
344
345	return (error);
346}
347
348static int
349uart_pl011_bus_ipend(struct uart_softc *sc)
350{
351	struct uart_bas *bas;
352	uint32_t ints;
353	int ipend;
354	int reg;
355
356	bas = &sc->sc_bas;
357	uart_lock(sc->sc_hwmtx);
358	ints = __uart_getreg(bas, UART_MIS);
359	ipend = 0;
360
361	if (ints & (UART_RXREADY | RIS_RTIM))
362		ipend |= SER_INT_RXREADY;
363	if (ints & RIS_BE)
364		ipend |= SER_INT_BREAK;
365	if (ints & RIS_OE)
366		ipend |= SER_INT_OVERRUN;
367	if (ints & UART_TXEMPTY) {
368		if (sc->sc_txbusy)
369			ipend |= SER_INT_TXIDLE;
370
371		/* Disable TX interrupt */
372		reg = __uart_getreg(bas, UART_IMSC);
373		reg &= ~(UART_TXEMPTY);
374		__uart_setreg(bas, UART_IMSC, reg);
375	}
376
377	uart_unlock(sc->sc_hwmtx);
378
379	return (ipend);
380}
381
382static int
383uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits,
384    int stopbits, int parity)
385{
386
387	uart_lock(sc->sc_hwmtx);
388	uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
389	uart_unlock(sc->sc_hwmtx);
390
391	return (0);
392}
393
394static int
395uart_pl011_bus_probe(struct uart_softc *sc)
396{
397
398	device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
399
400	sc->sc_rxfifosz = 1;
401	sc->sc_txfifosz = 1;
402
403	return (0);
404}
405
406static int
407uart_pl011_bus_receive(struct uart_softc *sc)
408{
409	struct uart_bas *bas;
410	uint32_t ints, xc;
411	int rx;
412
413	bas = &sc->sc_bas;
414	uart_lock(sc->sc_hwmtx);
415
416	ints = __uart_getreg(bas, UART_MIS);
417	while (ints & (UART_RXREADY | RIS_RTIM)) {
418		if (uart_rx_full(sc)) {
419			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
420			break;
421		}
422		xc = __uart_getreg(bas, UART_DR);
423		rx = xc & 0xff;
424
425		if (xc & DR_FE)
426			rx |= UART_STAT_FRAMERR;
427		if (xc & DR_PE)
428			rx |= UART_STAT_PARERR;
429
430		__uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM));
431
432		uart_rx_put(sc, rx);
433		ints = __uart_getreg(bas, UART_MIS);
434	}
435
436	uart_unlock(sc->sc_hwmtx);
437
438	return (0);
439}
440
441static int
442uart_pl011_bus_setsig(struct uart_softc *sc, int sig)
443{
444
445	return (0);
446}
447
448static int
449uart_pl011_bus_transmit(struct uart_softc *sc)
450{
451	struct uart_bas *bas;
452	int reg;
453	int i;
454
455	bas = &sc->sc_bas;
456	uart_lock(sc->sc_hwmtx);
457
458	for (i = 0; i < sc->sc_txdatasz; i++) {
459		__uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
460		uart_barrier(bas);
461	}
462	sc->sc_txbusy = 1;
463
464	/* Enable TX interrupt */
465	reg = __uart_getreg(bas, UART_IMSC);
466	reg |= (UART_TXEMPTY);
467	__uart_setreg(bas, UART_IMSC, reg);
468
469	uart_unlock(sc->sc_hwmtx);
470
471	return (0);
472}
473
474static void
475uart_pl011_bus_grab(struct uart_softc *sc)
476{
477	struct uart_bas *bas;
478
479	bas = &sc->sc_bas;
480	uart_lock(sc->sc_hwmtx);
481	__uart_setreg(bas, UART_IMSC, 	/* Switch to RX polling while grabbed */
482	    ~UART_RXREADY & __uart_getreg(bas, UART_IMSC));
483	uart_unlock(sc->sc_hwmtx);
484}
485
486static void
487uart_pl011_bus_ungrab(struct uart_softc *sc)
488{
489	struct uart_bas *bas;
490
491	bas = &sc->sc_bas;
492	uart_lock(sc->sc_hwmtx);
493	__uart_setreg(bas, UART_IMSC,	/* Switch to RX interrupts while not grabbed */
494	    UART_RXREADY | __uart_getreg(bas, UART_IMSC));
495	uart_unlock(sc->sc_hwmtx);
496}
497