uart_dev_ns8250.c revision 266046
1139749Simp/*- 2119815Smarcel * Copyright (c) 2003 Marcel Moolenaar 3119815Smarcel * All rights reserved. 4119815Smarcel * 5119815Smarcel * Redistribution and use in source and binary forms, with or without 6119815Smarcel * modification, are permitted provided that the following conditions 7119815Smarcel * are met: 8119815Smarcel * 9119815Smarcel * 1. Redistributions of source code must retain the above copyright 10119815Smarcel * notice, this list of conditions and the following disclaimer. 11119815Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12119815Smarcel * notice, this list of conditions and the following disclaimer in the 13119815Smarcel * documentation and/or other materials provided with the distribution. 14119815Smarcel * 15119815Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16119815Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17119815Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18119815Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19119815Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20119815Smarcel * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21119815Smarcel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22119815Smarcel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23119815Smarcel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24119815Smarcel * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25119815Smarcel */ 26119815Smarcel 27247519Sganbold#include "opt_platform.h" 28247519Sganbold 29119815Smarcel#include <sys/cdefs.h> 30119815Smarcel__FBSDID("$FreeBSD: stable/10/sys/dev/uart/uart_dev_ns8250.c 266046 2014-05-14 16:32:27Z ian $"); 31119815Smarcel 32119815Smarcel#include <sys/param.h> 33119815Smarcel#include <sys/systm.h> 34119815Smarcel#include <sys/bus.h> 35119815Smarcel#include <sys/conf.h> 36246016Scperciva#include <sys/kernel.h> 37246016Scperciva#include <sys/sysctl.h> 38119815Smarcel#include <machine/bus.h> 39119815Smarcel 40247519Sganbold#ifdef FDT 41247519Sganbold#include <dev/fdt/fdt_common.h> 42247519Sganbold#include <dev/ofw/ofw_bus.h> 43247519Sganbold#include <dev/ofw/ofw_bus_subr.h> 44247519Sganbold#endif 45247519Sganbold 46119815Smarcel#include <dev/uart/uart.h> 47119815Smarcel#include <dev/uart/uart_cpu.h> 48119815Smarcel#include <dev/uart/uart_bus.h> 49254597Sian#include <dev/uart/uart_dev_ns8250.h> 50119815Smarcel 51137949Smarcel#include <dev/ic/ns16550.h> 52137949Smarcel 53119815Smarcel#include "uart_if.h" 54119815Smarcel 55119815Smarcel#define DEFAULT_RCLK 1843200 56119815Smarcel 57247519Sganboldstatic int broken_txfifo = 0; 58247519SganboldSYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, 59247519Sganbold &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 60247519SganboldTUNABLE_INT("hw.broken_txfifo", &broken_txfifo); 61247519Sganbold 62119815Smarcel/* 63119815Smarcel * Clear pending interrupts. THRE is cleared by reading IIR. Data 64119815Smarcel * that may have been received gets lost here. 65119815Smarcel */ 66119815Smarcelstatic void 67119815Smarcelns8250_clrint(struct uart_bas *bas) 68119815Smarcel{ 69190834Smarcel uint8_t iir, lsr; 70119815Smarcel 71119815Smarcel iir = uart_getreg(bas, REG_IIR); 72119815Smarcel while ((iir & IIR_NOPEND) == 0) { 73119815Smarcel iir &= IIR_IMASK; 74190834Smarcel if (iir == IIR_RLS) { 75190834Smarcel lsr = uart_getreg(bas, REG_LSR); 76190834Smarcel if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 77190834Smarcel (void)uart_getreg(bas, REG_DATA); 78190834Smarcel } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 79119815Smarcel (void)uart_getreg(bas, REG_DATA); 80119815Smarcel else if (iir == IIR_MLSC) 81119815Smarcel (void)uart_getreg(bas, REG_MSR); 82119815Smarcel uart_barrier(bas); 83119815Smarcel iir = uart_getreg(bas, REG_IIR); 84119815Smarcel } 85119815Smarcel} 86119815Smarcel 87119815Smarcelstatic int 88119815Smarcelns8250_delay(struct uart_bas *bas) 89119815Smarcel{ 90119815Smarcel int divisor; 91119815Smarcel u_char lcr; 92119815Smarcel 93119815Smarcel lcr = uart_getreg(bas, REG_LCR); 94119815Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 95119815Smarcel uart_barrier(bas); 96158844Sbenno divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 97119815Smarcel uart_barrier(bas); 98119815Smarcel uart_setreg(bas, REG_LCR, lcr); 99119815Smarcel uart_barrier(bas); 100119815Smarcel 101119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 102168000Smarcel if (divisor <= 134) 103168000Smarcel return (16000000 * divisor / bas->rclk); 104168000Smarcel return (16000 * divisor / (bas->rclk / 1000)); 105119815Smarcel} 106119815Smarcel 107119815Smarcelstatic int 108119815Smarcelns8250_divisor(int rclk, int baudrate) 109119815Smarcel{ 110119815Smarcel int actual_baud, divisor; 111119815Smarcel int error; 112119815Smarcel 113119815Smarcel if (baudrate == 0) 114119815Smarcel return (0); 115119815Smarcel 116119815Smarcel divisor = (rclk / (baudrate << 3) + 1) >> 1; 117119815Smarcel if (divisor == 0 || divisor >= 65536) 118119815Smarcel return (0); 119119815Smarcel actual_baud = rclk / (divisor << 4); 120119815Smarcel 121119815Smarcel /* 10 times error in percent: */ 122119815Smarcel error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 123119815Smarcel 124119815Smarcel /* 3.0% maximum error tolerance: */ 125119815Smarcel if (error < -30 || error > 30) 126119815Smarcel return (0); 127119815Smarcel 128119815Smarcel return (divisor); 129119815Smarcel} 130119815Smarcel 131119815Smarcelstatic int 132119815Smarcelns8250_drain(struct uart_bas *bas, int what) 133119815Smarcel{ 134119815Smarcel int delay, limit; 135119815Smarcel 136119815Smarcel delay = ns8250_delay(bas); 137119815Smarcel 138119815Smarcel if (what & UART_DRAIN_TRANSMITTER) { 139119815Smarcel /* 140119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 141119815Smarcel * an infinite loop when the hardware is broken. Make the 142119815Smarcel * limit high enough to handle large FIFOs. 143119815Smarcel */ 144119815Smarcel limit = 10*1024; 145119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 146119815Smarcel DELAY(delay); 147119815Smarcel if (limit == 0) { 148119815Smarcel /* printf("ns8250: transmitter appears stuck... "); */ 149119815Smarcel return (EIO); 150119815Smarcel } 151119815Smarcel } 152119815Smarcel 153119815Smarcel if (what & UART_DRAIN_RECEIVER) { 154119815Smarcel /* 155119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 156119815Smarcel * an infinite loop when the hardware is broken. Make the 157119815Smarcel * limit high enough to handle large FIFOs and integrated 158119815Smarcel * UARTs. The HP rx2600 for example has 3 UARTs on the 159119815Smarcel * management board that tend to get a lot of data send 160119815Smarcel * to it when the UART is first activated. 161119815Smarcel */ 162119815Smarcel limit=10*4096; 163119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 164119815Smarcel (void)uart_getreg(bas, REG_DATA); 165119815Smarcel uart_barrier(bas); 166119815Smarcel DELAY(delay << 2); 167119815Smarcel } 168119815Smarcel if (limit == 0) { 169119815Smarcel /* printf("ns8250: receiver appears broken... "); */ 170119815Smarcel return (EIO); 171119815Smarcel } 172119815Smarcel } 173119815Smarcel 174119815Smarcel return (0); 175119815Smarcel} 176119815Smarcel 177119815Smarcel/* 178119815Smarcel * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 179119815Smarcel * drained. WARNING: this function clobbers the FIFO setting! 180119815Smarcel */ 181119815Smarcelstatic void 182119815Smarcelns8250_flush(struct uart_bas *bas, int what) 183119815Smarcel{ 184119815Smarcel uint8_t fcr; 185119815Smarcel 186119815Smarcel fcr = FCR_ENABLE; 187119815Smarcel if (what & UART_FLUSH_TRANSMITTER) 188119815Smarcel fcr |= FCR_XMT_RST; 189119815Smarcel if (what & UART_FLUSH_RECEIVER) 190119815Smarcel fcr |= FCR_RCV_RST; 191119815Smarcel uart_setreg(bas, REG_FCR, fcr); 192119815Smarcel uart_barrier(bas); 193119815Smarcel} 194119815Smarcel 195119815Smarcelstatic int 196119815Smarcelns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 197119815Smarcel int parity) 198119815Smarcel{ 199119815Smarcel int divisor; 200119815Smarcel uint8_t lcr; 201119815Smarcel 202119815Smarcel lcr = 0; 203119815Smarcel if (databits >= 8) 204119815Smarcel lcr |= LCR_8BITS; 205119815Smarcel else if (databits == 7) 206119815Smarcel lcr |= LCR_7BITS; 207119815Smarcel else if (databits == 6) 208119815Smarcel lcr |= LCR_6BITS; 209119815Smarcel else 210119815Smarcel lcr |= LCR_5BITS; 211119815Smarcel if (stopbits > 1) 212119815Smarcel lcr |= LCR_STOPB; 213119815Smarcel lcr |= parity << 3; 214119815Smarcel 215119815Smarcel /* Set baudrate. */ 216119815Smarcel if (baudrate > 0) { 217119815Smarcel divisor = ns8250_divisor(bas->rclk, baudrate); 218119815Smarcel if (divisor == 0) 219119815Smarcel return (EINVAL); 220157989Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 221157989Smarcel uart_barrier(bas); 222158844Sbenno uart_setreg(bas, REG_DLL, divisor & 0xff); 223158844Sbenno uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 224119815Smarcel uart_barrier(bas); 225119815Smarcel } 226119815Smarcel 227119815Smarcel /* Set LCR and clear DLAB. */ 228119815Smarcel uart_setreg(bas, REG_LCR, lcr); 229119815Smarcel uart_barrier(bas); 230119815Smarcel return (0); 231119815Smarcel} 232119815Smarcel 233119815Smarcel/* 234119815Smarcel * Low-level UART interface. 235119815Smarcel */ 236119815Smarcelstatic int ns8250_probe(struct uart_bas *bas); 237119815Smarcelstatic void ns8250_init(struct uart_bas *bas, int, int, int, int); 238119815Smarcelstatic void ns8250_term(struct uart_bas *bas); 239119815Smarcelstatic void ns8250_putc(struct uart_bas *bas, int); 240166100Smariusstatic int ns8250_rxready(struct uart_bas *bas); 241157380Smarcelstatic int ns8250_getc(struct uart_bas *bas, struct mtx *); 242119815Smarcel 243254597Sianstruct uart_ops uart_ns8250_ops = { 244119815Smarcel .probe = ns8250_probe, 245119815Smarcel .init = ns8250_init, 246119815Smarcel .term = ns8250_term, 247119815Smarcel .putc = ns8250_putc, 248166100Smarius .rxready = ns8250_rxready, 249119815Smarcel .getc = ns8250_getc, 250119815Smarcel}; 251119815Smarcel 252119815Smarcelstatic int 253119815Smarcelns8250_probe(struct uart_bas *bas) 254119815Smarcel{ 255158849Sbenno u_char val; 256119815Smarcel 257119815Smarcel /* Check known 0 bits that don't depend on DLAB. */ 258119815Smarcel val = uart_getreg(bas, REG_IIR); 259119815Smarcel if (val & 0x30) 260119815Smarcel return (ENXIO); 261222317Smarcel /* 262222317Smarcel * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 263222317Smarcel * chip, but otherwise doesn't seem to have a function. In 264222317Smarcel * other words, uart(4) works regardless. Ignore that bit so 265222317Smarcel * the probe succeeds. 266222317Smarcel */ 267119815Smarcel val = uart_getreg(bas, REG_MCR); 268222317Smarcel if (val & 0xa0) 269119815Smarcel return (ENXIO); 270119815Smarcel 271119815Smarcel return (0); 272119815Smarcel} 273119815Smarcel 274119815Smarcelstatic void 275119815Smarcelns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 276119815Smarcel int parity) 277119815Smarcel{ 278158844Sbenno u_char ier; 279119815Smarcel 280119815Smarcel if (bas->rclk == 0) 281119815Smarcel bas->rclk = DEFAULT_RCLK; 282119815Smarcel ns8250_param(bas, baudrate, databits, stopbits, parity); 283119815Smarcel 284119815Smarcel /* Disable all interrupt sources. */ 285179420Sbenno /* 286179420Sbenno * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 287179420Sbenno * UARTs split the receive time-out interrupt bit out separately as 288179420Sbenno * 0x10. This gets handled by ier_mask and ier_rxbits below. 289179420Sbenno */ 290179420Sbenno ier = uart_getreg(bas, REG_IER) & 0xe0; 291158844Sbenno uart_setreg(bas, REG_IER, ier); 292119815Smarcel uart_barrier(bas); 293119815Smarcel 294119815Smarcel /* Disable the FIFO (if present). */ 295119815Smarcel uart_setreg(bas, REG_FCR, 0); 296119815Smarcel uart_barrier(bas); 297119815Smarcel 298119815Smarcel /* Set RTS & DTR. */ 299119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 300119815Smarcel uart_barrier(bas); 301119815Smarcel 302119815Smarcel ns8250_clrint(bas); 303119815Smarcel} 304119815Smarcel 305119815Smarcelstatic void 306119815Smarcelns8250_term(struct uart_bas *bas) 307119815Smarcel{ 308119815Smarcel 309119815Smarcel /* Clear RTS & DTR. */ 310119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE); 311119815Smarcel uart_barrier(bas); 312119815Smarcel} 313119815Smarcel 314119815Smarcelstatic void 315119815Smarcelns8250_putc(struct uart_bas *bas, int c) 316119815Smarcel{ 317168285Smarcel int limit; 318119815Smarcel 319168285Smarcel limit = 250000; 320119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 321168285Smarcel DELAY(4); 322119815Smarcel uart_setreg(bas, REG_DATA, c); 323127742Smarcel uart_barrier(bas); 324168285Smarcel limit = 250000; 325119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 326168285Smarcel DELAY(4); 327119815Smarcel} 328119815Smarcel 329119815Smarcelstatic int 330166100Smariusns8250_rxready(struct uart_bas *bas) 331119815Smarcel{ 332119815Smarcel 333166100Smarius return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 334119815Smarcel} 335119815Smarcel 336119815Smarcelstatic int 337157380Smarcelns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 338119815Smarcel{ 339168285Smarcel int c; 340119815Smarcel 341157380Smarcel uart_lock(hwmtx); 342157380Smarcel 343157380Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 344157380Smarcel uart_unlock(hwmtx); 345168285Smarcel DELAY(4); 346157380Smarcel uart_lock(hwmtx); 347157380Smarcel } 348157380Smarcel 349157380Smarcel c = uart_getreg(bas, REG_DATA); 350157380Smarcel 351157380Smarcel uart_unlock(hwmtx); 352157380Smarcel 353157380Smarcel return (c); 354119815Smarcel} 355119815Smarcel 356119815Smarcelstatic kobj_method_t ns8250_methods[] = { 357119815Smarcel KOBJMETHOD(uart_attach, ns8250_bus_attach), 358119815Smarcel KOBJMETHOD(uart_detach, ns8250_bus_detach), 359119815Smarcel KOBJMETHOD(uart_flush, ns8250_bus_flush), 360119815Smarcel KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 361119815Smarcel KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 362119815Smarcel KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 363119815Smarcel KOBJMETHOD(uart_param, ns8250_bus_param), 364119815Smarcel KOBJMETHOD(uart_probe, ns8250_bus_probe), 365119815Smarcel KOBJMETHOD(uart_receive, ns8250_bus_receive), 366119815Smarcel KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 367119815Smarcel KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 368262649Simp KOBJMETHOD(uart_grab, ns8250_bus_grab), 369262649Simp KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 370119815Smarcel { 0, 0 } 371119815Smarcel}; 372119815Smarcel 373119815Smarcelstruct uart_class uart_ns8250_class = { 374168281Smarcel "ns8250", 375119815Smarcel ns8250_methods, 376119815Smarcel sizeof(struct ns8250_softc), 377168281Smarcel .uc_ops = &uart_ns8250_ops, 378119815Smarcel .uc_range = 8, 379119815Smarcel .uc_rclk = DEFAULT_RCLK 380119815Smarcel}; 381119815Smarcel 382119815Smarcel#define SIGCHG(c, i, s, d) \ 383119815Smarcel if (c) { \ 384119815Smarcel i |= (i & s) ? s : s | d; \ 385119815Smarcel } else { \ 386119815Smarcel i = (i & s) ? (i & ~s) | d : i; \ 387119815Smarcel } 388119815Smarcel 389254597Sianint 390119815Smarcelns8250_bus_attach(struct uart_softc *sc) 391119815Smarcel{ 392119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 393119815Smarcel struct uart_bas *bas; 394177117Ssam unsigned int ivar; 395247519Sganbold#ifdef FDT 396247519Sganbold phandle_t node; 397247519Sganbold pcell_t cell; 398247519Sganbold#endif 399119815Smarcel 400247519Sganbold ns8250->busy_detect = 0; 401247519Sganbold 402247519Sganbold#ifdef FDT 403247519Sganbold /* 404247519Sganbold * Check whether uart requires to read USR reg when IIR_BUSY and 405247519Sganbold * has broken txfifo. 406247519Sganbold */ 407247519Sganbold node = ofw_bus_get_node(sc->sc_dev); 408247519Sganbold if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 409247519Sganbold ns8250->busy_detect = 1; 410247519Sganbold if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 411247519Sganbold broken_txfifo = 1; 412247519Sganbold#endif 413247519Sganbold 414119815Smarcel bas = &sc->sc_bas; 415119815Smarcel 416119815Smarcel ns8250->mcr = uart_getreg(bas, REG_MCR); 417177117Ssam ns8250->fcr = FCR_ENABLE; 418177117Ssam if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 419177117Ssam &ivar)) { 420177117Ssam if (UART_FLAGS_FCR_RX_LOW(ivar)) 421177117Ssam ns8250->fcr |= FCR_RX_LOW; 422177117Ssam else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 423177117Ssam ns8250->fcr |= FCR_RX_MEDL; 424177117Ssam else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 425177117Ssam ns8250->fcr |= FCR_RX_HIGH; 426177117Ssam else 427177117Ssam ns8250->fcr |= FCR_RX_MEDH; 428177117Ssam } else 429177117Ssam ns8250->fcr |= FCR_RX_MEDH; 430179420Sbenno 431179420Sbenno /* Get IER mask */ 432179420Sbenno ivar = 0xf0; 433179420Sbenno resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 434179420Sbenno &ivar); 435179420Sbenno ns8250->ier_mask = (uint8_t)(ivar & 0xff); 436179420Sbenno 437179420Sbenno /* Get IER RX interrupt bits */ 438179420Sbenno ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 439179420Sbenno resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 440179420Sbenno &ivar); 441179420Sbenno ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 442179420Sbenno 443119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 444119815Smarcel uart_barrier(bas); 445119815Smarcel ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 446119815Smarcel 447119815Smarcel if (ns8250->mcr & MCR_DTR) 448131043Sphk sc->sc_hwsig |= SER_DTR; 449119815Smarcel if (ns8250->mcr & MCR_RTS) 450131043Sphk sc->sc_hwsig |= SER_RTS; 451119815Smarcel ns8250_bus_getsig(sc); 452119815Smarcel 453119815Smarcel ns8250_clrint(bas); 454179420Sbenno ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 455179420Sbenno ns8250->ier |= ns8250->ier_rxbits; 456119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier); 457119815Smarcel uart_barrier(bas); 458255031Smarcel 459255031Smarcel /* 460255031Smarcel * Timing of the H/W access was changed with r253161 of uart_core.c 461255031Smarcel * It has been observed that an ITE IT8513E would signal a break 462255031Smarcel * condition with pretty much every character it received, unless 463255031Smarcel * it had enough time to settle between ns8250_bus_attach() and 464255031Smarcel * ns8250_bus_ipend() -- which it accidentally had before r253161. 465255031Smarcel * It's not understood why the UART chip behaves this way and it 466255031Smarcel * could very well be that the DELAY make the H/W work in the same 467255031Smarcel * accidental manner as before. More analysis is warranted, but 468255031Smarcel * at least now we fixed a known regression. 469255031Smarcel */ 470255074Smarcel DELAY(200); 471119815Smarcel return (0); 472119815Smarcel} 473119815Smarcel 474254597Sianint 475119815Smarcelns8250_bus_detach(struct uart_softc *sc) 476119815Smarcel{ 477179420Sbenno struct ns8250_softc *ns8250; 478119815Smarcel struct uart_bas *bas; 479158844Sbenno u_char ier; 480119815Smarcel 481179420Sbenno ns8250 = (struct ns8250_softc *)sc; 482119815Smarcel bas = &sc->sc_bas; 483179420Sbenno ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 484158844Sbenno uart_setreg(bas, REG_IER, ier); 485119815Smarcel uart_barrier(bas); 486119815Smarcel ns8250_clrint(bas); 487119815Smarcel return (0); 488119815Smarcel} 489119815Smarcel 490254597Sianint 491119815Smarcelns8250_bus_flush(struct uart_softc *sc, int what) 492119815Smarcel{ 493119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 494119815Smarcel struct uart_bas *bas; 495120143Smarcel int error; 496119815Smarcel 497119815Smarcel bas = &sc->sc_bas; 498157300Smarcel uart_lock(sc->sc_hwmtx); 499157418Smarcel if (sc->sc_rxfifosz > 1) { 500119815Smarcel ns8250_flush(bas, what); 501119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 502119815Smarcel uart_barrier(bas); 503120143Smarcel error = 0; 504120143Smarcel } else 505120143Smarcel error = ns8250_drain(bas, what); 506157300Smarcel uart_unlock(sc->sc_hwmtx); 507120143Smarcel return (error); 508119815Smarcel} 509119815Smarcel 510254597Sianint 511119815Smarcelns8250_bus_getsig(struct uart_softc *sc) 512119815Smarcel{ 513119815Smarcel uint32_t new, old, sig; 514119815Smarcel uint8_t msr; 515119815Smarcel 516119815Smarcel do { 517119815Smarcel old = sc->sc_hwsig; 518119815Smarcel sig = old; 519157300Smarcel uart_lock(sc->sc_hwmtx); 520119815Smarcel msr = uart_getreg(&sc->sc_bas, REG_MSR); 521157300Smarcel uart_unlock(sc->sc_hwmtx); 522131043Sphk SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 523131043Sphk SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 524131043Sphk SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 525131043Sphk SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 526155973Smarcel new = sig & ~SER_MASK_DELTA; 527119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 528119815Smarcel return (sig); 529119815Smarcel} 530119815Smarcel 531254597Sianint 532119815Smarcelns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 533119815Smarcel{ 534119815Smarcel struct uart_bas *bas; 535137709Smarcel int baudrate, divisor, error; 536120022Smarcel uint8_t efr, lcr; 537119815Smarcel 538119815Smarcel bas = &sc->sc_bas; 539120143Smarcel error = 0; 540157300Smarcel uart_lock(sc->sc_hwmtx); 541119815Smarcel switch (request) { 542119815Smarcel case UART_IOCTL_BREAK: 543119815Smarcel lcr = uart_getreg(bas, REG_LCR); 544119815Smarcel if (data) 545119815Smarcel lcr |= LCR_SBREAK; 546119815Smarcel else 547119815Smarcel lcr &= ~LCR_SBREAK; 548119815Smarcel uart_setreg(bas, REG_LCR, lcr); 549119815Smarcel uart_barrier(bas); 550119815Smarcel break; 551120022Smarcel case UART_IOCTL_IFLOW: 552120022Smarcel lcr = uart_getreg(bas, REG_LCR); 553120022Smarcel uart_barrier(bas); 554120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 555120022Smarcel uart_barrier(bas); 556120022Smarcel efr = uart_getreg(bas, REG_EFR); 557120022Smarcel if (data) 558120022Smarcel efr |= EFR_RTS; 559120022Smarcel else 560120022Smarcel efr &= ~EFR_RTS; 561120022Smarcel uart_setreg(bas, REG_EFR, efr); 562120022Smarcel uart_barrier(bas); 563120022Smarcel uart_setreg(bas, REG_LCR, lcr); 564120022Smarcel uart_barrier(bas); 565120022Smarcel break; 566120022Smarcel case UART_IOCTL_OFLOW: 567120022Smarcel lcr = uart_getreg(bas, REG_LCR); 568120022Smarcel uart_barrier(bas); 569120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 570120022Smarcel uart_barrier(bas); 571120022Smarcel efr = uart_getreg(bas, REG_EFR); 572120022Smarcel if (data) 573120022Smarcel efr |= EFR_CTS; 574120022Smarcel else 575120022Smarcel efr &= ~EFR_CTS; 576120022Smarcel uart_setreg(bas, REG_EFR, efr); 577120022Smarcel uart_barrier(bas); 578120022Smarcel uart_setreg(bas, REG_LCR, lcr); 579120022Smarcel uart_barrier(bas); 580120022Smarcel break; 581137707Smarcel case UART_IOCTL_BAUD: 582137707Smarcel lcr = uart_getreg(bas, REG_LCR); 583137707Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 584137707Smarcel uart_barrier(bas); 585158844Sbenno divisor = uart_getreg(bas, REG_DLL) | 586158844Sbenno (uart_getreg(bas, REG_DLH) << 8); 587137707Smarcel uart_barrier(bas); 588137707Smarcel uart_setreg(bas, REG_LCR, lcr); 589137707Smarcel uart_barrier(bas); 590137709Smarcel baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 591137709Smarcel if (baudrate > 0) 592137709Smarcel *(int*)data = baudrate; 593137709Smarcel else 594137709Smarcel error = ENXIO; 595137707Smarcel break; 596119815Smarcel default: 597120143Smarcel error = EINVAL; 598120143Smarcel break; 599119815Smarcel } 600157300Smarcel uart_unlock(sc->sc_hwmtx); 601120143Smarcel return (error); 602119815Smarcel} 603119815Smarcel 604254597Sianint 605119815Smarcelns8250_bus_ipend(struct uart_softc *sc) 606119815Smarcel{ 607119815Smarcel struct uart_bas *bas; 608227032Scognet struct ns8250_softc *ns8250; 609119815Smarcel int ipend; 610119815Smarcel uint8_t iir, lsr; 611119815Smarcel 612227032Scognet ns8250 = (struct ns8250_softc *)sc; 613119815Smarcel bas = &sc->sc_bas; 614157300Smarcel uart_lock(sc->sc_hwmtx); 615119815Smarcel iir = uart_getreg(bas, REG_IIR); 616247519Sganbold 617247519Sganbold if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 618247519Sganbold (void)uart_getreg(bas, DW_REG_USR); 619247519Sganbold uart_unlock(sc->sc_hwmtx); 620247519Sganbold return (0); 621247519Sganbold } 622120143Smarcel if (iir & IIR_NOPEND) { 623157300Smarcel uart_unlock(sc->sc_hwmtx); 624119815Smarcel return (0); 625120143Smarcel } 626119815Smarcel ipend = 0; 627119815Smarcel if (iir & IIR_RXRDY) { 628119815Smarcel lsr = uart_getreg(bas, REG_LSR); 629119815Smarcel if (lsr & LSR_OE) 630155971Smarcel ipend |= SER_INT_OVERRUN; 631119815Smarcel if (lsr & LSR_BI) 632155971Smarcel ipend |= SER_INT_BREAK; 633119815Smarcel if (lsr & LSR_RXRDY) 634155971Smarcel ipend |= SER_INT_RXREADY; 635119815Smarcel } else { 636227032Scognet if (iir & IIR_TXRDY) { 637155971Smarcel ipend |= SER_INT_TXIDLE; 638227032Scognet uart_setreg(bas, REG_IER, ns8250->ier); 639227032Scognet } else 640155971Smarcel ipend |= SER_INT_SIGCHG; 641119815Smarcel } 642190834Smarcel if (ipend == 0) 643190834Smarcel ns8250_clrint(bas); 644190834Smarcel uart_unlock(sc->sc_hwmtx); 645207533Smarius return (ipend); 646119815Smarcel} 647119815Smarcel 648254597Sianint 649119815Smarcelns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 650119815Smarcel int stopbits, int parity) 651119815Smarcel{ 652266046Sian struct ns8250_softc *ns8250; 653119815Smarcel struct uart_bas *bas; 654266046Sian int error, limit; 655119815Smarcel 656266046Sian ns8250 = (struct ns8250_softc*)sc; 657119815Smarcel bas = &sc->sc_bas; 658157300Smarcel uart_lock(sc->sc_hwmtx); 659266046Sian /* 660266046Sian * When using DW UART with BUSY detection it is necessary to wait 661266046Sian * until all serial transfers are finished before manipulating the 662266046Sian * line control. LCR will not be affected when UART is busy. 663266046Sian */ 664266046Sian if (ns8250->busy_detect != 0) { 665266046Sian /* 666266046Sian * Pick an arbitrary high limit to avoid getting stuck in 667266046Sian * an infinite loop in case when the hardware is broken. 668266046Sian */ 669266046Sian limit = 10 * 1024; 670266046Sian while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 671266046Sian --limit) 672266046Sian DELAY(4); 673266046Sian 674266046Sian if (limit <= 0) { 675266046Sian /* UART appears to be stuck */ 676266046Sian uart_unlock(sc->sc_hwmtx); 677266046Sian return (EIO); 678266046Sian } 679266046Sian } 680266046Sian 681120143Smarcel error = ns8250_param(bas, baudrate, databits, stopbits, parity); 682157300Smarcel uart_unlock(sc->sc_hwmtx); 683120143Smarcel return (error); 684119815Smarcel} 685119815Smarcel 686254597Sianint 687119815Smarcelns8250_bus_probe(struct uart_softc *sc) 688119815Smarcel{ 689179420Sbenno struct ns8250_softc *ns8250; 690119815Smarcel struct uart_bas *bas; 691119815Smarcel int count, delay, error, limit; 692158844Sbenno uint8_t lsr, mcr, ier; 693119815Smarcel 694179420Sbenno ns8250 = (struct ns8250_softc *)sc; 695119815Smarcel bas = &sc->sc_bas; 696119815Smarcel 697119815Smarcel error = ns8250_probe(bas); 698119815Smarcel if (error) 699119815Smarcel return (error); 700119815Smarcel 701119815Smarcel mcr = MCR_IE; 702119815Smarcel if (sc->sc_sysdev == NULL) { 703119815Smarcel /* By using ns8250_init() we also set DTR and RTS. */ 704158069Smarcel ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 705119815Smarcel } else 706119815Smarcel mcr |= MCR_DTR | MCR_RTS; 707119815Smarcel 708119815Smarcel error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 709119815Smarcel if (error) 710119815Smarcel return (error); 711119815Smarcel 712119815Smarcel /* 713119815Smarcel * Set loopback mode. This avoids having garbage on the wire and 714119815Smarcel * also allows us send and receive data. We set DTR and RTS to 715119815Smarcel * avoid the possibility that automatic flow-control prevents 716129757Stmm * any data from being sent. 717119815Smarcel */ 718129757Stmm uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 719119815Smarcel uart_barrier(bas); 720119815Smarcel 721119815Smarcel /* 722119815Smarcel * Enable FIFOs. And check that the UART has them. If not, we're 723129757Stmm * done. Since this is the first time we enable the FIFOs, we reset 724129757Stmm * them. 725119815Smarcel */ 726119815Smarcel uart_setreg(bas, REG_FCR, FCR_ENABLE); 727119815Smarcel uart_barrier(bas); 728157418Smarcel if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 729119815Smarcel /* 730119815Smarcel * NS16450 or INS8250. We don't bother to differentiate 731119815Smarcel * between them. They're too old to be interesting. 732119815Smarcel */ 733119815Smarcel uart_setreg(bas, REG_MCR, mcr); 734119815Smarcel uart_barrier(bas); 735157418Smarcel sc->sc_rxfifosz = sc->sc_txfifosz = 1; 736119815Smarcel device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 737119815Smarcel return (0); 738119815Smarcel } 739119815Smarcel 740129757Stmm uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 741119815Smarcel uart_barrier(bas); 742119815Smarcel 743119815Smarcel count = 0; 744119815Smarcel delay = ns8250_delay(bas); 745119815Smarcel 746119815Smarcel /* We have FIFOs. Drain the transmitter and receiver. */ 747119815Smarcel error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 748119815Smarcel if (error) { 749119815Smarcel uart_setreg(bas, REG_MCR, mcr); 750119815Smarcel uart_setreg(bas, REG_FCR, 0); 751119815Smarcel uart_barrier(bas); 752119815Smarcel goto describe; 753119815Smarcel } 754119815Smarcel 755119815Smarcel /* 756119815Smarcel * We should have a sufficiently clean "pipe" to determine the 757119815Smarcel * size of the FIFOs. We send as much characters as is reasonable 758218909Sbrucec * and wait for the overflow bit in the LSR register to be 759129757Stmm * asserted, counting the characters as we send them. Based on 760129757Stmm * that count we know the FIFO size. 761119815Smarcel */ 762129757Stmm do { 763119815Smarcel uart_setreg(bas, REG_DATA, 0); 764119815Smarcel uart_barrier(bas); 765119815Smarcel count++; 766119815Smarcel 767119815Smarcel limit = 30; 768129757Stmm lsr = 0; 769129757Stmm /* 770129757Stmm * LSR bits are cleared upon read, so we must accumulate 771129757Stmm * them to be able to test LSR_OE below. 772129757Stmm */ 773129757Stmm while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 774129757Stmm --limit) 775119815Smarcel DELAY(delay); 776119815Smarcel if (limit == 0) { 777179420Sbenno ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 778158844Sbenno uart_setreg(bas, REG_IER, ier); 779119815Smarcel uart_setreg(bas, REG_MCR, mcr); 780119815Smarcel uart_setreg(bas, REG_FCR, 0); 781119815Smarcel uart_barrier(bas); 782119815Smarcel count = 0; 783119815Smarcel goto describe; 784119815Smarcel } 785132650Smarcel } while ((lsr & LSR_OE) == 0 && count < 130); 786129757Stmm count--; 787119815Smarcel 788119815Smarcel uart_setreg(bas, REG_MCR, mcr); 789119815Smarcel 790119815Smarcel /* Reset FIFOs. */ 791119815Smarcel ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 792119815Smarcel 793119815Smarcel describe: 794129757Stmm if (count >= 14 && count <= 16) { 795119815Smarcel sc->sc_rxfifosz = 16; 796119815Smarcel device_set_desc(sc->sc_dev, "16550 or compatible"); 797129757Stmm } else if (count >= 28 && count <= 32) { 798119815Smarcel sc->sc_rxfifosz = 32; 799119815Smarcel device_set_desc(sc->sc_dev, "16650 or compatible"); 800129757Stmm } else if (count >= 56 && count <= 64) { 801119815Smarcel sc->sc_rxfifosz = 64; 802119815Smarcel device_set_desc(sc->sc_dev, "16750 or compatible"); 803129757Stmm } else if (count >= 112 && count <= 128) { 804119815Smarcel sc->sc_rxfifosz = 128; 805119815Smarcel device_set_desc(sc->sc_dev, "16950 or compatible"); 806119815Smarcel } else { 807119943Smarcel sc->sc_rxfifosz = 16; 808119815Smarcel device_set_desc(sc->sc_dev, 809119815Smarcel "Non-standard ns8250 class UART with FIFOs"); 810119815Smarcel } 811119815Smarcel 812119815Smarcel /* 813119815Smarcel * Force the Tx FIFO size to 16 bytes for now. We don't program the 814119815Smarcel * Tx trigger. Also, we assume that all data has been sent when the 815119815Smarcel * interrupt happens. 816119815Smarcel */ 817119815Smarcel sc->sc_txfifosz = 16; 818119815Smarcel 819133220Smarcel#if 0 820133220Smarcel /* 821133220Smarcel * XXX there are some issues related to hardware flow control and 822133220Smarcel * it's likely that uart(4) is the cause. This basicly needs more 823133220Smarcel * investigation, but we avoid using for hardware flow control 824133220Smarcel * until then. 825133220Smarcel */ 826120022Smarcel /* 16650s or higher have automatic flow control. */ 827120022Smarcel if (sc->sc_rxfifosz > 16) { 828120022Smarcel sc->sc_hwiflow = 1; 829120022Smarcel sc->sc_hwoflow = 1; 830120022Smarcel } 831133220Smarcel#endif 832120022Smarcel 833119815Smarcel return (0); 834119815Smarcel} 835119815Smarcel 836254597Sianint 837119815Smarcelns8250_bus_receive(struct uart_softc *sc) 838119815Smarcel{ 839119815Smarcel struct uart_bas *bas; 840119815Smarcel int xc; 841119815Smarcel uint8_t lsr; 842119815Smarcel 843119815Smarcel bas = &sc->sc_bas; 844157300Smarcel uart_lock(sc->sc_hwmtx); 845120146Smarcel lsr = uart_getreg(bas, REG_LSR); 846120146Smarcel while (lsr & LSR_RXRDY) { 847120146Smarcel if (uart_rx_full(sc)) { 848120146Smarcel sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 849119815Smarcel break; 850120146Smarcel } 851119815Smarcel xc = uart_getreg(bas, REG_DATA); 852119815Smarcel if (lsr & LSR_FE) 853119815Smarcel xc |= UART_STAT_FRAMERR; 854119815Smarcel if (lsr & LSR_PE) 855119815Smarcel xc |= UART_STAT_PARERR; 856119815Smarcel uart_rx_put(sc, xc); 857120146Smarcel lsr = uart_getreg(bas, REG_LSR); 858119815Smarcel } 859120146Smarcel /* Discard everything left in the Rx FIFO. */ 860120146Smarcel while (lsr & LSR_RXRDY) { 861120146Smarcel (void)uart_getreg(bas, REG_DATA); 862120146Smarcel uart_barrier(bas); 863120146Smarcel lsr = uart_getreg(bas, REG_LSR); 864120146Smarcel } 865157300Smarcel uart_unlock(sc->sc_hwmtx); 866119815Smarcel return (0); 867119815Smarcel} 868119815Smarcel 869254597Sianint 870119815Smarcelns8250_bus_setsig(struct uart_softc *sc, int sig) 871119815Smarcel{ 872119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 873119815Smarcel struct uart_bas *bas; 874119815Smarcel uint32_t new, old; 875119815Smarcel 876119815Smarcel bas = &sc->sc_bas; 877119815Smarcel do { 878119815Smarcel old = sc->sc_hwsig; 879119815Smarcel new = old; 880131043Sphk if (sig & SER_DDTR) { 881131043Sphk SIGCHG(sig & SER_DTR, new, SER_DTR, 882131043Sphk SER_DDTR); 883119815Smarcel } 884131043Sphk if (sig & SER_DRTS) { 885131043Sphk SIGCHG(sig & SER_RTS, new, SER_RTS, 886131043Sphk SER_DRTS); 887119815Smarcel } 888119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 889157300Smarcel uart_lock(sc->sc_hwmtx); 890119815Smarcel ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 891131043Sphk if (new & SER_DTR) 892119815Smarcel ns8250->mcr |= MCR_DTR; 893131043Sphk if (new & SER_RTS) 894119815Smarcel ns8250->mcr |= MCR_RTS; 895119815Smarcel uart_setreg(bas, REG_MCR, ns8250->mcr); 896119815Smarcel uart_barrier(bas); 897157300Smarcel uart_unlock(sc->sc_hwmtx); 898119815Smarcel return (0); 899119815Smarcel} 900119815Smarcel 901254597Sianint 902119815Smarcelns8250_bus_transmit(struct uart_softc *sc) 903119815Smarcel{ 904119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 905119815Smarcel struct uart_bas *bas; 906119815Smarcel int i; 907119815Smarcel 908119815Smarcel bas = &sc->sc_bas; 909157300Smarcel uart_lock(sc->sc_hwmtx); 910119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 911119815Smarcel ; 912119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 913119815Smarcel uart_barrier(bas); 914119815Smarcel for (i = 0; i < sc->sc_txdatasz; i++) { 915119815Smarcel uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 916119815Smarcel uart_barrier(bas); 917119815Smarcel } 918246016Scperciva if (broken_txfifo) 919246016Scperciva ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 920246016Scperciva else 921246016Scperciva sc->sc_txbusy = 1; 922157300Smarcel uart_unlock(sc->sc_hwmtx); 923246016Scperciva if (broken_txfifo) 924246016Scperciva uart_sched_softih(sc, SER_INT_TXIDLE); 925119815Smarcel return (0); 926119815Smarcel} 927262649Simp 928262649Simpvoid 929262649Simpns8250_bus_grab(struct uart_softc *sc) 930262649Simp{ 931262649Simp struct uart_bas *bas = &sc->sc_bas; 932262649Simp 933262649Simp /* 934262649Simp * turn off all interrupts to enter polling mode. Leave the 935262649Simp * saved mask alone. We'll restore whatever it was in ungrab. 936262649Simp * All pending interupt signals are reset when IER is set to 0. 937262649Simp */ 938262649Simp uart_lock(sc->sc_hwmtx); 939262649Simp uart_setreg(bas, REG_IER, 0); 940262649Simp uart_barrier(bas); 941262649Simp uart_unlock(sc->sc_hwmtx); 942262649Simp} 943262649Simp 944262649Simpvoid 945262649Simpns8250_bus_ungrab(struct uart_softc *sc) 946262649Simp{ 947262649Simp struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 948262649Simp struct uart_bas *bas = &sc->sc_bas; 949262649Simp 950262649Simp /* 951262649Simp * Restore previous interrupt mask 952262649Simp */ 953262649Simp uart_lock(sc->sc_hwmtx); 954262649Simp uart_setreg(bas, REG_IER, ns8250->ier); 955262649Simp uart_barrier(bas); 956262649Simp uart_unlock(sc->sc_hwmtx); 957262649Simp} 958