1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include "opt_platform.h" 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: releng/10.3/sys/dev/uart/uart_dev_ns8250.c 294229 2016-01-17 18:18:01Z ian $"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/kernel.h> 37#include <sys/sysctl.h> 38#include <machine/bus.h> 39 40#ifdef FDT 41#include <dev/fdt/fdt_common.h> 42#include <dev/ofw/ofw_bus.h> 43#include <dev/ofw/ofw_bus_subr.h> 44#endif 45 46#include <dev/uart/uart.h> 47#include <dev/uart/uart_cpu.h> 48#ifdef FDT 49#include <dev/uart/uart_cpu_fdt.h> 50#endif 51#include <dev/uart/uart_bus.h> 52#include <dev/uart/uart_dev_ns8250.h> 53#include <dev/uart/uart_ppstypes.h> 54 55#include <dev/ic/ns16550.h> 56 57#include "uart_if.h" 58 59#define DEFAULT_RCLK 1843200 60 61static int broken_txfifo = 0; 62SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, 63 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 64TUNABLE_INT("hw.broken_txfifo", &broken_txfifo); 65 66/* 67 * Clear pending interrupts. THRE is cleared by reading IIR. Data 68 * that may have been received gets lost here. 69 */ 70static void 71ns8250_clrint(struct uart_bas *bas) 72{ 73 uint8_t iir, lsr; 74 75 iir = uart_getreg(bas, REG_IIR); 76 while ((iir & IIR_NOPEND) == 0) { 77 iir &= IIR_IMASK; 78 if (iir == IIR_RLS) { 79 lsr = uart_getreg(bas, REG_LSR); 80 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 81 (void)uart_getreg(bas, REG_DATA); 82 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 83 (void)uart_getreg(bas, REG_DATA); 84 else if (iir == IIR_MLSC) 85 (void)uart_getreg(bas, REG_MSR); 86 uart_barrier(bas); 87 iir = uart_getreg(bas, REG_IIR); 88 } 89} 90 91static int 92ns8250_delay(struct uart_bas *bas) 93{ 94 int divisor; 95 u_char lcr; 96 97 lcr = uart_getreg(bas, REG_LCR); 98 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 99 uart_barrier(bas); 100 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 101 uart_barrier(bas); 102 uart_setreg(bas, REG_LCR, lcr); 103 uart_barrier(bas); 104 105 /* 1/10th the time to transmit 1 character (estimate). */ 106 if (divisor <= 134) 107 return (16000000 * divisor / bas->rclk); 108 return (16000 * divisor / (bas->rclk / 1000)); 109} 110 111static int 112ns8250_divisor(int rclk, int baudrate) 113{ 114 int actual_baud, divisor; 115 int error; 116 117 if (baudrate == 0) 118 return (0); 119 120 divisor = (rclk / (baudrate << 3) + 1) >> 1; 121 if (divisor == 0 || divisor >= 65536) 122 return (0); 123 actual_baud = rclk / (divisor << 4); 124 125 /* 10 times error in percent: */ 126 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 127 128 /* 3.0% maximum error tolerance: */ 129 if (error < -30 || error > 30) 130 return (0); 131 132 return (divisor); 133} 134 135static int 136ns8250_drain(struct uart_bas *bas, int what) 137{ 138 int delay, limit; 139 140 delay = ns8250_delay(bas); 141 142 if (what & UART_DRAIN_TRANSMITTER) { 143 /* 144 * Pick an arbitrary high limit to avoid getting stuck in 145 * an infinite loop when the hardware is broken. Make the 146 * limit high enough to handle large FIFOs. 147 */ 148 limit = 10*1024; 149 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 150 DELAY(delay); 151 if (limit == 0) { 152 /* printf("ns8250: transmitter appears stuck... "); */ 153 return (EIO); 154 } 155 } 156 157 if (what & UART_DRAIN_RECEIVER) { 158 /* 159 * Pick an arbitrary high limit to avoid getting stuck in 160 * an infinite loop when the hardware is broken. Make the 161 * limit high enough to handle large FIFOs and integrated 162 * UARTs. The HP rx2600 for example has 3 UARTs on the 163 * management board that tend to get a lot of data send 164 * to it when the UART is first activated. 165 */ 166 limit=10*4096; 167 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 168 (void)uart_getreg(bas, REG_DATA); 169 uart_barrier(bas); 170 DELAY(delay << 2); 171 } 172 if (limit == 0) { 173 /* printf("ns8250: receiver appears broken... "); */ 174 return (EIO); 175 } 176 } 177 178 return (0); 179} 180 181/* 182 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 183 * drained. WARNING: this function clobbers the FIFO setting! 184 */ 185static void 186ns8250_flush(struct uart_bas *bas, int what) 187{ 188 uint8_t fcr; 189 190 fcr = FCR_ENABLE; 191 if (what & UART_FLUSH_TRANSMITTER) 192 fcr |= FCR_XMT_RST; 193 if (what & UART_FLUSH_RECEIVER) 194 fcr |= FCR_RCV_RST; 195 uart_setreg(bas, REG_FCR, fcr); 196 uart_barrier(bas); 197} 198 199static int 200ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 201 int parity) 202{ 203 int divisor; 204 uint8_t lcr; 205 206 lcr = 0; 207 if (databits >= 8) 208 lcr |= LCR_8BITS; 209 else if (databits == 7) 210 lcr |= LCR_7BITS; 211 else if (databits == 6) 212 lcr |= LCR_6BITS; 213 else 214 lcr |= LCR_5BITS; 215 if (stopbits > 1) 216 lcr |= LCR_STOPB; 217 lcr |= parity << 3; 218 219 /* Set baudrate. */ 220 if (baudrate > 0) { 221 divisor = ns8250_divisor(bas->rclk, baudrate); 222 if (divisor == 0) 223 return (EINVAL); 224 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 225 uart_barrier(bas); 226 uart_setreg(bas, REG_DLL, divisor & 0xff); 227 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 228 uart_barrier(bas); 229 } 230 231 /* Set LCR and clear DLAB. */ 232 uart_setreg(bas, REG_LCR, lcr); 233 uart_barrier(bas); 234 return (0); 235} 236 237/* 238 * Low-level UART interface. 239 */ 240static int ns8250_probe(struct uart_bas *bas); 241static void ns8250_init(struct uart_bas *bas, int, int, int, int); 242static void ns8250_term(struct uart_bas *bas); 243static void ns8250_putc(struct uart_bas *bas, int); 244static int ns8250_rxready(struct uart_bas *bas); 245static int ns8250_getc(struct uart_bas *bas, struct mtx *); 246 247struct uart_ops uart_ns8250_ops = { 248 .probe = ns8250_probe, 249 .init = ns8250_init, 250 .term = ns8250_term, 251 .putc = ns8250_putc, 252 .rxready = ns8250_rxready, 253 .getc = ns8250_getc, 254}; 255 256static int 257ns8250_probe(struct uart_bas *bas) 258{ 259 u_char val; 260 261 /* Check known 0 bits that don't depend on DLAB. */ 262 val = uart_getreg(bas, REG_IIR); 263 if (val & 0x30) 264 return (ENXIO); 265 /* 266 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 267 * chip, but otherwise doesn't seem to have a function. In 268 * other words, uart(4) works regardless. Ignore that bit so 269 * the probe succeeds. 270 */ 271 val = uart_getreg(bas, REG_MCR); 272 if (val & 0xa0) 273 return (ENXIO); 274 275 return (0); 276} 277 278static void 279ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 280 int parity) 281{ 282 u_char ier; 283 284 if (bas->rclk == 0) 285 bas->rclk = DEFAULT_RCLK; 286 ns8250_param(bas, baudrate, databits, stopbits, parity); 287 288 /* Disable all interrupt sources. */ 289 /* 290 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 291 * UARTs split the receive time-out interrupt bit out separately as 292 * 0x10. This gets handled by ier_mask and ier_rxbits below. 293 */ 294 ier = uart_getreg(bas, REG_IER) & 0xe0; 295 uart_setreg(bas, REG_IER, ier); 296 uart_barrier(bas); 297 298 /* Disable the FIFO (if present). */ 299 uart_setreg(bas, REG_FCR, 0); 300 uart_barrier(bas); 301 302 /* Set RTS & DTR. */ 303 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 304 uart_barrier(bas); 305 306 ns8250_clrint(bas); 307} 308 309static void 310ns8250_term(struct uart_bas *bas) 311{ 312 313 /* Clear RTS & DTR. */ 314 uart_setreg(bas, REG_MCR, MCR_IE); 315 uart_barrier(bas); 316} 317 318static void 319ns8250_putc(struct uart_bas *bas, int c) 320{ 321 int limit; 322 323 limit = 250000; 324 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 325 DELAY(4); 326 uart_setreg(bas, REG_DATA, c); 327 uart_barrier(bas); 328 limit = 250000; 329 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 330 DELAY(4); 331} 332 333static int 334ns8250_rxready(struct uart_bas *bas) 335{ 336 337 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 338} 339 340static int 341ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 342{ 343 int c; 344 345 uart_lock(hwmtx); 346 347 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 348 uart_unlock(hwmtx); 349 DELAY(4); 350 uart_lock(hwmtx); 351 } 352 353 c = uart_getreg(bas, REG_DATA); 354 355 uart_unlock(hwmtx); 356 357 return (c); 358} 359 360static kobj_method_t ns8250_methods[] = { 361 KOBJMETHOD(uart_attach, ns8250_bus_attach), 362 KOBJMETHOD(uart_detach, ns8250_bus_detach), 363 KOBJMETHOD(uart_flush, ns8250_bus_flush), 364 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 365 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 366 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 367 KOBJMETHOD(uart_param, ns8250_bus_param), 368 KOBJMETHOD(uart_probe, ns8250_bus_probe), 369 KOBJMETHOD(uart_receive, ns8250_bus_receive), 370 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 371 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 372 KOBJMETHOD(uart_grab, ns8250_bus_grab), 373 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 374 { 0, 0 } 375}; 376 377struct uart_class uart_ns8250_class = { 378 "ns8250", 379 ns8250_methods, 380 sizeof(struct ns8250_softc), 381 .uc_ops = &uart_ns8250_ops, 382 .uc_range = 8, 383 .uc_rclk = DEFAULT_RCLK 384}; 385 386#ifdef FDT 387static struct ofw_compat_data compat_data[] = { 388 {"ns16550", (uintptr_t)&uart_ns8250_class}, 389 {NULL, (uintptr_t)NULL}, 390}; 391UART_FDT_CLASS_AND_DEVICE(compat_data); 392#endif 393 394/* Use token-pasting to form SER_ and MSR_ named constants. */ 395#define SER(sig) SER_##sig 396#define SERD(sig) SER_D##sig 397#define MSR(sig) MSR_##sig 398#define MSRD(sig) MSR_D##sig 399 400/* 401 * Detect signal changes using software delta detection. The previous state of 402 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 403 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 404 * new state of both the signal and the delta bits. 405 */ 406#define SIGCHGSW(var, msr, sig) \ 407 if ((msr) & MSR(sig)) { \ 408 if ((var & SER(sig)) == 0) \ 409 var |= SERD(sig) | SER(sig); \ 410 } else { \ 411 if ((var & SER(sig)) != 0) \ 412 var = SERD(sig) | (var & ~SER(sig)); \ 413 } 414 415/* 416 * Detect signal changes using the hardware msr delta bits. This is currently 417 * used only when PPS timing information is being captured using the "narrow 418 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 419 * by time the interrupt handler is invoked. The hardware will latch the fact 420 * that it changed in the delta bits. 421 */ 422#define SIGCHGHW(var, msr, sig) \ 423 if ((msr) & MSRD(sig)) { \ 424 if (((msr) & MSR(sig)) != 0) \ 425 var |= SERD(sig) | SER(sig); \ 426 else \ 427 var = SERD(sig) | (var & ~SER(sig)); \ 428 } 429 430int 431ns8250_bus_attach(struct uart_softc *sc) 432{ 433 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 434 struct uart_bas *bas; 435 unsigned int ivar; 436#ifdef FDT 437 phandle_t node; 438 pcell_t cell; 439#endif 440 441 ns8250->busy_detect = 0; 442 443#ifdef FDT 444 /* 445 * Check whether uart requires to read USR reg when IIR_BUSY and 446 * has broken txfifo. 447 */ 448 node = ofw_bus_get_node(sc->sc_dev); 449 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 450 ns8250->busy_detect = 1; 451 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 452 broken_txfifo = 1; 453#endif 454 455 bas = &sc->sc_bas; 456 457 ns8250->mcr = uart_getreg(bas, REG_MCR); 458 ns8250->fcr = FCR_ENABLE; 459 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 460 &ivar)) { 461 if (UART_FLAGS_FCR_RX_LOW(ivar)) 462 ns8250->fcr |= FCR_RX_LOW; 463 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 464 ns8250->fcr |= FCR_RX_MEDL; 465 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 466 ns8250->fcr |= FCR_RX_HIGH; 467 else 468 ns8250->fcr |= FCR_RX_MEDH; 469 } else 470 ns8250->fcr |= FCR_RX_MEDH; 471 472 /* Get IER mask */ 473 ivar = 0xf0; 474 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 475 &ivar); 476 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 477 478 /* Get IER RX interrupt bits */ 479 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 480 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 481 &ivar); 482 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 483 484 uart_setreg(bas, REG_FCR, ns8250->fcr); 485 uart_barrier(bas); 486 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 487 488 if (ns8250->mcr & MCR_DTR) 489 sc->sc_hwsig |= SER_DTR; 490 if (ns8250->mcr & MCR_RTS) 491 sc->sc_hwsig |= SER_RTS; 492 ns8250_bus_getsig(sc); 493 494 ns8250_clrint(bas); 495 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 496 ns8250->ier |= ns8250->ier_rxbits; 497 uart_setreg(bas, REG_IER, ns8250->ier); 498 uart_barrier(bas); 499 500 /* 501 * Timing of the H/W access was changed with r253161 of uart_core.c 502 * It has been observed that an ITE IT8513E would signal a break 503 * condition with pretty much every character it received, unless 504 * it had enough time to settle between ns8250_bus_attach() and 505 * ns8250_bus_ipend() -- which it accidentally had before r253161. 506 * It's not understood why the UART chip behaves this way and it 507 * could very well be that the DELAY make the H/W work in the same 508 * accidental manner as before. More analysis is warranted, but 509 * at least now we fixed a known regression. 510 */ 511 DELAY(200); 512 return (0); 513} 514 515int 516ns8250_bus_detach(struct uart_softc *sc) 517{ 518 struct ns8250_softc *ns8250; 519 struct uart_bas *bas; 520 u_char ier; 521 522 ns8250 = (struct ns8250_softc *)sc; 523 bas = &sc->sc_bas; 524 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 525 uart_setreg(bas, REG_IER, ier); 526 uart_barrier(bas); 527 ns8250_clrint(bas); 528 return (0); 529} 530 531int 532ns8250_bus_flush(struct uart_softc *sc, int what) 533{ 534 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 535 struct uart_bas *bas; 536 int error; 537 538 bas = &sc->sc_bas; 539 uart_lock(sc->sc_hwmtx); 540 if (sc->sc_rxfifosz > 1) { 541 ns8250_flush(bas, what); 542 uart_setreg(bas, REG_FCR, ns8250->fcr); 543 uart_barrier(bas); 544 error = 0; 545 } else 546 error = ns8250_drain(bas, what); 547 uart_unlock(sc->sc_hwmtx); 548 return (error); 549} 550 551int 552ns8250_bus_getsig(struct uart_softc *sc) 553{ 554 uint32_t old, sig; 555 uint8_t msr; 556 557 /* 558 * The delta bits are reputed to be broken on some hardware, so use 559 * software delta detection by default. Use the hardware delta bits 560 * when capturing PPS pulses which are too narrow for software detection 561 * to see the edges. Hardware delta for RI doesn't work like the 562 * others, so always use software for it. Other threads may be changing 563 * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully 564 * update without other changes happening. Note that the SIGCHGxx() 565 * macros carefully preserve the delta bits when we have to loop several 566 * times and a signal transitions between iterations. 567 */ 568 do { 569 old = sc->sc_hwsig; 570 sig = old; 571 uart_lock(sc->sc_hwmtx); 572 msr = uart_getreg(&sc->sc_bas, REG_MSR); 573 uart_unlock(sc->sc_hwmtx); 574 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 575 SIGCHGHW(sig, msr, DSR); 576 SIGCHGHW(sig, msr, CTS); 577 SIGCHGHW(sig, msr, DCD); 578 } else { 579 SIGCHGSW(sig, msr, DSR); 580 SIGCHGSW(sig, msr, CTS); 581 SIGCHGSW(sig, msr, DCD); 582 } 583 SIGCHGSW(sig, msr, RI); 584 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 585 return (sig); 586} 587 588int 589ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 590{ 591 struct uart_bas *bas; 592 int baudrate, divisor, error; 593 uint8_t efr, lcr; 594 595 bas = &sc->sc_bas; 596 error = 0; 597 uart_lock(sc->sc_hwmtx); 598 switch (request) { 599 case UART_IOCTL_BREAK: 600 lcr = uart_getreg(bas, REG_LCR); 601 if (data) 602 lcr |= LCR_SBREAK; 603 else 604 lcr &= ~LCR_SBREAK; 605 uart_setreg(bas, REG_LCR, lcr); 606 uart_barrier(bas); 607 break; 608 case UART_IOCTL_IFLOW: 609 lcr = uart_getreg(bas, REG_LCR); 610 uart_barrier(bas); 611 uart_setreg(bas, REG_LCR, 0xbf); 612 uart_barrier(bas); 613 efr = uart_getreg(bas, REG_EFR); 614 if (data) 615 efr |= EFR_RTS; 616 else 617 efr &= ~EFR_RTS; 618 uart_setreg(bas, REG_EFR, efr); 619 uart_barrier(bas); 620 uart_setreg(bas, REG_LCR, lcr); 621 uart_barrier(bas); 622 break; 623 case UART_IOCTL_OFLOW: 624 lcr = uart_getreg(bas, REG_LCR); 625 uart_barrier(bas); 626 uart_setreg(bas, REG_LCR, 0xbf); 627 uart_barrier(bas); 628 efr = uart_getreg(bas, REG_EFR); 629 if (data) 630 efr |= EFR_CTS; 631 else 632 efr &= ~EFR_CTS; 633 uart_setreg(bas, REG_EFR, efr); 634 uart_barrier(bas); 635 uart_setreg(bas, REG_LCR, lcr); 636 uart_barrier(bas); 637 break; 638 case UART_IOCTL_BAUD: 639 lcr = uart_getreg(bas, REG_LCR); 640 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 641 uart_barrier(bas); 642 divisor = uart_getreg(bas, REG_DLL) | 643 (uart_getreg(bas, REG_DLH) << 8); 644 uart_barrier(bas); 645 uart_setreg(bas, REG_LCR, lcr); 646 uart_barrier(bas); 647 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 648 if (baudrate > 0) 649 *(int*)data = baudrate; 650 else 651 error = ENXIO; 652 break; 653 default: 654 error = EINVAL; 655 break; 656 } 657 uart_unlock(sc->sc_hwmtx); 658 return (error); 659} 660 661int 662ns8250_bus_ipend(struct uart_softc *sc) 663{ 664 struct uart_bas *bas; 665 struct ns8250_softc *ns8250; 666 int ipend; 667 uint8_t iir, lsr; 668 669 ns8250 = (struct ns8250_softc *)sc; 670 bas = &sc->sc_bas; 671 uart_lock(sc->sc_hwmtx); 672 iir = uart_getreg(bas, REG_IIR); 673 674 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 675 (void)uart_getreg(bas, DW_REG_USR); 676 uart_unlock(sc->sc_hwmtx); 677 return (0); 678 } 679 if (iir & IIR_NOPEND) { 680 uart_unlock(sc->sc_hwmtx); 681 return (0); 682 } 683 ipend = 0; 684 if (iir & IIR_RXRDY) { 685 lsr = uart_getreg(bas, REG_LSR); 686 if (lsr & LSR_OE) 687 ipend |= SER_INT_OVERRUN; 688 if (lsr & LSR_BI) 689 ipend |= SER_INT_BREAK; 690 if (lsr & LSR_RXRDY) 691 ipend |= SER_INT_RXREADY; 692 } else { 693 if (iir & IIR_TXRDY) { 694 ipend |= SER_INT_TXIDLE; 695 uart_setreg(bas, REG_IER, ns8250->ier); 696 } else 697 ipend |= SER_INT_SIGCHG; 698 } 699 if (ipend == 0) 700 ns8250_clrint(bas); 701 uart_unlock(sc->sc_hwmtx); 702 return (ipend); 703} 704 705int 706ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 707 int stopbits, int parity) 708{ 709 struct ns8250_softc *ns8250; 710 struct uart_bas *bas; 711 int error, limit; 712 713 ns8250 = (struct ns8250_softc*)sc; 714 bas = &sc->sc_bas; 715 uart_lock(sc->sc_hwmtx); 716 /* 717 * When using DW UART with BUSY detection it is necessary to wait 718 * until all serial transfers are finished before manipulating the 719 * line control. LCR will not be affected when UART is busy. 720 */ 721 if (ns8250->busy_detect != 0) { 722 /* 723 * Pick an arbitrary high limit to avoid getting stuck in 724 * an infinite loop in case when the hardware is broken. 725 */ 726 limit = 10 * 1024; 727 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 728 --limit) 729 DELAY(4); 730 731 if (limit <= 0) { 732 /* UART appears to be stuck */ 733 uart_unlock(sc->sc_hwmtx); 734 return (EIO); 735 } 736 } 737 738 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 739 uart_unlock(sc->sc_hwmtx); 740 return (error); 741} 742 743int 744ns8250_bus_probe(struct uart_softc *sc) 745{ 746 struct ns8250_softc *ns8250; 747 struct uart_bas *bas; 748 int count, delay, error, limit; 749 uint8_t lsr, mcr, ier; 750 751 ns8250 = (struct ns8250_softc *)sc; 752 bas = &sc->sc_bas; 753 754 error = ns8250_probe(bas); 755 if (error) 756 return (error); 757 758 mcr = MCR_IE; 759 if (sc->sc_sysdev == NULL) { 760 /* By using ns8250_init() we also set DTR and RTS. */ 761 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 762 } else 763 mcr |= MCR_DTR | MCR_RTS; 764 765 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 766 if (error) 767 return (error); 768 769 /* 770 * Set loopback mode. This avoids having garbage on the wire and 771 * also allows us send and receive data. We set DTR and RTS to 772 * avoid the possibility that automatic flow-control prevents 773 * any data from being sent. 774 */ 775 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 776 uart_barrier(bas); 777 778 /* 779 * Enable FIFOs. And check that the UART has them. If not, we're 780 * done. Since this is the first time we enable the FIFOs, we reset 781 * them. 782 */ 783 uart_setreg(bas, REG_FCR, FCR_ENABLE); 784 uart_barrier(bas); 785 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 786 /* 787 * NS16450 or INS8250. We don't bother to differentiate 788 * between them. They're too old to be interesting. 789 */ 790 uart_setreg(bas, REG_MCR, mcr); 791 uart_barrier(bas); 792 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 793 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 794 return (0); 795 } 796 797 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 798 uart_barrier(bas); 799 800 count = 0; 801 delay = ns8250_delay(bas); 802 803 /* We have FIFOs. Drain the transmitter and receiver. */ 804 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 805 if (error) { 806 uart_setreg(bas, REG_MCR, mcr); 807 uart_setreg(bas, REG_FCR, 0); 808 uart_barrier(bas); 809 goto describe; 810 } 811 812 /* 813 * We should have a sufficiently clean "pipe" to determine the 814 * size of the FIFOs. We send as much characters as is reasonable 815 * and wait for the overflow bit in the LSR register to be 816 * asserted, counting the characters as we send them. Based on 817 * that count we know the FIFO size. 818 */ 819 do { 820 uart_setreg(bas, REG_DATA, 0); 821 uart_barrier(bas); 822 count++; 823 824 limit = 30; 825 lsr = 0; 826 /* 827 * LSR bits are cleared upon read, so we must accumulate 828 * them to be able to test LSR_OE below. 829 */ 830 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 831 --limit) 832 DELAY(delay); 833 if (limit == 0) { 834 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 835 uart_setreg(bas, REG_IER, ier); 836 uart_setreg(bas, REG_MCR, mcr); 837 uart_setreg(bas, REG_FCR, 0); 838 uart_barrier(bas); 839 count = 0; 840 goto describe; 841 } 842 } while ((lsr & LSR_OE) == 0 && count < 130); 843 count--; 844 845 uart_setreg(bas, REG_MCR, mcr); 846 847 /* Reset FIFOs. */ 848 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 849 850 describe: 851 if (count >= 14 && count <= 16) { 852 sc->sc_rxfifosz = 16; 853 device_set_desc(sc->sc_dev, "16550 or compatible"); 854 } else if (count >= 28 && count <= 32) { 855 sc->sc_rxfifosz = 32; 856 device_set_desc(sc->sc_dev, "16650 or compatible"); 857 } else if (count >= 56 && count <= 64) { 858 sc->sc_rxfifosz = 64; 859 device_set_desc(sc->sc_dev, "16750 or compatible"); 860 } else if (count >= 112 && count <= 128) { 861 sc->sc_rxfifosz = 128; 862 device_set_desc(sc->sc_dev, "16950 or compatible"); 863 } else { 864 sc->sc_rxfifosz = 16; 865 device_set_desc(sc->sc_dev, 866 "Non-standard ns8250 class UART with FIFOs"); 867 } 868 869 /* 870 * Force the Tx FIFO size to 16 bytes for now. We don't program the 871 * Tx trigger. Also, we assume that all data has been sent when the 872 * interrupt happens. 873 */ 874 sc->sc_txfifosz = 16; 875 876#if 0 877 /* 878 * XXX there are some issues related to hardware flow control and 879 * it's likely that uart(4) is the cause. This basicly needs more 880 * investigation, but we avoid using for hardware flow control 881 * until then. 882 */ 883 /* 16650s or higher have automatic flow control. */ 884 if (sc->sc_rxfifosz > 16) { 885 sc->sc_hwiflow = 1; 886 sc->sc_hwoflow = 1; 887 } 888#endif 889 890 return (0); 891} 892 893int 894ns8250_bus_receive(struct uart_softc *sc) 895{ 896 struct uart_bas *bas; 897 int xc; 898 uint8_t lsr; 899 900 bas = &sc->sc_bas; 901 uart_lock(sc->sc_hwmtx); 902 lsr = uart_getreg(bas, REG_LSR); 903 while (lsr & LSR_RXRDY) { 904 if (uart_rx_full(sc)) { 905 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 906 break; 907 } 908 xc = uart_getreg(bas, REG_DATA); 909 if (lsr & LSR_FE) 910 xc |= UART_STAT_FRAMERR; 911 if (lsr & LSR_PE) 912 xc |= UART_STAT_PARERR; 913 uart_rx_put(sc, xc); 914 lsr = uart_getreg(bas, REG_LSR); 915 } 916 /* Discard everything left in the Rx FIFO. */ 917 while (lsr & LSR_RXRDY) { 918 (void)uart_getreg(bas, REG_DATA); 919 uart_barrier(bas); 920 lsr = uart_getreg(bas, REG_LSR); 921 } 922 uart_unlock(sc->sc_hwmtx); 923 return (0); 924} 925 926int 927ns8250_bus_setsig(struct uart_softc *sc, int sig) 928{ 929 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 930 struct uart_bas *bas; 931 uint32_t new, old; 932 933 bas = &sc->sc_bas; 934 do { 935 old = sc->sc_hwsig; 936 new = old; 937 if (sig & SER_DDTR) { 938 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 939 } 940 if (sig & SER_DRTS) { 941 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 942 } 943 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 944 uart_lock(sc->sc_hwmtx); 945 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 946 if (new & SER_DTR) 947 ns8250->mcr |= MCR_DTR; 948 if (new & SER_RTS) 949 ns8250->mcr |= MCR_RTS; 950 uart_setreg(bas, REG_MCR, ns8250->mcr); 951 uart_barrier(bas); 952 uart_unlock(sc->sc_hwmtx); 953 return (0); 954} 955 956int 957ns8250_bus_transmit(struct uart_softc *sc) 958{ 959 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 960 struct uart_bas *bas; 961 int i; 962 963 bas = &sc->sc_bas; 964 uart_lock(sc->sc_hwmtx); 965 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 966 ; 967 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 968 uart_barrier(bas); 969 for (i = 0; i < sc->sc_txdatasz; i++) { 970 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 971 uart_barrier(bas); 972 } 973 if (broken_txfifo) 974 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 975 else 976 sc->sc_txbusy = 1; 977 uart_unlock(sc->sc_hwmtx); 978 if (broken_txfifo) 979 uart_sched_softih(sc, SER_INT_TXIDLE); 980 return (0); 981} 982 983void 984ns8250_bus_grab(struct uart_softc *sc) 985{ 986 struct uart_bas *bas = &sc->sc_bas; 987 988 /* 989 * turn off all interrupts to enter polling mode. Leave the 990 * saved mask alone. We'll restore whatever it was in ungrab. 991 * All pending interupt signals are reset when IER is set to 0. 992 */ 993 uart_lock(sc->sc_hwmtx); 994 uart_setreg(bas, REG_IER, 0); 995 uart_barrier(bas); 996 uart_unlock(sc->sc_hwmtx); 997} 998 999void 1000ns8250_bus_ungrab(struct uart_softc *sc) 1001{ 1002 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1003 struct uart_bas *bas = &sc->sc_bas; 1004 1005 /* 1006 * Restore previous interrupt mask 1007 */ 1008 uart_lock(sc->sc_hwmtx); 1009 uart_setreg(bas, REG_IER, ns8250->ier); 1010 uart_barrier(bas); 1011 uart_unlock(sc->sc_hwmtx); 1012} 1013