uart_dev_ns8250.c revision 247519
1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include "opt_platform.h" 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 247519 2013-03-01 01:42:31Z ganbold $"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/kernel.h> 37#include <sys/sysctl.h> 38#include <machine/bus.h> 39 40#ifdef FDT 41#include <dev/fdt/fdt_common.h> 42#include <dev/ofw/ofw_bus.h> 43#include <dev/ofw/ofw_bus_subr.h> 44#endif 45 46#include <dev/uart/uart.h> 47#include <dev/uart/uart_cpu.h> 48#include <dev/uart/uart_bus.h> 49 50#include <dev/ic/ns16550.h> 51 52#include "uart_if.h" 53 54#define DEFAULT_RCLK 1843200 55 56static int broken_txfifo = 0; 57SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, 58 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 59TUNABLE_INT("hw.broken_txfifo", &broken_txfifo); 60 61/* 62 * Clear pending interrupts. THRE is cleared by reading IIR. Data 63 * that may have been received gets lost here. 64 */ 65static void 66ns8250_clrint(struct uart_bas *bas) 67{ 68 uint8_t iir, lsr; 69 70 iir = uart_getreg(bas, REG_IIR); 71 while ((iir & IIR_NOPEND) == 0) { 72 iir &= IIR_IMASK; 73 if (iir == IIR_RLS) { 74 lsr = uart_getreg(bas, REG_LSR); 75 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 76 (void)uart_getreg(bas, REG_DATA); 77 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 78 (void)uart_getreg(bas, REG_DATA); 79 else if (iir == IIR_MLSC) 80 (void)uart_getreg(bas, REG_MSR); 81 uart_barrier(bas); 82 iir = uart_getreg(bas, REG_IIR); 83 } 84} 85 86static int 87ns8250_delay(struct uart_bas *bas) 88{ 89 int divisor; 90 u_char lcr; 91 92 lcr = uart_getreg(bas, REG_LCR); 93 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 94 uart_barrier(bas); 95 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 96 uart_barrier(bas); 97 uart_setreg(bas, REG_LCR, lcr); 98 uart_barrier(bas); 99 100 /* 1/10th the time to transmit 1 character (estimate). */ 101 if (divisor <= 134) 102 return (16000000 * divisor / bas->rclk); 103 return (16000 * divisor / (bas->rclk / 1000)); 104} 105 106static int 107ns8250_divisor(int rclk, int baudrate) 108{ 109 int actual_baud, divisor; 110 int error; 111 112 if (baudrate == 0) 113 return (0); 114 115 divisor = (rclk / (baudrate << 3) + 1) >> 1; 116 if (divisor == 0 || divisor >= 65536) 117 return (0); 118 actual_baud = rclk / (divisor << 4); 119 120 /* 10 times error in percent: */ 121 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 122 123 /* 3.0% maximum error tolerance: */ 124 if (error < -30 || error > 30) 125 return (0); 126 127 return (divisor); 128} 129 130static int 131ns8250_drain(struct uart_bas *bas, int what) 132{ 133 int delay, limit; 134 135 delay = ns8250_delay(bas); 136 137 if (what & UART_DRAIN_TRANSMITTER) { 138 /* 139 * Pick an arbitrary high limit to avoid getting stuck in 140 * an infinite loop when the hardware is broken. Make the 141 * limit high enough to handle large FIFOs. 142 */ 143 limit = 10*1024; 144 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 145 DELAY(delay); 146 if (limit == 0) { 147 /* printf("ns8250: transmitter appears stuck... "); */ 148 return (EIO); 149 } 150 } 151 152 if (what & UART_DRAIN_RECEIVER) { 153 /* 154 * Pick an arbitrary high limit to avoid getting stuck in 155 * an infinite loop when the hardware is broken. Make the 156 * limit high enough to handle large FIFOs and integrated 157 * UARTs. The HP rx2600 for example has 3 UARTs on the 158 * management board that tend to get a lot of data send 159 * to it when the UART is first activated. 160 */ 161 limit=10*4096; 162 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 163 (void)uart_getreg(bas, REG_DATA); 164 uart_barrier(bas); 165 DELAY(delay << 2); 166 } 167 if (limit == 0) { 168 /* printf("ns8250: receiver appears broken... "); */ 169 return (EIO); 170 } 171 } 172 173 return (0); 174} 175 176/* 177 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 178 * drained. WARNING: this function clobbers the FIFO setting! 179 */ 180static void 181ns8250_flush(struct uart_bas *bas, int what) 182{ 183 uint8_t fcr; 184 185 fcr = FCR_ENABLE; 186 if (what & UART_FLUSH_TRANSMITTER) 187 fcr |= FCR_XMT_RST; 188 if (what & UART_FLUSH_RECEIVER) 189 fcr |= FCR_RCV_RST; 190 uart_setreg(bas, REG_FCR, fcr); 191 uart_barrier(bas); 192} 193 194static int 195ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 196 int parity) 197{ 198 int divisor; 199 uint8_t lcr; 200 201 lcr = 0; 202 if (databits >= 8) 203 lcr |= LCR_8BITS; 204 else if (databits == 7) 205 lcr |= LCR_7BITS; 206 else if (databits == 6) 207 lcr |= LCR_6BITS; 208 else 209 lcr |= LCR_5BITS; 210 if (stopbits > 1) 211 lcr |= LCR_STOPB; 212 lcr |= parity << 3; 213 214 /* Set baudrate. */ 215 if (baudrate > 0) { 216 divisor = ns8250_divisor(bas->rclk, baudrate); 217 if (divisor == 0) 218 return (EINVAL); 219 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 220 uart_barrier(bas); 221 uart_setreg(bas, REG_DLL, divisor & 0xff); 222 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 223 uart_barrier(bas); 224 } 225 226 /* Set LCR and clear DLAB. */ 227 uart_setreg(bas, REG_LCR, lcr); 228 uart_barrier(bas); 229 return (0); 230} 231 232/* 233 * Low-level UART interface. 234 */ 235static int ns8250_probe(struct uart_bas *bas); 236static void ns8250_init(struct uart_bas *bas, int, int, int, int); 237static void ns8250_term(struct uart_bas *bas); 238static void ns8250_putc(struct uart_bas *bas, int); 239static int ns8250_rxready(struct uart_bas *bas); 240static int ns8250_getc(struct uart_bas *bas, struct mtx *); 241 242static struct uart_ops uart_ns8250_ops = { 243 .probe = ns8250_probe, 244 .init = ns8250_init, 245 .term = ns8250_term, 246 .putc = ns8250_putc, 247 .rxready = ns8250_rxready, 248 .getc = ns8250_getc, 249}; 250 251static int 252ns8250_probe(struct uart_bas *bas) 253{ 254 u_char val; 255 256 /* Check known 0 bits that don't depend on DLAB. */ 257 val = uart_getreg(bas, REG_IIR); 258 if (val & 0x30) 259 return (ENXIO); 260 /* 261 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 262 * chip, but otherwise doesn't seem to have a function. In 263 * other words, uart(4) works regardless. Ignore that bit so 264 * the probe succeeds. 265 */ 266 val = uart_getreg(bas, REG_MCR); 267 if (val & 0xa0) 268 return (ENXIO); 269 270 return (0); 271} 272 273static void 274ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 275 int parity) 276{ 277 u_char ier; 278 279 if (bas->rclk == 0) 280 bas->rclk = DEFAULT_RCLK; 281 ns8250_param(bas, baudrate, databits, stopbits, parity); 282 283 /* Disable all interrupt sources. */ 284 /* 285 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 286 * UARTs split the receive time-out interrupt bit out separately as 287 * 0x10. This gets handled by ier_mask and ier_rxbits below. 288 */ 289 ier = uart_getreg(bas, REG_IER) & 0xe0; 290 uart_setreg(bas, REG_IER, ier); 291 uart_barrier(bas); 292 293 /* Disable the FIFO (if present). */ 294 uart_setreg(bas, REG_FCR, 0); 295 uart_barrier(bas); 296 297 /* Set RTS & DTR. */ 298 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 299 uart_barrier(bas); 300 301 ns8250_clrint(bas); 302} 303 304static void 305ns8250_term(struct uart_bas *bas) 306{ 307 308 /* Clear RTS & DTR. */ 309 uart_setreg(bas, REG_MCR, MCR_IE); 310 uart_barrier(bas); 311} 312 313static void 314ns8250_putc(struct uart_bas *bas, int c) 315{ 316 int limit; 317 318 limit = 250000; 319 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 320 DELAY(4); 321 uart_setreg(bas, REG_DATA, c); 322 uart_barrier(bas); 323 limit = 250000; 324 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 325 DELAY(4); 326} 327 328static int 329ns8250_rxready(struct uart_bas *bas) 330{ 331 332 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 333} 334 335static int 336ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 337{ 338 int c; 339 340 uart_lock(hwmtx); 341 342 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 343 uart_unlock(hwmtx); 344 DELAY(4); 345 uart_lock(hwmtx); 346 } 347 348 c = uart_getreg(bas, REG_DATA); 349 350 uart_unlock(hwmtx); 351 352 return (c); 353} 354 355/* 356 * High-level UART interface. 357 */ 358struct ns8250_softc { 359 struct uart_softc base; 360 uint8_t fcr; 361 uint8_t ier; 362 uint8_t mcr; 363 364 uint8_t ier_mask; 365 uint8_t ier_rxbits; 366 uint8_t busy_detect; 367}; 368 369static int ns8250_bus_attach(struct uart_softc *); 370static int ns8250_bus_detach(struct uart_softc *); 371static int ns8250_bus_flush(struct uart_softc *, int); 372static int ns8250_bus_getsig(struct uart_softc *); 373static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 374static int ns8250_bus_ipend(struct uart_softc *); 375static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 376static int ns8250_bus_probe(struct uart_softc *); 377static int ns8250_bus_receive(struct uart_softc *); 378static int ns8250_bus_setsig(struct uart_softc *, int); 379static int ns8250_bus_transmit(struct uart_softc *); 380 381static kobj_method_t ns8250_methods[] = { 382 KOBJMETHOD(uart_attach, ns8250_bus_attach), 383 KOBJMETHOD(uart_detach, ns8250_bus_detach), 384 KOBJMETHOD(uart_flush, ns8250_bus_flush), 385 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 386 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 387 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 388 KOBJMETHOD(uart_param, ns8250_bus_param), 389 KOBJMETHOD(uart_probe, ns8250_bus_probe), 390 KOBJMETHOD(uart_receive, ns8250_bus_receive), 391 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 392 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 393 { 0, 0 } 394}; 395 396struct uart_class uart_ns8250_class = { 397 "ns8250", 398 ns8250_methods, 399 sizeof(struct ns8250_softc), 400 .uc_ops = &uart_ns8250_ops, 401 .uc_range = 8, 402 .uc_rclk = DEFAULT_RCLK 403}; 404 405#define SIGCHG(c, i, s, d) \ 406 if (c) { \ 407 i |= (i & s) ? s : s | d; \ 408 } else { \ 409 i = (i & s) ? (i & ~s) | d : i; \ 410 } 411 412static int 413ns8250_bus_attach(struct uart_softc *sc) 414{ 415 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 416 struct uart_bas *bas; 417 unsigned int ivar; 418#ifdef FDT 419 phandle_t node; 420 pcell_t cell; 421#endif 422 423 ns8250->busy_detect = 0; 424 425#ifdef FDT 426 /* 427 * Check whether uart requires to read USR reg when IIR_BUSY and 428 * has broken txfifo. 429 */ 430 node = ofw_bus_get_node(sc->sc_dev); 431 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 432 ns8250->busy_detect = 1; 433 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 434 broken_txfifo = 1; 435#endif 436 437 bas = &sc->sc_bas; 438 439 ns8250->mcr = uart_getreg(bas, REG_MCR); 440 ns8250->fcr = FCR_ENABLE; 441 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 442 &ivar)) { 443 if (UART_FLAGS_FCR_RX_LOW(ivar)) 444 ns8250->fcr |= FCR_RX_LOW; 445 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 446 ns8250->fcr |= FCR_RX_MEDL; 447 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 448 ns8250->fcr |= FCR_RX_HIGH; 449 else 450 ns8250->fcr |= FCR_RX_MEDH; 451 } else 452 ns8250->fcr |= FCR_RX_MEDH; 453 454 /* Get IER mask */ 455 ivar = 0xf0; 456 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 457 &ivar); 458 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 459 460 /* Get IER RX interrupt bits */ 461 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 462 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 463 &ivar); 464 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 465 466 uart_setreg(bas, REG_FCR, ns8250->fcr); 467 uart_barrier(bas); 468 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 469 470 if (ns8250->mcr & MCR_DTR) 471 sc->sc_hwsig |= SER_DTR; 472 if (ns8250->mcr & MCR_RTS) 473 sc->sc_hwsig |= SER_RTS; 474 ns8250_bus_getsig(sc); 475 476 ns8250_clrint(bas); 477 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 478 ns8250->ier |= ns8250->ier_rxbits; 479 uart_setreg(bas, REG_IER, ns8250->ier); 480 uart_barrier(bas); 481 482 return (0); 483} 484 485static int 486ns8250_bus_detach(struct uart_softc *sc) 487{ 488 struct ns8250_softc *ns8250; 489 struct uart_bas *bas; 490 u_char ier; 491 492 ns8250 = (struct ns8250_softc *)sc; 493 bas = &sc->sc_bas; 494 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 495 uart_setreg(bas, REG_IER, ier); 496 uart_barrier(bas); 497 ns8250_clrint(bas); 498 return (0); 499} 500 501static int 502ns8250_bus_flush(struct uart_softc *sc, int what) 503{ 504 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 505 struct uart_bas *bas; 506 int error; 507 508 bas = &sc->sc_bas; 509 uart_lock(sc->sc_hwmtx); 510 if (sc->sc_rxfifosz > 1) { 511 ns8250_flush(bas, what); 512 uart_setreg(bas, REG_FCR, ns8250->fcr); 513 uart_barrier(bas); 514 error = 0; 515 } else 516 error = ns8250_drain(bas, what); 517 uart_unlock(sc->sc_hwmtx); 518 return (error); 519} 520 521static int 522ns8250_bus_getsig(struct uart_softc *sc) 523{ 524 uint32_t new, old, sig; 525 uint8_t msr; 526 527 do { 528 old = sc->sc_hwsig; 529 sig = old; 530 uart_lock(sc->sc_hwmtx); 531 msr = uart_getreg(&sc->sc_bas, REG_MSR); 532 uart_unlock(sc->sc_hwmtx); 533 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 534 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 535 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 536 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 537 new = sig & ~SER_MASK_DELTA; 538 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 539 return (sig); 540} 541 542static int 543ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 544{ 545 struct uart_bas *bas; 546 int baudrate, divisor, error; 547 uint8_t efr, lcr; 548 549 bas = &sc->sc_bas; 550 error = 0; 551 uart_lock(sc->sc_hwmtx); 552 switch (request) { 553 case UART_IOCTL_BREAK: 554 lcr = uart_getreg(bas, REG_LCR); 555 if (data) 556 lcr |= LCR_SBREAK; 557 else 558 lcr &= ~LCR_SBREAK; 559 uart_setreg(bas, REG_LCR, lcr); 560 uart_barrier(bas); 561 break; 562 case UART_IOCTL_IFLOW: 563 lcr = uart_getreg(bas, REG_LCR); 564 uart_barrier(bas); 565 uart_setreg(bas, REG_LCR, 0xbf); 566 uart_barrier(bas); 567 efr = uart_getreg(bas, REG_EFR); 568 if (data) 569 efr |= EFR_RTS; 570 else 571 efr &= ~EFR_RTS; 572 uart_setreg(bas, REG_EFR, efr); 573 uart_barrier(bas); 574 uart_setreg(bas, REG_LCR, lcr); 575 uart_barrier(bas); 576 break; 577 case UART_IOCTL_OFLOW: 578 lcr = uart_getreg(bas, REG_LCR); 579 uart_barrier(bas); 580 uart_setreg(bas, REG_LCR, 0xbf); 581 uart_barrier(bas); 582 efr = uart_getreg(bas, REG_EFR); 583 if (data) 584 efr |= EFR_CTS; 585 else 586 efr &= ~EFR_CTS; 587 uart_setreg(bas, REG_EFR, efr); 588 uart_barrier(bas); 589 uart_setreg(bas, REG_LCR, lcr); 590 uart_barrier(bas); 591 break; 592 case UART_IOCTL_BAUD: 593 lcr = uart_getreg(bas, REG_LCR); 594 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 595 uart_barrier(bas); 596 divisor = uart_getreg(bas, REG_DLL) | 597 (uart_getreg(bas, REG_DLH) << 8); 598 uart_barrier(bas); 599 uart_setreg(bas, REG_LCR, lcr); 600 uart_barrier(bas); 601 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 602 if (baudrate > 0) 603 *(int*)data = baudrate; 604 else 605 error = ENXIO; 606 break; 607 default: 608 error = EINVAL; 609 break; 610 } 611 uart_unlock(sc->sc_hwmtx); 612 return (error); 613} 614 615static int 616ns8250_bus_ipend(struct uart_softc *sc) 617{ 618 struct uart_bas *bas; 619 struct ns8250_softc *ns8250; 620 int ipend; 621 uint8_t iir, lsr; 622 623 ns8250 = (struct ns8250_softc *)sc; 624 bas = &sc->sc_bas; 625 uart_lock(sc->sc_hwmtx); 626 iir = uart_getreg(bas, REG_IIR); 627 628 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 629 (void)uart_getreg(bas, DW_REG_USR); 630 uart_unlock(sc->sc_hwmtx); 631 return (0); 632 } 633 if (iir & IIR_NOPEND) { 634 uart_unlock(sc->sc_hwmtx); 635 return (0); 636 } 637 ipend = 0; 638 if (iir & IIR_RXRDY) { 639 lsr = uart_getreg(bas, REG_LSR); 640 if (lsr & LSR_OE) 641 ipend |= SER_INT_OVERRUN; 642 if (lsr & LSR_BI) 643 ipend |= SER_INT_BREAK; 644 if (lsr & LSR_RXRDY) 645 ipend |= SER_INT_RXREADY; 646 } else { 647 if (iir & IIR_TXRDY) { 648 ipend |= SER_INT_TXIDLE; 649 uart_setreg(bas, REG_IER, ns8250->ier); 650 } else 651 ipend |= SER_INT_SIGCHG; 652 } 653 if (ipend == 0) 654 ns8250_clrint(bas); 655 uart_unlock(sc->sc_hwmtx); 656 return (ipend); 657} 658 659static int 660ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 661 int stopbits, int parity) 662{ 663 struct uart_bas *bas; 664 int error; 665 666 bas = &sc->sc_bas; 667 uart_lock(sc->sc_hwmtx); 668 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 669 uart_unlock(sc->sc_hwmtx); 670 return (error); 671} 672 673static int 674ns8250_bus_probe(struct uart_softc *sc) 675{ 676 struct ns8250_softc *ns8250; 677 struct uart_bas *bas; 678 int count, delay, error, limit; 679 uint8_t lsr, mcr, ier; 680 681 ns8250 = (struct ns8250_softc *)sc; 682 bas = &sc->sc_bas; 683 684 error = ns8250_probe(bas); 685 if (error) 686 return (error); 687 688 mcr = MCR_IE; 689 if (sc->sc_sysdev == NULL) { 690 /* By using ns8250_init() we also set DTR and RTS. */ 691 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 692 } else 693 mcr |= MCR_DTR | MCR_RTS; 694 695 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 696 if (error) 697 return (error); 698 699 /* 700 * Set loopback mode. This avoids having garbage on the wire and 701 * also allows us send and receive data. We set DTR and RTS to 702 * avoid the possibility that automatic flow-control prevents 703 * any data from being sent. 704 */ 705 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 706 uart_barrier(bas); 707 708 /* 709 * Enable FIFOs. And check that the UART has them. If not, we're 710 * done. Since this is the first time we enable the FIFOs, we reset 711 * them. 712 */ 713 uart_setreg(bas, REG_FCR, FCR_ENABLE); 714 uart_barrier(bas); 715 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 716 /* 717 * NS16450 or INS8250. We don't bother to differentiate 718 * between them. They're too old to be interesting. 719 */ 720 uart_setreg(bas, REG_MCR, mcr); 721 uart_barrier(bas); 722 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 723 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 724 return (0); 725 } 726 727 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 728 uart_barrier(bas); 729 730 count = 0; 731 delay = ns8250_delay(bas); 732 733 /* We have FIFOs. Drain the transmitter and receiver. */ 734 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 735 if (error) { 736 uart_setreg(bas, REG_MCR, mcr); 737 uart_setreg(bas, REG_FCR, 0); 738 uart_barrier(bas); 739 goto describe; 740 } 741 742 /* 743 * We should have a sufficiently clean "pipe" to determine the 744 * size of the FIFOs. We send as much characters as is reasonable 745 * and wait for the overflow bit in the LSR register to be 746 * asserted, counting the characters as we send them. Based on 747 * that count we know the FIFO size. 748 */ 749 do { 750 uart_setreg(bas, REG_DATA, 0); 751 uart_barrier(bas); 752 count++; 753 754 limit = 30; 755 lsr = 0; 756 /* 757 * LSR bits are cleared upon read, so we must accumulate 758 * them to be able to test LSR_OE below. 759 */ 760 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 761 --limit) 762 DELAY(delay); 763 if (limit == 0) { 764 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 765 uart_setreg(bas, REG_IER, ier); 766 uart_setreg(bas, REG_MCR, mcr); 767 uart_setreg(bas, REG_FCR, 0); 768 uart_barrier(bas); 769 count = 0; 770 goto describe; 771 } 772 } while ((lsr & LSR_OE) == 0 && count < 130); 773 count--; 774 775 uart_setreg(bas, REG_MCR, mcr); 776 777 /* Reset FIFOs. */ 778 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 779 780 describe: 781 if (count >= 14 && count <= 16) { 782 sc->sc_rxfifosz = 16; 783 device_set_desc(sc->sc_dev, "16550 or compatible"); 784 } else if (count >= 28 && count <= 32) { 785 sc->sc_rxfifosz = 32; 786 device_set_desc(sc->sc_dev, "16650 or compatible"); 787 } else if (count >= 56 && count <= 64) { 788 sc->sc_rxfifosz = 64; 789 device_set_desc(sc->sc_dev, "16750 or compatible"); 790 } else if (count >= 112 && count <= 128) { 791 sc->sc_rxfifosz = 128; 792 device_set_desc(sc->sc_dev, "16950 or compatible"); 793 } else { 794 sc->sc_rxfifosz = 16; 795 device_set_desc(sc->sc_dev, 796 "Non-standard ns8250 class UART with FIFOs"); 797 } 798 799 /* 800 * Force the Tx FIFO size to 16 bytes for now. We don't program the 801 * Tx trigger. Also, we assume that all data has been sent when the 802 * interrupt happens. 803 */ 804 sc->sc_txfifosz = 16; 805 806#if 0 807 /* 808 * XXX there are some issues related to hardware flow control and 809 * it's likely that uart(4) is the cause. This basicly needs more 810 * investigation, but we avoid using for hardware flow control 811 * until then. 812 */ 813 /* 16650s or higher have automatic flow control. */ 814 if (sc->sc_rxfifosz > 16) { 815 sc->sc_hwiflow = 1; 816 sc->sc_hwoflow = 1; 817 } 818#endif 819 820 return (0); 821} 822 823static int 824ns8250_bus_receive(struct uart_softc *sc) 825{ 826 struct uart_bas *bas; 827 int xc; 828 uint8_t lsr; 829 830 bas = &sc->sc_bas; 831 uart_lock(sc->sc_hwmtx); 832 lsr = uart_getreg(bas, REG_LSR); 833 while (lsr & LSR_RXRDY) { 834 if (uart_rx_full(sc)) { 835 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 836 break; 837 } 838 xc = uart_getreg(bas, REG_DATA); 839 if (lsr & LSR_FE) 840 xc |= UART_STAT_FRAMERR; 841 if (lsr & LSR_PE) 842 xc |= UART_STAT_PARERR; 843 uart_rx_put(sc, xc); 844 lsr = uart_getreg(bas, REG_LSR); 845 } 846 /* Discard everything left in the Rx FIFO. */ 847 while (lsr & LSR_RXRDY) { 848 (void)uart_getreg(bas, REG_DATA); 849 uart_barrier(bas); 850 lsr = uart_getreg(bas, REG_LSR); 851 } 852 uart_unlock(sc->sc_hwmtx); 853 return (0); 854} 855 856static int 857ns8250_bus_setsig(struct uart_softc *sc, int sig) 858{ 859 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 860 struct uart_bas *bas; 861 uint32_t new, old; 862 863 bas = &sc->sc_bas; 864 do { 865 old = sc->sc_hwsig; 866 new = old; 867 if (sig & SER_DDTR) { 868 SIGCHG(sig & SER_DTR, new, SER_DTR, 869 SER_DDTR); 870 } 871 if (sig & SER_DRTS) { 872 SIGCHG(sig & SER_RTS, new, SER_RTS, 873 SER_DRTS); 874 } 875 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 876 uart_lock(sc->sc_hwmtx); 877 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 878 if (new & SER_DTR) 879 ns8250->mcr |= MCR_DTR; 880 if (new & SER_RTS) 881 ns8250->mcr |= MCR_RTS; 882 uart_setreg(bas, REG_MCR, ns8250->mcr); 883 uart_barrier(bas); 884 uart_unlock(sc->sc_hwmtx); 885 return (0); 886} 887 888static int 889ns8250_bus_transmit(struct uart_softc *sc) 890{ 891 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 892 struct uart_bas *bas; 893 int i; 894 895 bas = &sc->sc_bas; 896 uart_lock(sc->sc_hwmtx); 897 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 898 ; 899 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 900 uart_barrier(bas); 901 for (i = 0; i < sc->sc_txdatasz; i++) { 902 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 903 uart_barrier(bas); 904 } 905 if (broken_txfifo) 906 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 907 else 908 sc->sc_txbusy = 1; 909 uart_unlock(sc->sc_hwmtx); 910 if (broken_txfifo) 911 uart_sched_softih(sc, SER_INT_TXIDLE); 912 return (0); 913} 914