uart_dev_ns8250.c revision 177117
1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 177117 2008-03-12 19:09:20Z sam $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> 37#include <dev/uart/uart_cpu.h> 38#include <dev/uart/uart_bus.h> 39 40#include <dev/ic/ns16550.h> 41 42#include "uart_if.h" 43 44#define DEFAULT_RCLK 1843200 45 46/* 47 * Clear pending interrupts. THRE is cleared by reading IIR. Data 48 * that may have been received gets lost here. 49 */ 50static void 51ns8250_clrint(struct uart_bas *bas) 52{ 53 uint8_t iir; 54 55 iir = uart_getreg(bas, REG_IIR); 56 while ((iir & IIR_NOPEND) == 0) { 57 iir &= IIR_IMASK; 58 if (iir == IIR_RLS) 59 (void)uart_getreg(bas, REG_LSR); 60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 61 (void)uart_getreg(bas, REG_DATA); 62 else if (iir == IIR_MLSC) 63 (void)uart_getreg(bas, REG_MSR); 64 uart_barrier(bas); 65 iir = uart_getreg(bas, REG_IIR); 66 } 67} 68 69static int 70ns8250_delay(struct uart_bas *bas) 71{ 72 int divisor; 73 u_char lcr; 74 75 lcr = uart_getreg(bas, REG_LCR); 76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 77 uart_barrier(bas); 78 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 79 uart_barrier(bas); 80 uart_setreg(bas, REG_LCR, lcr); 81 uart_barrier(bas); 82 83 /* 1/10th the time to transmit 1 character (estimate). */ 84 if (divisor <= 134) 85 return (16000000 * divisor / bas->rclk); 86 return (16000 * divisor / (bas->rclk / 1000)); 87} 88 89static int 90ns8250_divisor(int rclk, int baudrate) 91{ 92 int actual_baud, divisor; 93 int error; 94 95 if (baudrate == 0) 96 return (0); 97 98 divisor = (rclk / (baudrate << 3) + 1) >> 1; 99 if (divisor == 0 || divisor >= 65536) 100 return (0); 101 actual_baud = rclk / (divisor << 4); 102 103 /* 10 times error in percent: */ 104 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 105 106 /* 3.0% maximum error tolerance: */ 107 if (error < -30 || error > 30) 108 return (0); 109 110 return (divisor); 111} 112 113static int 114ns8250_drain(struct uart_bas *bas, int what) 115{ 116 int delay, limit; 117 118 delay = ns8250_delay(bas); 119 120 if (what & UART_DRAIN_TRANSMITTER) { 121 /* 122 * Pick an arbitrary high limit to avoid getting stuck in 123 * an infinite loop when the hardware is broken. Make the 124 * limit high enough to handle large FIFOs. 125 */ 126 limit = 10*1024; 127 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 128 DELAY(delay); 129 if (limit == 0) { 130 /* printf("ns8250: transmitter appears stuck... "); */ 131 return (EIO); 132 } 133 } 134 135 if (what & UART_DRAIN_RECEIVER) { 136 /* 137 * Pick an arbitrary high limit to avoid getting stuck in 138 * an infinite loop when the hardware is broken. Make the 139 * limit high enough to handle large FIFOs and integrated 140 * UARTs. The HP rx2600 for example has 3 UARTs on the 141 * management board that tend to get a lot of data send 142 * to it when the UART is first activated. 143 */ 144 limit=10*4096; 145 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 146 (void)uart_getreg(bas, REG_DATA); 147 uart_barrier(bas); 148 DELAY(delay << 2); 149 } 150 if (limit == 0) { 151 /* printf("ns8250: receiver appears broken... "); */ 152 return (EIO); 153 } 154 } 155 156 return (0); 157} 158 159/* 160 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 161 * drained. WARNING: this function clobbers the FIFO setting! 162 */ 163static void 164ns8250_flush(struct uart_bas *bas, int what) 165{ 166 uint8_t fcr; 167 168 fcr = FCR_ENABLE; 169 if (what & UART_FLUSH_TRANSMITTER) 170 fcr |= FCR_XMT_RST; 171 if (what & UART_FLUSH_RECEIVER) 172 fcr |= FCR_RCV_RST; 173 uart_setreg(bas, REG_FCR, fcr); 174 uart_barrier(bas); 175} 176 177static int 178ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 179 int parity) 180{ 181 int divisor; 182 uint8_t lcr; 183 184 lcr = 0; 185 if (databits >= 8) 186 lcr |= LCR_8BITS; 187 else if (databits == 7) 188 lcr |= LCR_7BITS; 189 else if (databits == 6) 190 lcr |= LCR_6BITS; 191 else 192 lcr |= LCR_5BITS; 193 if (stopbits > 1) 194 lcr |= LCR_STOPB; 195 lcr |= parity << 3; 196 197 /* Set baudrate. */ 198 if (baudrate > 0) { 199 divisor = ns8250_divisor(bas->rclk, baudrate); 200 if (divisor == 0) 201 return (EINVAL); 202 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 203 uart_barrier(bas); 204 uart_setreg(bas, REG_DLL, divisor & 0xff); 205 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 206 uart_barrier(bas); 207 } 208 209 /* Set LCR and clear DLAB. */ 210 uart_setreg(bas, REG_LCR, lcr); 211 uart_barrier(bas); 212 return (0); 213} 214 215/* 216 * Low-level UART interface. 217 */ 218static int ns8250_probe(struct uart_bas *bas); 219static void ns8250_init(struct uart_bas *bas, int, int, int, int); 220static void ns8250_term(struct uart_bas *bas); 221static void ns8250_putc(struct uart_bas *bas, int); 222static int ns8250_rxready(struct uart_bas *bas); 223static int ns8250_getc(struct uart_bas *bas, struct mtx *); 224 225static struct uart_ops uart_ns8250_ops = { 226 .probe = ns8250_probe, 227 .init = ns8250_init, 228 .term = ns8250_term, 229 .putc = ns8250_putc, 230 .rxready = ns8250_rxready, 231 .getc = ns8250_getc, 232}; 233 234static int 235ns8250_probe(struct uart_bas *bas) 236{ 237 u_char val; 238 239 /* Check known 0 bits that don't depend on DLAB. */ 240 val = uart_getreg(bas, REG_IIR); 241 if (val & 0x30) 242 return (ENXIO); 243 val = uart_getreg(bas, REG_MCR); 244 if (val & 0xe0) 245 return (ENXIO); 246 247 return (0); 248} 249 250static void 251ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 252 int parity) 253{ 254 u_char ier; 255 256 if (bas->rclk == 0) 257 bas->rclk = DEFAULT_RCLK; 258 ns8250_param(bas, baudrate, databits, stopbits, parity); 259 260 /* Disable all interrupt sources. */ 261 ier = uart_getreg(bas, REG_IER) & 0xf0; 262 uart_setreg(bas, REG_IER, ier); 263 uart_barrier(bas); 264 265 /* Disable the FIFO (if present). */ 266 uart_setreg(bas, REG_FCR, 0); 267 uart_barrier(bas); 268 269 /* Set RTS & DTR. */ 270 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 271 uart_barrier(bas); 272 273 ns8250_clrint(bas); 274} 275 276static void 277ns8250_term(struct uart_bas *bas) 278{ 279 280 /* Clear RTS & DTR. */ 281 uart_setreg(bas, REG_MCR, MCR_IE); 282 uart_barrier(bas); 283} 284 285static void 286ns8250_putc(struct uart_bas *bas, int c) 287{ 288 int limit; 289 290 limit = 250000; 291 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 292 DELAY(4); 293 uart_setreg(bas, REG_DATA, c); 294 uart_barrier(bas); 295 limit = 250000; 296 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 297 DELAY(4); 298} 299 300static int 301ns8250_rxready(struct uart_bas *bas) 302{ 303 304 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 305} 306 307static int 308ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 309{ 310 int c; 311 312 uart_lock(hwmtx); 313 314 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 315 uart_unlock(hwmtx); 316 DELAY(4); 317 uart_lock(hwmtx); 318 } 319 320 c = uart_getreg(bas, REG_DATA); 321 322 uart_unlock(hwmtx); 323 324 return (c); 325} 326 327/* 328 * High-level UART interface. 329 */ 330struct ns8250_softc { 331 struct uart_softc base; 332 uint8_t fcr; 333 uint8_t ier; 334 uint8_t mcr; 335}; 336 337static int ns8250_bus_attach(struct uart_softc *); 338static int ns8250_bus_detach(struct uart_softc *); 339static int ns8250_bus_flush(struct uart_softc *, int); 340static int ns8250_bus_getsig(struct uart_softc *); 341static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 342static int ns8250_bus_ipend(struct uart_softc *); 343static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 344static int ns8250_bus_probe(struct uart_softc *); 345static int ns8250_bus_receive(struct uart_softc *); 346static int ns8250_bus_setsig(struct uart_softc *, int); 347static int ns8250_bus_transmit(struct uart_softc *); 348 349static kobj_method_t ns8250_methods[] = { 350 KOBJMETHOD(uart_attach, ns8250_bus_attach), 351 KOBJMETHOD(uart_detach, ns8250_bus_detach), 352 KOBJMETHOD(uart_flush, ns8250_bus_flush), 353 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 354 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 355 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 356 KOBJMETHOD(uart_param, ns8250_bus_param), 357 KOBJMETHOD(uart_probe, ns8250_bus_probe), 358 KOBJMETHOD(uart_receive, ns8250_bus_receive), 359 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 360 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 361 { 0, 0 } 362}; 363 364struct uart_class uart_ns8250_class = { 365 "ns8250", 366 ns8250_methods, 367 sizeof(struct ns8250_softc), 368 .uc_ops = &uart_ns8250_ops, 369 .uc_range = 8, 370 .uc_rclk = DEFAULT_RCLK 371}; 372 373#define SIGCHG(c, i, s, d) \ 374 if (c) { \ 375 i |= (i & s) ? s : s | d; \ 376 } else { \ 377 i = (i & s) ? (i & ~s) | d : i; \ 378 } 379 380static int 381ns8250_bus_attach(struct uart_softc *sc) 382{ 383 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 384 struct uart_bas *bas; 385 unsigned int ivar; 386 387 bas = &sc->sc_bas; 388 389 ns8250->mcr = uart_getreg(bas, REG_MCR); 390 ns8250->fcr = FCR_ENABLE; 391 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 392 &ivar)) { 393 if (UART_FLAGS_FCR_RX_LOW(ivar)) 394 ns8250->fcr |= FCR_RX_LOW; 395 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 396 ns8250->fcr |= FCR_RX_MEDL; 397 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 398 ns8250->fcr |= FCR_RX_HIGH; 399 else 400 ns8250->fcr |= FCR_RX_MEDH; 401 } else 402 ns8250->fcr |= FCR_RX_MEDH; 403 uart_setreg(bas, REG_FCR, ns8250->fcr); 404 uart_barrier(bas); 405 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 406 407 if (ns8250->mcr & MCR_DTR) 408 sc->sc_hwsig |= SER_DTR; 409 if (ns8250->mcr & MCR_RTS) 410 sc->sc_hwsig |= SER_RTS; 411 ns8250_bus_getsig(sc); 412 413 ns8250_clrint(bas); 414 ns8250->ier = uart_getreg(bas, REG_IER) & 0xf0; 415 ns8250->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY; 416 uart_setreg(bas, REG_IER, ns8250->ier); 417 uart_barrier(bas); 418 return (0); 419} 420 421static int 422ns8250_bus_detach(struct uart_softc *sc) 423{ 424 struct uart_bas *bas; 425 u_char ier; 426 427 bas = &sc->sc_bas; 428 ier = uart_getreg(bas, REG_IER) & 0xf0; 429 uart_setreg(bas, REG_IER, ier); 430 uart_barrier(bas); 431 ns8250_clrint(bas); 432 return (0); 433} 434 435static int 436ns8250_bus_flush(struct uart_softc *sc, int what) 437{ 438 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 439 struct uart_bas *bas; 440 int error; 441 442 bas = &sc->sc_bas; 443 uart_lock(sc->sc_hwmtx); 444 if (sc->sc_rxfifosz > 1) { 445 ns8250_flush(bas, what); 446 uart_setreg(bas, REG_FCR, ns8250->fcr); 447 uart_barrier(bas); 448 error = 0; 449 } else 450 error = ns8250_drain(bas, what); 451 uart_unlock(sc->sc_hwmtx); 452 return (error); 453} 454 455static int 456ns8250_bus_getsig(struct uart_softc *sc) 457{ 458 uint32_t new, old, sig; 459 uint8_t msr; 460 461 do { 462 old = sc->sc_hwsig; 463 sig = old; 464 uart_lock(sc->sc_hwmtx); 465 msr = uart_getreg(&sc->sc_bas, REG_MSR); 466 uart_unlock(sc->sc_hwmtx); 467 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 468 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 469 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 470 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 471 new = sig & ~SER_MASK_DELTA; 472 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 473 return (sig); 474} 475 476static int 477ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 478{ 479 struct uart_bas *bas; 480 int baudrate, divisor, error; 481 uint8_t efr, lcr; 482 483 bas = &sc->sc_bas; 484 error = 0; 485 uart_lock(sc->sc_hwmtx); 486 switch (request) { 487 case UART_IOCTL_BREAK: 488 lcr = uart_getreg(bas, REG_LCR); 489 if (data) 490 lcr |= LCR_SBREAK; 491 else 492 lcr &= ~LCR_SBREAK; 493 uart_setreg(bas, REG_LCR, lcr); 494 uart_barrier(bas); 495 break; 496 case UART_IOCTL_IFLOW: 497 lcr = uart_getreg(bas, REG_LCR); 498 uart_barrier(bas); 499 uart_setreg(bas, REG_LCR, 0xbf); 500 uart_barrier(bas); 501 efr = uart_getreg(bas, REG_EFR); 502 if (data) 503 efr |= EFR_RTS; 504 else 505 efr &= ~EFR_RTS; 506 uart_setreg(bas, REG_EFR, efr); 507 uart_barrier(bas); 508 uart_setreg(bas, REG_LCR, lcr); 509 uart_barrier(bas); 510 break; 511 case UART_IOCTL_OFLOW: 512 lcr = uart_getreg(bas, REG_LCR); 513 uart_barrier(bas); 514 uart_setreg(bas, REG_LCR, 0xbf); 515 uart_barrier(bas); 516 efr = uart_getreg(bas, REG_EFR); 517 if (data) 518 efr |= EFR_CTS; 519 else 520 efr &= ~EFR_CTS; 521 uart_setreg(bas, REG_EFR, efr); 522 uart_barrier(bas); 523 uart_setreg(bas, REG_LCR, lcr); 524 uart_barrier(bas); 525 break; 526 case UART_IOCTL_BAUD: 527 lcr = uart_getreg(bas, REG_LCR); 528 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 529 uart_barrier(bas); 530 divisor = uart_getreg(bas, REG_DLL) | 531 (uart_getreg(bas, REG_DLH) << 8); 532 uart_barrier(bas); 533 uart_setreg(bas, REG_LCR, lcr); 534 uart_barrier(bas); 535 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 536 if (baudrate > 0) 537 *(int*)data = baudrate; 538 else 539 error = ENXIO; 540 break; 541 default: 542 error = EINVAL; 543 break; 544 } 545 uart_unlock(sc->sc_hwmtx); 546 return (error); 547} 548 549static int 550ns8250_bus_ipend(struct uart_softc *sc) 551{ 552 struct uart_bas *bas; 553 int ipend; 554 uint8_t iir, lsr; 555 556 bas = &sc->sc_bas; 557 uart_lock(sc->sc_hwmtx); 558 iir = uart_getreg(bas, REG_IIR); 559 if (iir & IIR_NOPEND) { 560 uart_unlock(sc->sc_hwmtx); 561 return (0); 562 } 563 ipend = 0; 564 if (iir & IIR_RXRDY) { 565 lsr = uart_getreg(bas, REG_LSR); 566 uart_unlock(sc->sc_hwmtx); 567 if (lsr & LSR_OE) 568 ipend |= SER_INT_OVERRUN; 569 if (lsr & LSR_BI) 570 ipend |= SER_INT_BREAK; 571 if (lsr & LSR_RXRDY) 572 ipend |= SER_INT_RXREADY; 573 } else { 574 uart_unlock(sc->sc_hwmtx); 575 if (iir & IIR_TXRDY) 576 ipend |= SER_INT_TXIDLE; 577 else 578 ipend |= SER_INT_SIGCHG; 579 } 580 return ((sc->sc_leaving) ? 0 : ipend); 581} 582 583static int 584ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 585 int stopbits, int parity) 586{ 587 struct uart_bas *bas; 588 int error; 589 590 bas = &sc->sc_bas; 591 uart_lock(sc->sc_hwmtx); 592 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 593 uart_unlock(sc->sc_hwmtx); 594 return (error); 595} 596 597static int 598ns8250_bus_probe(struct uart_softc *sc) 599{ 600 struct uart_bas *bas; 601 int count, delay, error, limit; 602 uint8_t lsr, mcr, ier; 603 604 bas = &sc->sc_bas; 605 606 error = ns8250_probe(bas); 607 if (error) 608 return (error); 609 610 mcr = MCR_IE; 611 if (sc->sc_sysdev == NULL) { 612 /* By using ns8250_init() we also set DTR and RTS. */ 613 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 614 } else 615 mcr |= MCR_DTR | MCR_RTS; 616 617 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 618 if (error) 619 return (error); 620 621 /* 622 * Set loopback mode. This avoids having garbage on the wire and 623 * also allows us send and receive data. We set DTR and RTS to 624 * avoid the possibility that automatic flow-control prevents 625 * any data from being sent. 626 */ 627 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 628 uart_barrier(bas); 629 630 /* 631 * Enable FIFOs. And check that the UART has them. If not, we're 632 * done. Since this is the first time we enable the FIFOs, we reset 633 * them. 634 */ 635 uart_setreg(bas, REG_FCR, FCR_ENABLE); 636 uart_barrier(bas); 637 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 638 /* 639 * NS16450 or INS8250. We don't bother to differentiate 640 * between them. They're too old to be interesting. 641 */ 642 uart_setreg(bas, REG_MCR, mcr); 643 uart_barrier(bas); 644 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 645 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 646 return (0); 647 } 648 649 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 650 uart_barrier(bas); 651 652 count = 0; 653 delay = ns8250_delay(bas); 654 655 /* We have FIFOs. Drain the transmitter and receiver. */ 656 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 657 if (error) { 658 uart_setreg(bas, REG_MCR, mcr); 659 uart_setreg(bas, REG_FCR, 0); 660 uart_barrier(bas); 661 goto describe; 662 } 663 664 /* 665 * We should have a sufficiently clean "pipe" to determine the 666 * size of the FIFOs. We send as much characters as is reasonable 667 * and wait for the the overflow bit in the LSR register to be 668 * asserted, counting the characters as we send them. Based on 669 * that count we know the FIFO size. 670 */ 671 do { 672 uart_setreg(bas, REG_DATA, 0); 673 uart_barrier(bas); 674 count++; 675 676 limit = 30; 677 lsr = 0; 678 /* 679 * LSR bits are cleared upon read, so we must accumulate 680 * them to be able to test LSR_OE below. 681 */ 682 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 683 --limit) 684 DELAY(delay); 685 if (limit == 0) { 686 ier = uart_getreg(bas, REG_IER) & 0xf0; 687 uart_setreg(bas, REG_IER, ier); 688 uart_setreg(bas, REG_MCR, mcr); 689 uart_setreg(bas, REG_FCR, 0); 690 uart_barrier(bas); 691 count = 0; 692 goto describe; 693 } 694 } while ((lsr & LSR_OE) == 0 && count < 130); 695 count--; 696 697 uart_setreg(bas, REG_MCR, mcr); 698 699 /* Reset FIFOs. */ 700 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 701 702 describe: 703 if (count >= 14 && count <= 16) { 704 sc->sc_rxfifosz = 16; 705 device_set_desc(sc->sc_dev, "16550 or compatible"); 706 } else if (count >= 28 && count <= 32) { 707 sc->sc_rxfifosz = 32; 708 device_set_desc(sc->sc_dev, "16650 or compatible"); 709 } else if (count >= 56 && count <= 64) { 710 sc->sc_rxfifosz = 64; 711 device_set_desc(sc->sc_dev, "16750 or compatible"); 712 } else if (count >= 112 && count <= 128) { 713 sc->sc_rxfifosz = 128; 714 device_set_desc(sc->sc_dev, "16950 or compatible"); 715 } else { 716 sc->sc_rxfifosz = 16; 717 device_set_desc(sc->sc_dev, 718 "Non-standard ns8250 class UART with FIFOs"); 719 } 720 721 /* 722 * Force the Tx FIFO size to 16 bytes for now. We don't program the 723 * Tx trigger. Also, we assume that all data has been sent when the 724 * interrupt happens. 725 */ 726 sc->sc_txfifosz = 16; 727 728#if 0 729 /* 730 * XXX there are some issues related to hardware flow control and 731 * it's likely that uart(4) is the cause. This basicly needs more 732 * investigation, but we avoid using for hardware flow control 733 * until then. 734 */ 735 /* 16650s or higher have automatic flow control. */ 736 if (sc->sc_rxfifosz > 16) { 737 sc->sc_hwiflow = 1; 738 sc->sc_hwoflow = 1; 739 } 740#endif 741 742 return (0); 743} 744 745static int 746ns8250_bus_receive(struct uart_softc *sc) 747{ 748 struct uart_bas *bas; 749 int xc; 750 uint8_t lsr; 751 752 bas = &sc->sc_bas; 753 uart_lock(sc->sc_hwmtx); 754 lsr = uart_getreg(bas, REG_LSR); 755 while (lsr & LSR_RXRDY) { 756 if (uart_rx_full(sc)) { 757 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 758 break; 759 } 760 xc = uart_getreg(bas, REG_DATA); 761 if (lsr & LSR_FE) 762 xc |= UART_STAT_FRAMERR; 763 if (lsr & LSR_PE) 764 xc |= UART_STAT_PARERR; 765 uart_rx_put(sc, xc); 766 lsr = uart_getreg(bas, REG_LSR); 767 } 768 /* Discard everything left in the Rx FIFO. */ 769 while (lsr & LSR_RXRDY) { 770 (void)uart_getreg(bas, REG_DATA); 771 uart_barrier(bas); 772 lsr = uart_getreg(bas, REG_LSR); 773 } 774 uart_unlock(sc->sc_hwmtx); 775 return (0); 776} 777 778static int 779ns8250_bus_setsig(struct uart_softc *sc, int sig) 780{ 781 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 782 struct uart_bas *bas; 783 uint32_t new, old; 784 785 bas = &sc->sc_bas; 786 do { 787 old = sc->sc_hwsig; 788 new = old; 789 if (sig & SER_DDTR) { 790 SIGCHG(sig & SER_DTR, new, SER_DTR, 791 SER_DDTR); 792 } 793 if (sig & SER_DRTS) { 794 SIGCHG(sig & SER_RTS, new, SER_RTS, 795 SER_DRTS); 796 } 797 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 798 uart_lock(sc->sc_hwmtx); 799 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 800 if (new & SER_DTR) 801 ns8250->mcr |= MCR_DTR; 802 if (new & SER_RTS) 803 ns8250->mcr |= MCR_RTS; 804 uart_setreg(bas, REG_MCR, ns8250->mcr); 805 uart_barrier(bas); 806 uart_unlock(sc->sc_hwmtx); 807 return (0); 808} 809 810static int 811ns8250_bus_transmit(struct uart_softc *sc) 812{ 813 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 814 struct uart_bas *bas; 815 int i; 816 817 bas = &sc->sc_bas; 818 uart_lock(sc->sc_hwmtx); 819 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 820 ; 821 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 822 uart_barrier(bas); 823 for (i = 0; i < sc->sc_txdatasz; i++) { 824 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 825 uart_barrier(bas); 826 } 827 sc->sc_txbusy = 1; 828 uart_unlock(sc->sc_hwmtx); 829 return (0); 830} 831