uart_dev_ns8250.c revision 168281
1139749Simp/*- 2119815Smarcel * Copyright (c) 2003 Marcel Moolenaar 3119815Smarcel * All rights reserved. 4119815Smarcel * 5119815Smarcel * Redistribution and use in source and binary forms, with or without 6119815Smarcel * modification, are permitted provided that the following conditions 7119815Smarcel * are met: 8119815Smarcel * 9119815Smarcel * 1. Redistributions of source code must retain the above copyright 10119815Smarcel * notice, this list of conditions and the following disclaimer. 11119815Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12119815Smarcel * notice, this list of conditions and the following disclaimer in the 13119815Smarcel * documentation and/or other materials provided with the distribution. 14119815Smarcel * 15119815Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16119815Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17119815Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18119815Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19119815Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20119815Smarcel * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21119815Smarcel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22119815Smarcel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23119815Smarcel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24119815Smarcel * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25119815Smarcel */ 26119815Smarcel 27119815Smarcel#include <sys/cdefs.h> 28119815Smarcel__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 168281 2007-04-02 22:00:22Z marcel $"); 29119815Smarcel 30119815Smarcel#include <sys/param.h> 31119815Smarcel#include <sys/systm.h> 32119815Smarcel#include <sys/bus.h> 33119815Smarcel#include <sys/conf.h> 34119815Smarcel#include <machine/bus.h> 35119815Smarcel 36119815Smarcel#include <dev/uart/uart.h> 37119815Smarcel#include <dev/uart/uart_cpu.h> 38119815Smarcel#include <dev/uart/uart_bus.h> 39119815Smarcel 40137949Smarcel#include <dev/ic/ns16550.h> 41137949Smarcel 42119815Smarcel#include "uart_if.h" 43119815Smarcel 44119815Smarcel#define DEFAULT_RCLK 1843200 45119815Smarcel 46119815Smarcel/* 47119815Smarcel * Clear pending interrupts. THRE is cleared by reading IIR. Data 48119815Smarcel * that may have been received gets lost here. 49119815Smarcel */ 50119815Smarcelstatic void 51119815Smarcelns8250_clrint(struct uart_bas *bas) 52119815Smarcel{ 53119815Smarcel uint8_t iir; 54119815Smarcel 55119815Smarcel iir = uart_getreg(bas, REG_IIR); 56119815Smarcel while ((iir & IIR_NOPEND) == 0) { 57119815Smarcel iir &= IIR_IMASK; 58119815Smarcel if (iir == IIR_RLS) 59119815Smarcel (void)uart_getreg(bas, REG_LSR); 60119815Smarcel else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 61119815Smarcel (void)uart_getreg(bas, REG_DATA); 62119815Smarcel else if (iir == IIR_MLSC) 63119815Smarcel (void)uart_getreg(bas, REG_MSR); 64119815Smarcel uart_barrier(bas); 65119815Smarcel iir = uart_getreg(bas, REG_IIR); 66119815Smarcel } 67119815Smarcel} 68119815Smarcel 69119815Smarcelstatic int 70119815Smarcelns8250_delay(struct uart_bas *bas) 71119815Smarcel{ 72119815Smarcel int divisor; 73119815Smarcel u_char lcr; 74119815Smarcel 75119815Smarcel lcr = uart_getreg(bas, REG_LCR); 76119815Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 77119815Smarcel uart_barrier(bas); 78158844Sbenno divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 79119815Smarcel uart_barrier(bas); 80119815Smarcel uart_setreg(bas, REG_LCR, lcr); 81119815Smarcel uart_barrier(bas); 82119815Smarcel 83119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 84168000Smarcel if (divisor <= 134) 85168000Smarcel return (16000000 * divisor / bas->rclk); 86168000Smarcel return (16000 * divisor / (bas->rclk / 1000)); 87119815Smarcel} 88119815Smarcel 89119815Smarcelstatic int 90119815Smarcelns8250_divisor(int rclk, int baudrate) 91119815Smarcel{ 92119815Smarcel int actual_baud, divisor; 93119815Smarcel int error; 94119815Smarcel 95119815Smarcel if (baudrate == 0) 96119815Smarcel return (0); 97119815Smarcel 98119815Smarcel divisor = (rclk / (baudrate << 3) + 1) >> 1; 99119815Smarcel if (divisor == 0 || divisor >= 65536) 100119815Smarcel return (0); 101119815Smarcel actual_baud = rclk / (divisor << 4); 102119815Smarcel 103119815Smarcel /* 10 times error in percent: */ 104119815Smarcel error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 105119815Smarcel 106119815Smarcel /* 3.0% maximum error tolerance: */ 107119815Smarcel if (error < -30 || error > 30) 108119815Smarcel return (0); 109119815Smarcel 110119815Smarcel return (divisor); 111119815Smarcel} 112119815Smarcel 113119815Smarcelstatic int 114119815Smarcelns8250_drain(struct uart_bas *bas, int what) 115119815Smarcel{ 116119815Smarcel int delay, limit; 117119815Smarcel 118119815Smarcel delay = ns8250_delay(bas); 119119815Smarcel 120119815Smarcel if (what & UART_DRAIN_TRANSMITTER) { 121119815Smarcel /* 122119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 123119815Smarcel * an infinite loop when the hardware is broken. Make the 124119815Smarcel * limit high enough to handle large FIFOs. 125119815Smarcel */ 126119815Smarcel limit = 10*1024; 127119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 128119815Smarcel DELAY(delay); 129119815Smarcel if (limit == 0) { 130119815Smarcel /* printf("ns8250: transmitter appears stuck... "); */ 131119815Smarcel return (EIO); 132119815Smarcel } 133119815Smarcel } 134119815Smarcel 135119815Smarcel if (what & UART_DRAIN_RECEIVER) { 136119815Smarcel /* 137119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 138119815Smarcel * an infinite loop when the hardware is broken. Make the 139119815Smarcel * limit high enough to handle large FIFOs and integrated 140119815Smarcel * UARTs. The HP rx2600 for example has 3 UARTs on the 141119815Smarcel * management board that tend to get a lot of data send 142119815Smarcel * to it when the UART is first activated. 143119815Smarcel */ 144119815Smarcel limit=10*4096; 145119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 146119815Smarcel (void)uart_getreg(bas, REG_DATA); 147119815Smarcel uart_barrier(bas); 148119815Smarcel DELAY(delay << 2); 149119815Smarcel } 150119815Smarcel if (limit == 0) { 151119815Smarcel /* printf("ns8250: receiver appears broken... "); */ 152119815Smarcel return (EIO); 153119815Smarcel } 154119815Smarcel } 155119815Smarcel 156119815Smarcel return (0); 157119815Smarcel} 158119815Smarcel 159119815Smarcel/* 160119815Smarcel * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 161119815Smarcel * drained. WARNING: this function clobbers the FIFO setting! 162119815Smarcel */ 163119815Smarcelstatic void 164119815Smarcelns8250_flush(struct uart_bas *bas, int what) 165119815Smarcel{ 166119815Smarcel uint8_t fcr; 167119815Smarcel 168119815Smarcel fcr = FCR_ENABLE; 169119815Smarcel if (what & UART_FLUSH_TRANSMITTER) 170119815Smarcel fcr |= FCR_XMT_RST; 171119815Smarcel if (what & UART_FLUSH_RECEIVER) 172119815Smarcel fcr |= FCR_RCV_RST; 173119815Smarcel uart_setreg(bas, REG_FCR, fcr); 174119815Smarcel uart_barrier(bas); 175119815Smarcel} 176119815Smarcel 177119815Smarcelstatic int 178119815Smarcelns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 179119815Smarcel int parity) 180119815Smarcel{ 181119815Smarcel int divisor; 182119815Smarcel uint8_t lcr; 183119815Smarcel 184119815Smarcel lcr = 0; 185119815Smarcel if (databits >= 8) 186119815Smarcel lcr |= LCR_8BITS; 187119815Smarcel else if (databits == 7) 188119815Smarcel lcr |= LCR_7BITS; 189119815Smarcel else if (databits == 6) 190119815Smarcel lcr |= LCR_6BITS; 191119815Smarcel else 192119815Smarcel lcr |= LCR_5BITS; 193119815Smarcel if (stopbits > 1) 194119815Smarcel lcr |= LCR_STOPB; 195119815Smarcel lcr |= parity << 3; 196119815Smarcel 197119815Smarcel /* Set baudrate. */ 198119815Smarcel if (baudrate > 0) { 199119815Smarcel divisor = ns8250_divisor(bas->rclk, baudrate); 200119815Smarcel if (divisor == 0) 201119815Smarcel return (EINVAL); 202157989Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 203157989Smarcel uart_barrier(bas); 204158844Sbenno uart_setreg(bas, REG_DLL, divisor & 0xff); 205158844Sbenno uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 206119815Smarcel uart_barrier(bas); 207119815Smarcel } 208119815Smarcel 209119815Smarcel /* Set LCR and clear DLAB. */ 210119815Smarcel uart_setreg(bas, REG_LCR, lcr); 211119815Smarcel uart_barrier(bas); 212119815Smarcel return (0); 213119815Smarcel} 214119815Smarcel 215119815Smarcel/* 216119815Smarcel * Low-level UART interface. 217119815Smarcel */ 218119815Smarcelstatic int ns8250_probe(struct uart_bas *bas); 219119815Smarcelstatic void ns8250_init(struct uart_bas *bas, int, int, int, int); 220119815Smarcelstatic void ns8250_term(struct uart_bas *bas); 221119815Smarcelstatic void ns8250_putc(struct uart_bas *bas, int); 222166100Smariusstatic int ns8250_rxready(struct uart_bas *bas); 223157380Smarcelstatic int ns8250_getc(struct uart_bas *bas, struct mtx *); 224119815Smarcel 225168281Smarcelstatic struct uart_ops uart_ns8250_ops = { 226119815Smarcel .probe = ns8250_probe, 227119815Smarcel .init = ns8250_init, 228119815Smarcel .term = ns8250_term, 229119815Smarcel .putc = ns8250_putc, 230166100Smarius .rxready = ns8250_rxready, 231119815Smarcel .getc = ns8250_getc, 232119815Smarcel}; 233119815Smarcel 234119815Smarcelstatic int 235119815Smarcelns8250_probe(struct uart_bas *bas) 236119815Smarcel{ 237158849Sbenno u_char val; 238119815Smarcel 239119815Smarcel /* Check known 0 bits that don't depend on DLAB. */ 240119815Smarcel val = uart_getreg(bas, REG_IIR); 241119815Smarcel if (val & 0x30) 242119815Smarcel return (ENXIO); 243119815Smarcel val = uart_getreg(bas, REG_MCR); 244119815Smarcel if (val & 0xe0) 245119815Smarcel return (ENXIO); 246119815Smarcel 247119815Smarcel return (0); 248119815Smarcel} 249119815Smarcel 250119815Smarcelstatic void 251119815Smarcelns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 252119815Smarcel int parity) 253119815Smarcel{ 254158844Sbenno u_char ier; 255119815Smarcel 256119815Smarcel if (bas->rclk == 0) 257119815Smarcel bas->rclk = DEFAULT_RCLK; 258119815Smarcel ns8250_param(bas, baudrate, databits, stopbits, parity); 259119815Smarcel 260119815Smarcel /* Disable all interrupt sources. */ 261158844Sbenno ier = uart_getreg(bas, REG_IER) & 0xf0; 262158844Sbenno uart_setreg(bas, REG_IER, ier); 263119815Smarcel uart_barrier(bas); 264119815Smarcel 265119815Smarcel /* Disable the FIFO (if present). */ 266119815Smarcel uart_setreg(bas, REG_FCR, 0); 267119815Smarcel uart_barrier(bas); 268119815Smarcel 269119815Smarcel /* Set RTS & DTR. */ 270119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 271119815Smarcel uart_barrier(bas); 272119815Smarcel 273119815Smarcel ns8250_clrint(bas); 274119815Smarcel} 275119815Smarcel 276119815Smarcelstatic void 277119815Smarcelns8250_term(struct uart_bas *bas) 278119815Smarcel{ 279119815Smarcel 280119815Smarcel /* Clear RTS & DTR. */ 281119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE); 282119815Smarcel uart_barrier(bas); 283119815Smarcel} 284119815Smarcel 285119815Smarcelstatic void 286119815Smarcelns8250_putc(struct uart_bas *bas, int c) 287119815Smarcel{ 288119815Smarcel int delay, limit; 289119815Smarcel 290119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 291119815Smarcel delay = ns8250_delay(bas); 292119815Smarcel 293119815Smarcel limit = 20; 294119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 295119815Smarcel DELAY(delay); 296119815Smarcel uart_setreg(bas, REG_DATA, c); 297127742Smarcel uart_barrier(bas); 298119815Smarcel limit = 40; 299119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 300119815Smarcel DELAY(delay); 301119815Smarcel} 302119815Smarcel 303119815Smarcelstatic int 304166100Smariusns8250_rxready(struct uart_bas *bas) 305119815Smarcel{ 306119815Smarcel 307166100Smarius return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 308119815Smarcel} 309119815Smarcel 310119815Smarcelstatic int 311157380Smarcelns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 312119815Smarcel{ 313157380Smarcel int c, delay; 314119815Smarcel 315157380Smarcel uart_lock(hwmtx); 316157380Smarcel 317119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 318119815Smarcel delay = ns8250_delay(bas); 319119815Smarcel 320157380Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 321157380Smarcel uart_unlock(hwmtx); 322119815Smarcel DELAY(delay); 323157380Smarcel uart_lock(hwmtx); 324157380Smarcel } 325157380Smarcel 326157380Smarcel c = uart_getreg(bas, REG_DATA); 327157380Smarcel 328157380Smarcel uart_unlock(hwmtx); 329157380Smarcel 330157380Smarcel return (c); 331119815Smarcel} 332119815Smarcel 333119815Smarcel/* 334119815Smarcel * High-level UART interface. 335119815Smarcel */ 336119815Smarcelstruct ns8250_softc { 337119815Smarcel struct uart_softc base; 338119815Smarcel uint8_t fcr; 339119815Smarcel uint8_t ier; 340119815Smarcel uint8_t mcr; 341119815Smarcel}; 342119815Smarcel 343119815Smarcelstatic int ns8250_bus_attach(struct uart_softc *); 344119815Smarcelstatic int ns8250_bus_detach(struct uart_softc *); 345119815Smarcelstatic int ns8250_bus_flush(struct uart_softc *, int); 346119815Smarcelstatic int ns8250_bus_getsig(struct uart_softc *); 347119815Smarcelstatic int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 348119815Smarcelstatic int ns8250_bus_ipend(struct uart_softc *); 349119815Smarcelstatic int ns8250_bus_param(struct uart_softc *, int, int, int, int); 350119815Smarcelstatic int ns8250_bus_probe(struct uart_softc *); 351119815Smarcelstatic int ns8250_bus_receive(struct uart_softc *); 352119815Smarcelstatic int ns8250_bus_setsig(struct uart_softc *, int); 353119815Smarcelstatic int ns8250_bus_transmit(struct uart_softc *); 354119815Smarcel 355119815Smarcelstatic kobj_method_t ns8250_methods[] = { 356119815Smarcel KOBJMETHOD(uart_attach, ns8250_bus_attach), 357119815Smarcel KOBJMETHOD(uart_detach, ns8250_bus_detach), 358119815Smarcel KOBJMETHOD(uart_flush, ns8250_bus_flush), 359119815Smarcel KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 360119815Smarcel KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 361119815Smarcel KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 362119815Smarcel KOBJMETHOD(uart_param, ns8250_bus_param), 363119815Smarcel KOBJMETHOD(uart_probe, ns8250_bus_probe), 364119815Smarcel KOBJMETHOD(uart_receive, ns8250_bus_receive), 365119815Smarcel KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 366119815Smarcel KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 367119815Smarcel { 0, 0 } 368119815Smarcel}; 369119815Smarcel 370119815Smarcelstruct uart_class uart_ns8250_class = { 371168281Smarcel "ns8250", 372119815Smarcel ns8250_methods, 373119815Smarcel sizeof(struct ns8250_softc), 374168281Smarcel .uc_ops = &uart_ns8250_ops, 375119815Smarcel .uc_range = 8, 376119815Smarcel .uc_rclk = DEFAULT_RCLK 377119815Smarcel}; 378119815Smarcel 379119815Smarcel#define SIGCHG(c, i, s, d) \ 380119815Smarcel if (c) { \ 381119815Smarcel i |= (i & s) ? s : s | d; \ 382119815Smarcel } else { \ 383119815Smarcel i = (i & s) ? (i & ~s) | d : i; \ 384119815Smarcel } 385119815Smarcel 386119815Smarcelstatic int 387119815Smarcelns8250_bus_attach(struct uart_softc *sc) 388119815Smarcel{ 389119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 390119815Smarcel struct uart_bas *bas; 391119815Smarcel 392119815Smarcel bas = &sc->sc_bas; 393119815Smarcel 394119815Smarcel ns8250->mcr = uart_getreg(bas, REG_MCR); 395119815Smarcel ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH; 396119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 397119815Smarcel uart_barrier(bas); 398119815Smarcel ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 399119815Smarcel 400119815Smarcel if (ns8250->mcr & MCR_DTR) 401131043Sphk sc->sc_hwsig |= SER_DTR; 402119815Smarcel if (ns8250->mcr & MCR_RTS) 403131043Sphk sc->sc_hwsig |= SER_RTS; 404119815Smarcel ns8250_bus_getsig(sc); 405119815Smarcel 406119815Smarcel ns8250_clrint(bas); 407158844Sbenno ns8250->ier = uart_getreg(bas, REG_IER) & 0xf0; 408158844Sbenno ns8250->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY; 409119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier); 410119815Smarcel uart_barrier(bas); 411119815Smarcel return (0); 412119815Smarcel} 413119815Smarcel 414119815Smarcelstatic int 415119815Smarcelns8250_bus_detach(struct uart_softc *sc) 416119815Smarcel{ 417119815Smarcel struct uart_bas *bas; 418158844Sbenno u_char ier; 419119815Smarcel 420119815Smarcel bas = &sc->sc_bas; 421158844Sbenno ier = uart_getreg(bas, REG_IER) & 0xf0; 422158844Sbenno uart_setreg(bas, REG_IER, ier); 423119815Smarcel uart_barrier(bas); 424119815Smarcel ns8250_clrint(bas); 425119815Smarcel return (0); 426119815Smarcel} 427119815Smarcel 428119815Smarcelstatic int 429119815Smarcelns8250_bus_flush(struct uart_softc *sc, int what) 430119815Smarcel{ 431119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 432119815Smarcel struct uart_bas *bas; 433120143Smarcel int error; 434119815Smarcel 435119815Smarcel bas = &sc->sc_bas; 436157300Smarcel uart_lock(sc->sc_hwmtx); 437157418Smarcel if (sc->sc_rxfifosz > 1) { 438119815Smarcel ns8250_flush(bas, what); 439119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 440119815Smarcel uart_barrier(bas); 441120143Smarcel error = 0; 442120143Smarcel } else 443120143Smarcel error = ns8250_drain(bas, what); 444157300Smarcel uart_unlock(sc->sc_hwmtx); 445120143Smarcel return (error); 446119815Smarcel} 447119815Smarcel 448119815Smarcelstatic int 449119815Smarcelns8250_bus_getsig(struct uart_softc *sc) 450119815Smarcel{ 451119815Smarcel uint32_t new, old, sig; 452119815Smarcel uint8_t msr; 453119815Smarcel 454119815Smarcel do { 455119815Smarcel old = sc->sc_hwsig; 456119815Smarcel sig = old; 457157300Smarcel uart_lock(sc->sc_hwmtx); 458119815Smarcel msr = uart_getreg(&sc->sc_bas, REG_MSR); 459157300Smarcel uart_unlock(sc->sc_hwmtx); 460131043Sphk SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 461131043Sphk SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 462131043Sphk SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 463131043Sphk SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 464155973Smarcel new = sig & ~SER_MASK_DELTA; 465119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 466119815Smarcel return (sig); 467119815Smarcel} 468119815Smarcel 469119815Smarcelstatic int 470119815Smarcelns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 471119815Smarcel{ 472119815Smarcel struct uart_bas *bas; 473137709Smarcel int baudrate, divisor, error; 474120022Smarcel uint8_t efr, lcr; 475119815Smarcel 476119815Smarcel bas = &sc->sc_bas; 477120143Smarcel error = 0; 478157300Smarcel uart_lock(sc->sc_hwmtx); 479119815Smarcel switch (request) { 480119815Smarcel case UART_IOCTL_BREAK: 481119815Smarcel lcr = uart_getreg(bas, REG_LCR); 482119815Smarcel if (data) 483119815Smarcel lcr |= LCR_SBREAK; 484119815Smarcel else 485119815Smarcel lcr &= ~LCR_SBREAK; 486119815Smarcel uart_setreg(bas, REG_LCR, lcr); 487119815Smarcel uart_barrier(bas); 488119815Smarcel break; 489120022Smarcel case UART_IOCTL_IFLOW: 490120022Smarcel lcr = uart_getreg(bas, REG_LCR); 491120022Smarcel uart_barrier(bas); 492120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 493120022Smarcel uart_barrier(bas); 494120022Smarcel efr = uart_getreg(bas, REG_EFR); 495120022Smarcel if (data) 496120022Smarcel efr |= EFR_RTS; 497120022Smarcel else 498120022Smarcel efr &= ~EFR_RTS; 499120022Smarcel uart_setreg(bas, REG_EFR, efr); 500120022Smarcel uart_barrier(bas); 501120022Smarcel uart_setreg(bas, REG_LCR, lcr); 502120022Smarcel uart_barrier(bas); 503120022Smarcel break; 504120022Smarcel case UART_IOCTL_OFLOW: 505120022Smarcel lcr = uart_getreg(bas, REG_LCR); 506120022Smarcel uart_barrier(bas); 507120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 508120022Smarcel uart_barrier(bas); 509120022Smarcel efr = uart_getreg(bas, REG_EFR); 510120022Smarcel if (data) 511120022Smarcel efr |= EFR_CTS; 512120022Smarcel else 513120022Smarcel efr &= ~EFR_CTS; 514120022Smarcel uart_setreg(bas, REG_EFR, efr); 515120022Smarcel uart_barrier(bas); 516120022Smarcel uart_setreg(bas, REG_LCR, lcr); 517120022Smarcel uart_barrier(bas); 518120022Smarcel break; 519137707Smarcel case UART_IOCTL_BAUD: 520137707Smarcel lcr = uart_getreg(bas, REG_LCR); 521137707Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 522137707Smarcel uart_barrier(bas); 523158844Sbenno divisor = uart_getreg(bas, REG_DLL) | 524158844Sbenno (uart_getreg(bas, REG_DLH) << 8); 525137707Smarcel uart_barrier(bas); 526137707Smarcel uart_setreg(bas, REG_LCR, lcr); 527137707Smarcel uart_barrier(bas); 528137709Smarcel baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 529137709Smarcel if (baudrate > 0) 530137709Smarcel *(int*)data = baudrate; 531137709Smarcel else 532137709Smarcel error = ENXIO; 533137707Smarcel break; 534119815Smarcel default: 535120143Smarcel error = EINVAL; 536120143Smarcel break; 537119815Smarcel } 538157300Smarcel uart_unlock(sc->sc_hwmtx); 539120143Smarcel return (error); 540119815Smarcel} 541119815Smarcel 542119815Smarcelstatic int 543119815Smarcelns8250_bus_ipend(struct uart_softc *sc) 544119815Smarcel{ 545119815Smarcel struct uart_bas *bas; 546119815Smarcel int ipend; 547119815Smarcel uint8_t iir, lsr; 548119815Smarcel 549119815Smarcel bas = &sc->sc_bas; 550157300Smarcel uart_lock(sc->sc_hwmtx); 551119815Smarcel iir = uart_getreg(bas, REG_IIR); 552120143Smarcel if (iir & IIR_NOPEND) { 553157300Smarcel uart_unlock(sc->sc_hwmtx); 554119815Smarcel return (0); 555120143Smarcel } 556119815Smarcel ipend = 0; 557119815Smarcel if (iir & IIR_RXRDY) { 558119815Smarcel lsr = uart_getreg(bas, REG_LSR); 559157300Smarcel uart_unlock(sc->sc_hwmtx); 560119815Smarcel if (lsr & LSR_OE) 561155971Smarcel ipend |= SER_INT_OVERRUN; 562119815Smarcel if (lsr & LSR_BI) 563155971Smarcel ipend |= SER_INT_BREAK; 564119815Smarcel if (lsr & LSR_RXRDY) 565155971Smarcel ipend |= SER_INT_RXREADY; 566119815Smarcel } else { 567157300Smarcel uart_unlock(sc->sc_hwmtx); 568119815Smarcel if (iir & IIR_TXRDY) 569155971Smarcel ipend |= SER_INT_TXIDLE; 570119815Smarcel else 571155971Smarcel ipend |= SER_INT_SIGCHG; 572119815Smarcel } 573119815Smarcel return ((sc->sc_leaving) ? 0 : ipend); 574119815Smarcel} 575119815Smarcel 576119815Smarcelstatic int 577119815Smarcelns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 578119815Smarcel int stopbits, int parity) 579119815Smarcel{ 580119815Smarcel struct uart_bas *bas; 581120143Smarcel int error; 582119815Smarcel 583119815Smarcel bas = &sc->sc_bas; 584157300Smarcel uart_lock(sc->sc_hwmtx); 585120143Smarcel error = ns8250_param(bas, baudrate, databits, stopbits, parity); 586157300Smarcel uart_unlock(sc->sc_hwmtx); 587120143Smarcel return (error); 588119815Smarcel} 589119815Smarcel 590119815Smarcelstatic int 591119815Smarcelns8250_bus_probe(struct uart_softc *sc) 592119815Smarcel{ 593119815Smarcel struct uart_bas *bas; 594119815Smarcel int count, delay, error, limit; 595158844Sbenno uint8_t lsr, mcr, ier; 596119815Smarcel 597119815Smarcel bas = &sc->sc_bas; 598119815Smarcel 599119815Smarcel error = ns8250_probe(bas); 600119815Smarcel if (error) 601119815Smarcel return (error); 602119815Smarcel 603119815Smarcel mcr = MCR_IE; 604119815Smarcel if (sc->sc_sysdev == NULL) { 605119815Smarcel /* By using ns8250_init() we also set DTR and RTS. */ 606158069Smarcel ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 607119815Smarcel } else 608119815Smarcel mcr |= MCR_DTR | MCR_RTS; 609119815Smarcel 610119815Smarcel error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 611119815Smarcel if (error) 612119815Smarcel return (error); 613119815Smarcel 614119815Smarcel /* 615119815Smarcel * Set loopback mode. This avoids having garbage on the wire and 616119815Smarcel * also allows us send and receive data. We set DTR and RTS to 617119815Smarcel * avoid the possibility that automatic flow-control prevents 618129757Stmm * any data from being sent. 619119815Smarcel */ 620129757Stmm uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 621119815Smarcel uart_barrier(bas); 622119815Smarcel 623119815Smarcel /* 624119815Smarcel * Enable FIFOs. And check that the UART has them. If not, we're 625129757Stmm * done. Since this is the first time we enable the FIFOs, we reset 626129757Stmm * them. 627119815Smarcel */ 628119815Smarcel uart_setreg(bas, REG_FCR, FCR_ENABLE); 629119815Smarcel uart_barrier(bas); 630157418Smarcel if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 631119815Smarcel /* 632119815Smarcel * NS16450 or INS8250. We don't bother to differentiate 633119815Smarcel * between them. They're too old to be interesting. 634119815Smarcel */ 635119815Smarcel uart_setreg(bas, REG_MCR, mcr); 636119815Smarcel uart_barrier(bas); 637157418Smarcel sc->sc_rxfifosz = sc->sc_txfifosz = 1; 638119815Smarcel device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 639119815Smarcel return (0); 640119815Smarcel } 641119815Smarcel 642129757Stmm uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 643119815Smarcel uart_barrier(bas); 644119815Smarcel 645119815Smarcel count = 0; 646119815Smarcel delay = ns8250_delay(bas); 647119815Smarcel 648119815Smarcel /* We have FIFOs. Drain the transmitter and receiver. */ 649119815Smarcel error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 650119815Smarcel if (error) { 651119815Smarcel uart_setreg(bas, REG_MCR, mcr); 652119815Smarcel uart_setreg(bas, REG_FCR, 0); 653119815Smarcel uart_barrier(bas); 654119815Smarcel goto describe; 655119815Smarcel } 656119815Smarcel 657119815Smarcel /* 658119815Smarcel * We should have a sufficiently clean "pipe" to determine the 659119815Smarcel * size of the FIFOs. We send as much characters as is reasonable 660129757Stmm * and wait for the the overflow bit in the LSR register to be 661129757Stmm * asserted, counting the characters as we send them. Based on 662129757Stmm * that count we know the FIFO size. 663119815Smarcel */ 664129757Stmm do { 665119815Smarcel uart_setreg(bas, REG_DATA, 0); 666119815Smarcel uart_barrier(bas); 667119815Smarcel count++; 668119815Smarcel 669119815Smarcel limit = 30; 670129757Stmm lsr = 0; 671129757Stmm /* 672129757Stmm * LSR bits are cleared upon read, so we must accumulate 673129757Stmm * them to be able to test LSR_OE below. 674129757Stmm */ 675129757Stmm while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 676129757Stmm --limit) 677119815Smarcel DELAY(delay); 678119815Smarcel if (limit == 0) { 679158844Sbenno ier = uart_getreg(bas, REG_IER) & 0xf0; 680158844Sbenno uart_setreg(bas, REG_IER, ier); 681119815Smarcel uart_setreg(bas, REG_MCR, mcr); 682119815Smarcel uart_setreg(bas, REG_FCR, 0); 683119815Smarcel uart_barrier(bas); 684119815Smarcel count = 0; 685119815Smarcel goto describe; 686119815Smarcel } 687132650Smarcel } while ((lsr & LSR_OE) == 0 && count < 130); 688129757Stmm count--; 689119815Smarcel 690119815Smarcel uart_setreg(bas, REG_MCR, mcr); 691119815Smarcel 692119815Smarcel /* Reset FIFOs. */ 693119815Smarcel ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 694119815Smarcel 695119815Smarcel describe: 696129757Stmm if (count >= 14 && count <= 16) { 697119815Smarcel sc->sc_rxfifosz = 16; 698119815Smarcel device_set_desc(sc->sc_dev, "16550 or compatible"); 699129757Stmm } else if (count >= 28 && count <= 32) { 700119815Smarcel sc->sc_rxfifosz = 32; 701119815Smarcel device_set_desc(sc->sc_dev, "16650 or compatible"); 702129757Stmm } else if (count >= 56 && count <= 64) { 703119815Smarcel sc->sc_rxfifosz = 64; 704119815Smarcel device_set_desc(sc->sc_dev, "16750 or compatible"); 705129757Stmm } else if (count >= 112 && count <= 128) { 706119815Smarcel sc->sc_rxfifosz = 128; 707119815Smarcel device_set_desc(sc->sc_dev, "16950 or compatible"); 708119815Smarcel } else { 709119943Smarcel sc->sc_rxfifosz = 16; 710119815Smarcel device_set_desc(sc->sc_dev, 711119815Smarcel "Non-standard ns8250 class UART with FIFOs"); 712119815Smarcel } 713119815Smarcel 714119815Smarcel /* 715119815Smarcel * Force the Tx FIFO size to 16 bytes for now. We don't program the 716119815Smarcel * Tx trigger. Also, we assume that all data has been sent when the 717119815Smarcel * interrupt happens. 718119815Smarcel */ 719119815Smarcel sc->sc_txfifosz = 16; 720119815Smarcel 721133220Smarcel#if 0 722133220Smarcel /* 723133220Smarcel * XXX there are some issues related to hardware flow control and 724133220Smarcel * it's likely that uart(4) is the cause. This basicly needs more 725133220Smarcel * investigation, but we avoid using for hardware flow control 726133220Smarcel * until then. 727133220Smarcel */ 728120022Smarcel /* 16650s or higher have automatic flow control. */ 729120022Smarcel if (sc->sc_rxfifosz > 16) { 730120022Smarcel sc->sc_hwiflow = 1; 731120022Smarcel sc->sc_hwoflow = 1; 732120022Smarcel } 733133220Smarcel#endif 734120022Smarcel 735119815Smarcel return (0); 736119815Smarcel} 737119815Smarcel 738119815Smarcelstatic int 739119815Smarcelns8250_bus_receive(struct uart_softc *sc) 740119815Smarcel{ 741119815Smarcel struct uart_bas *bas; 742119815Smarcel int xc; 743119815Smarcel uint8_t lsr; 744119815Smarcel 745119815Smarcel bas = &sc->sc_bas; 746157300Smarcel uart_lock(sc->sc_hwmtx); 747120146Smarcel lsr = uart_getreg(bas, REG_LSR); 748120146Smarcel while (lsr & LSR_RXRDY) { 749120146Smarcel if (uart_rx_full(sc)) { 750120146Smarcel sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 751119815Smarcel break; 752120146Smarcel } 753119815Smarcel xc = uart_getreg(bas, REG_DATA); 754119815Smarcel if (lsr & LSR_FE) 755119815Smarcel xc |= UART_STAT_FRAMERR; 756119815Smarcel if (lsr & LSR_PE) 757119815Smarcel xc |= UART_STAT_PARERR; 758119815Smarcel uart_rx_put(sc, xc); 759120146Smarcel lsr = uart_getreg(bas, REG_LSR); 760119815Smarcel } 761120146Smarcel /* Discard everything left in the Rx FIFO. */ 762120146Smarcel while (lsr & LSR_RXRDY) { 763120146Smarcel (void)uart_getreg(bas, REG_DATA); 764120146Smarcel uart_barrier(bas); 765120146Smarcel lsr = uart_getreg(bas, REG_LSR); 766120146Smarcel } 767157300Smarcel uart_unlock(sc->sc_hwmtx); 768119815Smarcel return (0); 769119815Smarcel} 770119815Smarcel 771119815Smarcelstatic int 772119815Smarcelns8250_bus_setsig(struct uart_softc *sc, int sig) 773119815Smarcel{ 774119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 775119815Smarcel struct uart_bas *bas; 776119815Smarcel uint32_t new, old; 777119815Smarcel 778119815Smarcel bas = &sc->sc_bas; 779119815Smarcel do { 780119815Smarcel old = sc->sc_hwsig; 781119815Smarcel new = old; 782131043Sphk if (sig & SER_DDTR) { 783131043Sphk SIGCHG(sig & SER_DTR, new, SER_DTR, 784131043Sphk SER_DDTR); 785119815Smarcel } 786131043Sphk if (sig & SER_DRTS) { 787131043Sphk SIGCHG(sig & SER_RTS, new, SER_RTS, 788131043Sphk SER_DRTS); 789119815Smarcel } 790119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 791157300Smarcel uart_lock(sc->sc_hwmtx); 792119815Smarcel ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 793131043Sphk if (new & SER_DTR) 794119815Smarcel ns8250->mcr |= MCR_DTR; 795131043Sphk if (new & SER_RTS) 796119815Smarcel ns8250->mcr |= MCR_RTS; 797119815Smarcel uart_setreg(bas, REG_MCR, ns8250->mcr); 798119815Smarcel uart_barrier(bas); 799157300Smarcel uart_unlock(sc->sc_hwmtx); 800119815Smarcel return (0); 801119815Smarcel} 802119815Smarcel 803119815Smarcelstatic int 804119815Smarcelns8250_bus_transmit(struct uart_softc *sc) 805119815Smarcel{ 806119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 807119815Smarcel struct uart_bas *bas; 808119815Smarcel int i; 809119815Smarcel 810119815Smarcel bas = &sc->sc_bas; 811157300Smarcel uart_lock(sc->sc_hwmtx); 812119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 813119815Smarcel ; 814119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 815119815Smarcel uart_barrier(bas); 816119815Smarcel for (i = 0; i < sc->sc_txdatasz; i++) { 817119815Smarcel uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 818119815Smarcel uart_barrier(bas); 819119815Smarcel } 820119815Smarcel sc->sc_txbusy = 1; 821157300Smarcel uart_unlock(sc->sc_hwmtx); 822119815Smarcel return (0); 823119815Smarcel} 824