uart_dev_ns8250.c revision 158844
1139749Simp/*- 2119815Smarcel * Copyright (c) 2003 Marcel Moolenaar 3119815Smarcel * All rights reserved. 4119815Smarcel * 5119815Smarcel * Redistribution and use in source and binary forms, with or without 6119815Smarcel * modification, are permitted provided that the following conditions 7119815Smarcel * are met: 8119815Smarcel * 9119815Smarcel * 1. Redistributions of source code must retain the above copyright 10119815Smarcel * notice, this list of conditions and the following disclaimer. 11119815Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12119815Smarcel * notice, this list of conditions and the following disclaimer in the 13119815Smarcel * documentation and/or other materials provided with the distribution. 14119815Smarcel * 15119815Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16119815Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17119815Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18119815Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19119815Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20119815Smarcel * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21119815Smarcel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22119815Smarcel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23119815Smarcel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24119815Smarcel * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25119815Smarcel */ 26119815Smarcel 27119815Smarcel#include <sys/cdefs.h> 28119815Smarcel__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 158844 2006-05-23 00:41:12Z benno $"); 29119815Smarcel 30119815Smarcel#include <sys/param.h> 31119815Smarcel#include <sys/systm.h> 32119815Smarcel#include <sys/bus.h> 33119815Smarcel#include <sys/conf.h> 34119815Smarcel#include <machine/bus.h> 35119815Smarcel 36119815Smarcel#include <dev/uart/uart.h> 37119815Smarcel#include <dev/uart/uart_cpu.h> 38119815Smarcel#include <dev/uart/uart_bus.h> 39119815Smarcel 40137949Smarcel#include <dev/ic/ns16550.h> 41137949Smarcel 42119815Smarcel#include "uart_if.h" 43119815Smarcel 44119815Smarcel#define DEFAULT_RCLK 1843200 45119815Smarcel 46119815Smarcel/* 47119815Smarcel * Clear pending interrupts. THRE is cleared by reading IIR. Data 48119815Smarcel * that may have been received gets lost here. 49119815Smarcel */ 50119815Smarcelstatic void 51119815Smarcelns8250_clrint(struct uart_bas *bas) 52119815Smarcel{ 53119815Smarcel uint8_t iir; 54119815Smarcel 55119815Smarcel iir = uart_getreg(bas, REG_IIR); 56119815Smarcel while ((iir & IIR_NOPEND) == 0) { 57119815Smarcel iir &= IIR_IMASK; 58119815Smarcel if (iir == IIR_RLS) 59119815Smarcel (void)uart_getreg(bas, REG_LSR); 60119815Smarcel else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 61119815Smarcel (void)uart_getreg(bas, REG_DATA); 62119815Smarcel else if (iir == IIR_MLSC) 63119815Smarcel (void)uart_getreg(bas, REG_MSR); 64119815Smarcel uart_barrier(bas); 65119815Smarcel iir = uart_getreg(bas, REG_IIR); 66119815Smarcel } 67119815Smarcel} 68119815Smarcel 69119815Smarcelstatic int 70119815Smarcelns8250_delay(struct uart_bas *bas) 71119815Smarcel{ 72119815Smarcel int divisor; 73119815Smarcel u_char lcr; 74119815Smarcel 75119815Smarcel lcr = uart_getreg(bas, REG_LCR); 76119815Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 77119815Smarcel uart_barrier(bas); 78158844Sbenno divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 79119815Smarcel uart_barrier(bas); 80119815Smarcel uart_setreg(bas, REG_LCR, lcr); 81119815Smarcel uart_barrier(bas); 82119815Smarcel 83119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 84119815Smarcel return (16000000 * divisor / bas->rclk); 85119815Smarcel} 86119815Smarcel 87119815Smarcelstatic int 88119815Smarcelns8250_divisor(int rclk, int baudrate) 89119815Smarcel{ 90119815Smarcel int actual_baud, divisor; 91119815Smarcel int error; 92119815Smarcel 93119815Smarcel if (baudrate == 0) 94119815Smarcel return (0); 95119815Smarcel 96119815Smarcel divisor = (rclk / (baudrate << 3) + 1) >> 1; 97119815Smarcel if (divisor == 0 || divisor >= 65536) 98119815Smarcel return (0); 99119815Smarcel actual_baud = rclk / (divisor << 4); 100119815Smarcel 101119815Smarcel /* 10 times error in percent: */ 102119815Smarcel error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 103119815Smarcel 104119815Smarcel /* 3.0% maximum error tolerance: */ 105119815Smarcel if (error < -30 || error > 30) 106119815Smarcel return (0); 107119815Smarcel 108119815Smarcel return (divisor); 109119815Smarcel} 110119815Smarcel 111119815Smarcelstatic int 112119815Smarcelns8250_drain(struct uart_bas *bas, int what) 113119815Smarcel{ 114119815Smarcel int delay, limit; 115119815Smarcel 116119815Smarcel delay = ns8250_delay(bas); 117119815Smarcel 118119815Smarcel if (what & UART_DRAIN_TRANSMITTER) { 119119815Smarcel /* 120119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 121119815Smarcel * an infinite loop when the hardware is broken. Make the 122119815Smarcel * limit high enough to handle large FIFOs. 123119815Smarcel */ 124119815Smarcel limit = 10*1024; 125119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 126119815Smarcel DELAY(delay); 127119815Smarcel if (limit == 0) { 128119815Smarcel /* printf("ns8250: transmitter appears stuck... "); */ 129119815Smarcel return (EIO); 130119815Smarcel } 131119815Smarcel } 132119815Smarcel 133119815Smarcel if (what & UART_DRAIN_RECEIVER) { 134119815Smarcel /* 135119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 136119815Smarcel * an infinite loop when the hardware is broken. Make the 137119815Smarcel * limit high enough to handle large FIFOs and integrated 138119815Smarcel * UARTs. The HP rx2600 for example has 3 UARTs on the 139119815Smarcel * management board that tend to get a lot of data send 140119815Smarcel * to it when the UART is first activated. 141119815Smarcel */ 142119815Smarcel limit=10*4096; 143119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 144119815Smarcel (void)uart_getreg(bas, REG_DATA); 145119815Smarcel uart_barrier(bas); 146119815Smarcel DELAY(delay << 2); 147119815Smarcel } 148119815Smarcel if (limit == 0) { 149119815Smarcel /* printf("ns8250: receiver appears broken... "); */ 150119815Smarcel return (EIO); 151119815Smarcel } 152119815Smarcel } 153119815Smarcel 154119815Smarcel return (0); 155119815Smarcel} 156119815Smarcel 157119815Smarcel/* 158119815Smarcel * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 159119815Smarcel * drained. WARNING: this function clobbers the FIFO setting! 160119815Smarcel */ 161119815Smarcelstatic void 162119815Smarcelns8250_flush(struct uart_bas *bas, int what) 163119815Smarcel{ 164119815Smarcel uint8_t fcr; 165119815Smarcel 166119815Smarcel fcr = FCR_ENABLE; 167119815Smarcel if (what & UART_FLUSH_TRANSMITTER) 168119815Smarcel fcr |= FCR_XMT_RST; 169119815Smarcel if (what & UART_FLUSH_RECEIVER) 170119815Smarcel fcr |= FCR_RCV_RST; 171119815Smarcel uart_setreg(bas, REG_FCR, fcr); 172119815Smarcel uart_barrier(bas); 173119815Smarcel} 174119815Smarcel 175119815Smarcelstatic int 176119815Smarcelns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 177119815Smarcel int parity) 178119815Smarcel{ 179119815Smarcel int divisor; 180119815Smarcel uint8_t lcr; 181119815Smarcel 182119815Smarcel lcr = 0; 183119815Smarcel if (databits >= 8) 184119815Smarcel lcr |= LCR_8BITS; 185119815Smarcel else if (databits == 7) 186119815Smarcel lcr |= LCR_7BITS; 187119815Smarcel else if (databits == 6) 188119815Smarcel lcr |= LCR_6BITS; 189119815Smarcel else 190119815Smarcel lcr |= LCR_5BITS; 191119815Smarcel if (stopbits > 1) 192119815Smarcel lcr |= LCR_STOPB; 193119815Smarcel lcr |= parity << 3; 194119815Smarcel 195119815Smarcel /* Set baudrate. */ 196119815Smarcel if (baudrate > 0) { 197119815Smarcel divisor = ns8250_divisor(bas->rclk, baudrate); 198119815Smarcel if (divisor == 0) 199119815Smarcel return (EINVAL); 200157989Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 201157989Smarcel uart_barrier(bas); 202158844Sbenno uart_setreg(bas, REG_DLL, divisor & 0xff); 203158844Sbenno uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 204119815Smarcel uart_barrier(bas); 205119815Smarcel } 206119815Smarcel 207119815Smarcel /* Set LCR and clear DLAB. */ 208119815Smarcel uart_setreg(bas, REG_LCR, lcr); 209119815Smarcel uart_barrier(bas); 210119815Smarcel return (0); 211119815Smarcel} 212119815Smarcel 213119815Smarcel/* 214119815Smarcel * Low-level UART interface. 215119815Smarcel */ 216119815Smarcelstatic int ns8250_probe(struct uart_bas *bas); 217119815Smarcelstatic void ns8250_init(struct uart_bas *bas, int, int, int, int); 218119815Smarcelstatic void ns8250_term(struct uart_bas *bas); 219119815Smarcelstatic void ns8250_putc(struct uart_bas *bas, int); 220119815Smarcelstatic int ns8250_poll(struct uart_bas *bas); 221157380Smarcelstatic int ns8250_getc(struct uart_bas *bas, struct mtx *); 222119815Smarcel 223119815Smarcelstruct uart_ops uart_ns8250_ops = { 224119815Smarcel .probe = ns8250_probe, 225119815Smarcel .init = ns8250_init, 226119815Smarcel .term = ns8250_term, 227119815Smarcel .putc = ns8250_putc, 228119815Smarcel .poll = ns8250_poll, 229119815Smarcel .getc = ns8250_getc, 230119815Smarcel}; 231119815Smarcel 232119815Smarcelstatic int 233119815Smarcelns8250_probe(struct uart_bas *bas) 234119815Smarcel{ 235119815Smarcel u_char lcr, val; 236119815Smarcel 237119815Smarcel /* Check known 0 bits that don't depend on DLAB. */ 238119815Smarcel val = uart_getreg(bas, REG_IIR); 239119815Smarcel if (val & 0x30) 240119815Smarcel return (ENXIO); 241119815Smarcel val = uart_getreg(bas, REG_MCR); 242119815Smarcel if (val & 0xe0) 243119815Smarcel return (ENXIO); 244119815Smarcel 245119815Smarcel return (0); 246119815Smarcel} 247119815Smarcel 248119815Smarcelstatic void 249119815Smarcelns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 250119815Smarcel int parity) 251119815Smarcel{ 252158844Sbenno u_char ier; 253119815Smarcel 254119815Smarcel if (bas->rclk == 0) 255119815Smarcel bas->rclk = DEFAULT_RCLK; 256119815Smarcel ns8250_param(bas, baudrate, databits, stopbits, parity); 257119815Smarcel 258119815Smarcel /* Disable all interrupt sources. */ 259158844Sbenno ier = uart_getreg(bas, REG_IER) & 0xf0; 260158844Sbenno uart_setreg(bas, REG_IER, ier); 261119815Smarcel uart_barrier(bas); 262119815Smarcel 263119815Smarcel /* Disable the FIFO (if present). */ 264119815Smarcel uart_setreg(bas, REG_FCR, 0); 265119815Smarcel uart_barrier(bas); 266119815Smarcel 267119815Smarcel /* Set RTS & DTR. */ 268119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 269119815Smarcel uart_barrier(bas); 270119815Smarcel 271119815Smarcel ns8250_clrint(bas); 272119815Smarcel} 273119815Smarcel 274119815Smarcelstatic void 275119815Smarcelns8250_term(struct uart_bas *bas) 276119815Smarcel{ 277119815Smarcel 278119815Smarcel /* Clear RTS & DTR. */ 279119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE); 280119815Smarcel uart_barrier(bas); 281119815Smarcel} 282119815Smarcel 283119815Smarcelstatic void 284119815Smarcelns8250_putc(struct uart_bas *bas, int c) 285119815Smarcel{ 286119815Smarcel int delay, limit; 287119815Smarcel 288119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 289119815Smarcel delay = ns8250_delay(bas); 290119815Smarcel 291119815Smarcel limit = 20; 292119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 293119815Smarcel DELAY(delay); 294119815Smarcel uart_setreg(bas, REG_DATA, c); 295127742Smarcel uart_barrier(bas); 296119815Smarcel limit = 40; 297119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 298119815Smarcel DELAY(delay); 299119815Smarcel} 300119815Smarcel 301119815Smarcelstatic int 302119815Smarcelns8250_poll(struct uart_bas *bas) 303119815Smarcel{ 304119815Smarcel 305119815Smarcel if (uart_getreg(bas, REG_LSR) & LSR_RXRDY) 306119815Smarcel return (uart_getreg(bas, REG_DATA)); 307119815Smarcel return (-1); 308119815Smarcel} 309119815Smarcel 310119815Smarcelstatic int 311157380Smarcelns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 312119815Smarcel{ 313157380Smarcel int c, delay; 314119815Smarcel 315157380Smarcel uart_lock(hwmtx); 316157380Smarcel 317119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 318119815Smarcel delay = ns8250_delay(bas); 319119815Smarcel 320157380Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 321157380Smarcel uart_unlock(hwmtx); 322119815Smarcel DELAY(delay); 323157380Smarcel uart_lock(hwmtx); 324157380Smarcel } 325157380Smarcel 326157380Smarcel c = uart_getreg(bas, REG_DATA); 327157380Smarcel 328157380Smarcel uart_unlock(hwmtx); 329157380Smarcel 330157380Smarcel return (c); 331119815Smarcel} 332119815Smarcel 333119815Smarcel/* 334119815Smarcel * High-level UART interface. 335119815Smarcel */ 336119815Smarcelstruct ns8250_softc { 337119815Smarcel struct uart_softc base; 338119815Smarcel uint8_t fcr; 339119815Smarcel uint8_t ier; 340119815Smarcel uint8_t mcr; 341119815Smarcel}; 342119815Smarcel 343119815Smarcelstatic int ns8250_bus_attach(struct uart_softc *); 344119815Smarcelstatic int ns8250_bus_detach(struct uart_softc *); 345119815Smarcelstatic int ns8250_bus_flush(struct uart_softc *, int); 346119815Smarcelstatic int ns8250_bus_getsig(struct uart_softc *); 347119815Smarcelstatic int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 348119815Smarcelstatic int ns8250_bus_ipend(struct uart_softc *); 349119815Smarcelstatic int ns8250_bus_param(struct uart_softc *, int, int, int, int); 350119815Smarcelstatic int ns8250_bus_probe(struct uart_softc *); 351119815Smarcelstatic int ns8250_bus_receive(struct uart_softc *); 352119815Smarcelstatic int ns8250_bus_setsig(struct uart_softc *, int); 353119815Smarcelstatic int ns8250_bus_transmit(struct uart_softc *); 354119815Smarcel 355119815Smarcelstatic kobj_method_t ns8250_methods[] = { 356119815Smarcel KOBJMETHOD(uart_attach, ns8250_bus_attach), 357119815Smarcel KOBJMETHOD(uart_detach, ns8250_bus_detach), 358119815Smarcel KOBJMETHOD(uart_flush, ns8250_bus_flush), 359119815Smarcel KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 360119815Smarcel KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 361119815Smarcel KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 362119815Smarcel KOBJMETHOD(uart_param, ns8250_bus_param), 363119815Smarcel KOBJMETHOD(uart_probe, ns8250_bus_probe), 364119815Smarcel KOBJMETHOD(uart_receive, ns8250_bus_receive), 365119815Smarcel KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 366119815Smarcel KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 367119815Smarcel { 0, 0 } 368119815Smarcel}; 369119815Smarcel 370119815Smarcelstruct uart_class uart_ns8250_class = { 371119815Smarcel "ns8250 class", 372119815Smarcel ns8250_methods, 373119815Smarcel sizeof(struct ns8250_softc), 374119815Smarcel .uc_range = 8, 375119815Smarcel .uc_rclk = DEFAULT_RCLK 376119815Smarcel}; 377119815Smarcel 378119815Smarcel#define SIGCHG(c, i, s, d) \ 379119815Smarcel if (c) { \ 380119815Smarcel i |= (i & s) ? s : s | d; \ 381119815Smarcel } else { \ 382119815Smarcel i = (i & s) ? (i & ~s) | d : i; \ 383119815Smarcel } 384119815Smarcel 385119815Smarcelstatic int 386119815Smarcelns8250_bus_attach(struct uart_softc *sc) 387119815Smarcel{ 388119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 389119815Smarcel struct uart_bas *bas; 390119815Smarcel 391119815Smarcel bas = &sc->sc_bas; 392119815Smarcel 393119815Smarcel ns8250->mcr = uart_getreg(bas, REG_MCR); 394119815Smarcel ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH; 395119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 396119815Smarcel uart_barrier(bas); 397119815Smarcel ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 398119815Smarcel 399119815Smarcel if (ns8250->mcr & MCR_DTR) 400131043Sphk sc->sc_hwsig |= SER_DTR; 401119815Smarcel if (ns8250->mcr & MCR_RTS) 402131043Sphk sc->sc_hwsig |= SER_RTS; 403119815Smarcel ns8250_bus_getsig(sc); 404119815Smarcel 405119815Smarcel ns8250_clrint(bas); 406158844Sbenno ns8250->ier = uart_getreg(bas, REG_IER) & 0xf0; 407158844Sbenno ns8250->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY; 408119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier); 409119815Smarcel uart_barrier(bas); 410119815Smarcel return (0); 411119815Smarcel} 412119815Smarcel 413119815Smarcelstatic int 414119815Smarcelns8250_bus_detach(struct uart_softc *sc) 415119815Smarcel{ 416119815Smarcel struct uart_bas *bas; 417158844Sbenno u_char ier; 418119815Smarcel 419119815Smarcel bas = &sc->sc_bas; 420158844Sbenno ier = uart_getreg(bas, REG_IER) & 0xf0; 421158844Sbenno uart_setreg(bas, REG_IER, ier); 422119815Smarcel uart_barrier(bas); 423119815Smarcel ns8250_clrint(bas); 424119815Smarcel return (0); 425119815Smarcel} 426119815Smarcel 427119815Smarcelstatic int 428119815Smarcelns8250_bus_flush(struct uart_softc *sc, int what) 429119815Smarcel{ 430119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 431119815Smarcel struct uart_bas *bas; 432120143Smarcel int error; 433119815Smarcel 434119815Smarcel bas = &sc->sc_bas; 435157300Smarcel uart_lock(sc->sc_hwmtx); 436157418Smarcel if (sc->sc_rxfifosz > 1) { 437119815Smarcel ns8250_flush(bas, what); 438119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 439119815Smarcel uart_barrier(bas); 440120143Smarcel error = 0; 441120143Smarcel } else 442120143Smarcel error = ns8250_drain(bas, what); 443157300Smarcel uart_unlock(sc->sc_hwmtx); 444120143Smarcel return (error); 445119815Smarcel} 446119815Smarcel 447119815Smarcelstatic int 448119815Smarcelns8250_bus_getsig(struct uart_softc *sc) 449119815Smarcel{ 450119815Smarcel uint32_t new, old, sig; 451119815Smarcel uint8_t msr; 452119815Smarcel 453119815Smarcel do { 454119815Smarcel old = sc->sc_hwsig; 455119815Smarcel sig = old; 456157300Smarcel uart_lock(sc->sc_hwmtx); 457119815Smarcel msr = uart_getreg(&sc->sc_bas, REG_MSR); 458157300Smarcel uart_unlock(sc->sc_hwmtx); 459131043Sphk SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 460131043Sphk SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 461131043Sphk SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 462131043Sphk SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 463155973Smarcel new = sig & ~SER_MASK_DELTA; 464119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 465119815Smarcel return (sig); 466119815Smarcel} 467119815Smarcel 468119815Smarcelstatic int 469119815Smarcelns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 470119815Smarcel{ 471119815Smarcel struct uart_bas *bas; 472137709Smarcel int baudrate, divisor, error; 473120022Smarcel uint8_t efr, lcr; 474119815Smarcel 475119815Smarcel bas = &sc->sc_bas; 476120143Smarcel error = 0; 477157300Smarcel uart_lock(sc->sc_hwmtx); 478119815Smarcel switch (request) { 479119815Smarcel case UART_IOCTL_BREAK: 480119815Smarcel lcr = uart_getreg(bas, REG_LCR); 481119815Smarcel if (data) 482119815Smarcel lcr |= LCR_SBREAK; 483119815Smarcel else 484119815Smarcel lcr &= ~LCR_SBREAK; 485119815Smarcel uart_setreg(bas, REG_LCR, lcr); 486119815Smarcel uart_barrier(bas); 487119815Smarcel break; 488120022Smarcel case UART_IOCTL_IFLOW: 489120022Smarcel lcr = uart_getreg(bas, REG_LCR); 490120022Smarcel uart_barrier(bas); 491120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 492120022Smarcel uart_barrier(bas); 493120022Smarcel efr = uart_getreg(bas, REG_EFR); 494120022Smarcel if (data) 495120022Smarcel efr |= EFR_RTS; 496120022Smarcel else 497120022Smarcel efr &= ~EFR_RTS; 498120022Smarcel uart_setreg(bas, REG_EFR, efr); 499120022Smarcel uart_barrier(bas); 500120022Smarcel uart_setreg(bas, REG_LCR, lcr); 501120022Smarcel uart_barrier(bas); 502120022Smarcel break; 503120022Smarcel case UART_IOCTL_OFLOW: 504120022Smarcel lcr = uart_getreg(bas, REG_LCR); 505120022Smarcel uart_barrier(bas); 506120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 507120022Smarcel uart_barrier(bas); 508120022Smarcel efr = uart_getreg(bas, REG_EFR); 509120022Smarcel if (data) 510120022Smarcel efr |= EFR_CTS; 511120022Smarcel else 512120022Smarcel efr &= ~EFR_CTS; 513120022Smarcel uart_setreg(bas, REG_EFR, efr); 514120022Smarcel uart_barrier(bas); 515120022Smarcel uart_setreg(bas, REG_LCR, lcr); 516120022Smarcel uart_barrier(bas); 517120022Smarcel break; 518137707Smarcel case UART_IOCTL_BAUD: 519137707Smarcel lcr = uart_getreg(bas, REG_LCR); 520137707Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 521137707Smarcel uart_barrier(bas); 522158844Sbenno divisor = uart_getreg(bas, REG_DLL) | 523158844Sbenno (uart_getreg(bas, REG_DLH) << 8); 524137707Smarcel uart_barrier(bas); 525137707Smarcel uart_setreg(bas, REG_LCR, lcr); 526137707Smarcel uart_barrier(bas); 527137709Smarcel baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 528137709Smarcel if (baudrate > 0) 529137709Smarcel *(int*)data = baudrate; 530137709Smarcel else 531137709Smarcel error = ENXIO; 532137707Smarcel break; 533119815Smarcel default: 534120143Smarcel error = EINVAL; 535120143Smarcel break; 536119815Smarcel } 537157300Smarcel uart_unlock(sc->sc_hwmtx); 538120143Smarcel return (error); 539119815Smarcel} 540119815Smarcel 541119815Smarcelstatic int 542119815Smarcelns8250_bus_ipend(struct uart_softc *sc) 543119815Smarcel{ 544119815Smarcel struct uart_bas *bas; 545119815Smarcel int ipend; 546119815Smarcel uint8_t iir, lsr; 547119815Smarcel 548119815Smarcel bas = &sc->sc_bas; 549157300Smarcel uart_lock(sc->sc_hwmtx); 550119815Smarcel iir = uart_getreg(bas, REG_IIR); 551120143Smarcel if (iir & IIR_NOPEND) { 552157300Smarcel uart_unlock(sc->sc_hwmtx); 553119815Smarcel return (0); 554120143Smarcel } 555119815Smarcel ipend = 0; 556119815Smarcel if (iir & IIR_RXRDY) { 557119815Smarcel lsr = uart_getreg(bas, REG_LSR); 558157300Smarcel uart_unlock(sc->sc_hwmtx); 559119815Smarcel if (lsr & LSR_OE) 560155971Smarcel ipend |= SER_INT_OVERRUN; 561119815Smarcel if (lsr & LSR_BI) 562155971Smarcel ipend |= SER_INT_BREAK; 563119815Smarcel if (lsr & LSR_RXRDY) 564155971Smarcel ipend |= SER_INT_RXREADY; 565119815Smarcel } else { 566157300Smarcel uart_unlock(sc->sc_hwmtx); 567119815Smarcel if (iir & IIR_TXRDY) 568155971Smarcel ipend |= SER_INT_TXIDLE; 569119815Smarcel else 570155971Smarcel ipend |= SER_INT_SIGCHG; 571119815Smarcel } 572119815Smarcel return ((sc->sc_leaving) ? 0 : ipend); 573119815Smarcel} 574119815Smarcel 575119815Smarcelstatic int 576119815Smarcelns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 577119815Smarcel int stopbits, int parity) 578119815Smarcel{ 579119815Smarcel struct uart_bas *bas; 580120143Smarcel int error; 581119815Smarcel 582119815Smarcel bas = &sc->sc_bas; 583157300Smarcel uart_lock(sc->sc_hwmtx); 584120143Smarcel error = ns8250_param(bas, baudrate, databits, stopbits, parity); 585157300Smarcel uart_unlock(sc->sc_hwmtx); 586120143Smarcel return (error); 587119815Smarcel} 588119815Smarcel 589119815Smarcelstatic int 590119815Smarcelns8250_bus_probe(struct uart_softc *sc) 591119815Smarcel{ 592119815Smarcel struct uart_bas *bas; 593119815Smarcel int count, delay, error, limit; 594158844Sbenno uint8_t lsr, mcr, ier; 595119815Smarcel 596119815Smarcel bas = &sc->sc_bas; 597119815Smarcel 598119815Smarcel error = ns8250_probe(bas); 599119815Smarcel if (error) 600119815Smarcel return (error); 601119815Smarcel 602119815Smarcel mcr = MCR_IE; 603119815Smarcel if (sc->sc_sysdev == NULL) { 604119815Smarcel /* By using ns8250_init() we also set DTR and RTS. */ 605158069Smarcel ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 606119815Smarcel } else 607119815Smarcel mcr |= MCR_DTR | MCR_RTS; 608119815Smarcel 609119815Smarcel error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 610119815Smarcel if (error) 611119815Smarcel return (error); 612119815Smarcel 613119815Smarcel /* 614119815Smarcel * Set loopback mode. This avoids having garbage on the wire and 615119815Smarcel * also allows us send and receive data. We set DTR and RTS to 616119815Smarcel * avoid the possibility that automatic flow-control prevents 617129757Stmm * any data from being sent. 618119815Smarcel */ 619129757Stmm uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 620119815Smarcel uart_barrier(bas); 621119815Smarcel 622119815Smarcel /* 623119815Smarcel * Enable FIFOs. And check that the UART has them. If not, we're 624129757Stmm * done. Since this is the first time we enable the FIFOs, we reset 625129757Stmm * them. 626119815Smarcel */ 627119815Smarcel uart_setreg(bas, REG_FCR, FCR_ENABLE); 628119815Smarcel uart_barrier(bas); 629157418Smarcel if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 630119815Smarcel /* 631119815Smarcel * NS16450 or INS8250. We don't bother to differentiate 632119815Smarcel * between them. They're too old to be interesting. 633119815Smarcel */ 634119815Smarcel uart_setreg(bas, REG_MCR, mcr); 635119815Smarcel uart_barrier(bas); 636157418Smarcel sc->sc_rxfifosz = sc->sc_txfifosz = 1; 637119815Smarcel device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 638119815Smarcel return (0); 639119815Smarcel } 640119815Smarcel 641129757Stmm uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 642119815Smarcel uart_barrier(bas); 643119815Smarcel 644119815Smarcel count = 0; 645119815Smarcel delay = ns8250_delay(bas); 646119815Smarcel 647119815Smarcel /* We have FIFOs. Drain the transmitter and receiver. */ 648119815Smarcel error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 649119815Smarcel if (error) { 650119815Smarcel uart_setreg(bas, REG_MCR, mcr); 651119815Smarcel uart_setreg(bas, REG_FCR, 0); 652119815Smarcel uart_barrier(bas); 653119815Smarcel goto describe; 654119815Smarcel } 655119815Smarcel 656119815Smarcel /* 657119815Smarcel * We should have a sufficiently clean "pipe" to determine the 658119815Smarcel * size of the FIFOs. We send as much characters as is reasonable 659129757Stmm * and wait for the the overflow bit in the LSR register to be 660129757Stmm * asserted, counting the characters as we send them. Based on 661129757Stmm * that count we know the FIFO size. 662119815Smarcel */ 663129757Stmm do { 664119815Smarcel uart_setreg(bas, REG_DATA, 0); 665119815Smarcel uart_barrier(bas); 666119815Smarcel count++; 667119815Smarcel 668119815Smarcel limit = 30; 669129757Stmm lsr = 0; 670129757Stmm /* 671129757Stmm * LSR bits are cleared upon read, so we must accumulate 672129757Stmm * them to be able to test LSR_OE below. 673129757Stmm */ 674129757Stmm while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 675129757Stmm --limit) 676119815Smarcel DELAY(delay); 677119815Smarcel if (limit == 0) { 678158844Sbenno ier = uart_getreg(bas, REG_IER) & 0xf0; 679158844Sbenno uart_setreg(bas, REG_IER, ier); 680119815Smarcel uart_setreg(bas, REG_MCR, mcr); 681119815Smarcel uart_setreg(bas, REG_FCR, 0); 682119815Smarcel uart_barrier(bas); 683119815Smarcel count = 0; 684119815Smarcel goto describe; 685119815Smarcel } 686132650Smarcel } while ((lsr & LSR_OE) == 0 && count < 130); 687129757Stmm count--; 688119815Smarcel 689119815Smarcel uart_setreg(bas, REG_MCR, mcr); 690119815Smarcel 691119815Smarcel /* Reset FIFOs. */ 692119815Smarcel ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 693119815Smarcel 694119815Smarcel describe: 695129757Stmm if (count >= 14 && count <= 16) { 696119815Smarcel sc->sc_rxfifosz = 16; 697119815Smarcel device_set_desc(sc->sc_dev, "16550 or compatible"); 698129757Stmm } else if (count >= 28 && count <= 32) { 699119815Smarcel sc->sc_rxfifosz = 32; 700119815Smarcel device_set_desc(sc->sc_dev, "16650 or compatible"); 701129757Stmm } else if (count >= 56 && count <= 64) { 702119815Smarcel sc->sc_rxfifosz = 64; 703119815Smarcel device_set_desc(sc->sc_dev, "16750 or compatible"); 704129757Stmm } else if (count >= 112 && count <= 128) { 705119815Smarcel sc->sc_rxfifosz = 128; 706119815Smarcel device_set_desc(sc->sc_dev, "16950 or compatible"); 707119815Smarcel } else { 708119943Smarcel sc->sc_rxfifosz = 16; 709119815Smarcel device_set_desc(sc->sc_dev, 710119815Smarcel "Non-standard ns8250 class UART with FIFOs"); 711119815Smarcel } 712119815Smarcel 713119815Smarcel /* 714119815Smarcel * Force the Tx FIFO size to 16 bytes for now. We don't program the 715119815Smarcel * Tx trigger. Also, we assume that all data has been sent when the 716119815Smarcel * interrupt happens. 717119815Smarcel */ 718119815Smarcel sc->sc_txfifosz = 16; 719119815Smarcel 720133220Smarcel#if 0 721133220Smarcel /* 722133220Smarcel * XXX there are some issues related to hardware flow control and 723133220Smarcel * it's likely that uart(4) is the cause. This basicly needs more 724133220Smarcel * investigation, but we avoid using for hardware flow control 725133220Smarcel * until then. 726133220Smarcel */ 727120022Smarcel /* 16650s or higher have automatic flow control. */ 728120022Smarcel if (sc->sc_rxfifosz > 16) { 729120022Smarcel sc->sc_hwiflow = 1; 730120022Smarcel sc->sc_hwoflow = 1; 731120022Smarcel } 732133220Smarcel#endif 733120022Smarcel 734119815Smarcel return (0); 735119815Smarcel} 736119815Smarcel 737119815Smarcelstatic int 738119815Smarcelns8250_bus_receive(struct uart_softc *sc) 739119815Smarcel{ 740119815Smarcel struct uart_bas *bas; 741119815Smarcel int xc; 742119815Smarcel uint8_t lsr; 743119815Smarcel 744119815Smarcel bas = &sc->sc_bas; 745157300Smarcel uart_lock(sc->sc_hwmtx); 746120146Smarcel lsr = uart_getreg(bas, REG_LSR); 747120146Smarcel while (lsr & LSR_RXRDY) { 748120146Smarcel if (uart_rx_full(sc)) { 749120146Smarcel sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 750119815Smarcel break; 751120146Smarcel } 752119815Smarcel xc = uart_getreg(bas, REG_DATA); 753119815Smarcel if (lsr & LSR_FE) 754119815Smarcel xc |= UART_STAT_FRAMERR; 755119815Smarcel if (lsr & LSR_PE) 756119815Smarcel xc |= UART_STAT_PARERR; 757119815Smarcel uart_rx_put(sc, xc); 758120146Smarcel lsr = uart_getreg(bas, REG_LSR); 759119815Smarcel } 760120146Smarcel /* Discard everything left in the Rx FIFO. */ 761120146Smarcel while (lsr & LSR_RXRDY) { 762120146Smarcel (void)uart_getreg(bas, REG_DATA); 763120146Smarcel uart_barrier(bas); 764120146Smarcel lsr = uart_getreg(bas, REG_LSR); 765120146Smarcel } 766157300Smarcel uart_unlock(sc->sc_hwmtx); 767119815Smarcel return (0); 768119815Smarcel} 769119815Smarcel 770119815Smarcelstatic int 771119815Smarcelns8250_bus_setsig(struct uart_softc *sc, int sig) 772119815Smarcel{ 773119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 774119815Smarcel struct uart_bas *bas; 775119815Smarcel uint32_t new, old; 776119815Smarcel 777119815Smarcel bas = &sc->sc_bas; 778119815Smarcel do { 779119815Smarcel old = sc->sc_hwsig; 780119815Smarcel new = old; 781131043Sphk if (sig & SER_DDTR) { 782131043Sphk SIGCHG(sig & SER_DTR, new, SER_DTR, 783131043Sphk SER_DDTR); 784119815Smarcel } 785131043Sphk if (sig & SER_DRTS) { 786131043Sphk SIGCHG(sig & SER_RTS, new, SER_RTS, 787131043Sphk SER_DRTS); 788119815Smarcel } 789119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 790157300Smarcel uart_lock(sc->sc_hwmtx); 791119815Smarcel ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 792131043Sphk if (new & SER_DTR) 793119815Smarcel ns8250->mcr |= MCR_DTR; 794131043Sphk if (new & SER_RTS) 795119815Smarcel ns8250->mcr |= MCR_RTS; 796119815Smarcel uart_setreg(bas, REG_MCR, ns8250->mcr); 797119815Smarcel uart_barrier(bas); 798157300Smarcel uart_unlock(sc->sc_hwmtx); 799119815Smarcel return (0); 800119815Smarcel} 801119815Smarcel 802119815Smarcelstatic int 803119815Smarcelns8250_bus_transmit(struct uart_softc *sc) 804119815Smarcel{ 805119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 806119815Smarcel struct uart_bas *bas; 807119815Smarcel int i; 808119815Smarcel 809119815Smarcel bas = &sc->sc_bas; 810157300Smarcel uart_lock(sc->sc_hwmtx); 811119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 812119815Smarcel ; 813119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 814119815Smarcel uart_barrier(bas); 815119815Smarcel for (i = 0; i < sc->sc_txdatasz; i++) { 816119815Smarcel uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 817119815Smarcel uart_barrier(bas); 818119815Smarcel } 819119815Smarcel sc->sc_txbusy = 1; 820157300Smarcel uart_unlock(sc->sc_hwmtx); 821119815Smarcel return (0); 822119815Smarcel} 823