uart_dev_ns8250.c revision 157989
1139749Simp/*- 2119815Smarcel * Copyright (c) 2003 Marcel Moolenaar 3119815Smarcel * All rights reserved. 4119815Smarcel * 5119815Smarcel * Redistribution and use in source and binary forms, with or without 6119815Smarcel * modification, are permitted provided that the following conditions 7119815Smarcel * are met: 8119815Smarcel * 9119815Smarcel * 1. Redistributions of source code must retain the above copyright 10119815Smarcel * notice, this list of conditions and the following disclaimer. 11119815Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12119815Smarcel * notice, this list of conditions and the following disclaimer in the 13119815Smarcel * documentation and/or other materials provided with the distribution. 14119815Smarcel * 15119815Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16119815Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17119815Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18119815Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19119815Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20119815Smarcel * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21119815Smarcel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22119815Smarcel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23119815Smarcel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24119815Smarcel * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25119815Smarcel */ 26119815Smarcel 27119815Smarcel#include <sys/cdefs.h> 28119815Smarcel__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 157989 2006-04-23 21:15:07Z marcel $"); 29119815Smarcel 30119815Smarcel#include <sys/param.h> 31119815Smarcel#include <sys/systm.h> 32119815Smarcel#include <sys/bus.h> 33119815Smarcel#include <sys/conf.h> 34119815Smarcel#include <machine/bus.h> 35119815Smarcel 36119815Smarcel#include <dev/uart/uart.h> 37119815Smarcel#include <dev/uart/uart_cpu.h> 38119815Smarcel#include <dev/uart/uart_bus.h> 39119815Smarcel 40137949Smarcel#include <dev/ic/ns16550.h> 41137949Smarcel 42119815Smarcel#include "uart_if.h" 43119815Smarcel 44119815Smarcel#define DEFAULT_RCLK 1843200 45119815Smarcel 46119815Smarcel/* 47119815Smarcel * Clear pending interrupts. THRE is cleared by reading IIR. Data 48119815Smarcel * that may have been received gets lost here. 49119815Smarcel */ 50119815Smarcelstatic void 51119815Smarcelns8250_clrint(struct uart_bas *bas) 52119815Smarcel{ 53119815Smarcel uint8_t iir; 54119815Smarcel 55119815Smarcel iir = uart_getreg(bas, REG_IIR); 56119815Smarcel while ((iir & IIR_NOPEND) == 0) { 57119815Smarcel iir &= IIR_IMASK; 58119815Smarcel if (iir == IIR_RLS) 59119815Smarcel (void)uart_getreg(bas, REG_LSR); 60119815Smarcel else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 61119815Smarcel (void)uart_getreg(bas, REG_DATA); 62119815Smarcel else if (iir == IIR_MLSC) 63119815Smarcel (void)uart_getreg(bas, REG_MSR); 64119815Smarcel uart_barrier(bas); 65119815Smarcel iir = uart_getreg(bas, REG_IIR); 66119815Smarcel } 67119815Smarcel} 68119815Smarcel 69119815Smarcelstatic int 70119815Smarcelns8250_delay(struct uart_bas *bas) 71119815Smarcel{ 72119815Smarcel int divisor; 73119815Smarcel u_char lcr; 74119815Smarcel 75119815Smarcel lcr = uart_getreg(bas, REG_LCR); 76119815Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 77119815Smarcel uart_barrier(bas); 78119815Smarcel divisor = uart_getdreg(bas, REG_DL); 79119815Smarcel uart_barrier(bas); 80119815Smarcel uart_setreg(bas, REG_LCR, lcr); 81119815Smarcel uart_barrier(bas); 82119815Smarcel 83119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 84119815Smarcel return (16000000 * divisor / bas->rclk); 85119815Smarcel} 86119815Smarcel 87119815Smarcelstatic int 88119815Smarcelns8250_divisor(int rclk, int baudrate) 89119815Smarcel{ 90119815Smarcel int actual_baud, divisor; 91119815Smarcel int error; 92119815Smarcel 93119815Smarcel if (baudrate == 0) 94119815Smarcel return (0); 95119815Smarcel 96119815Smarcel divisor = (rclk / (baudrate << 3) + 1) >> 1; 97119815Smarcel if (divisor == 0 || divisor >= 65536) 98119815Smarcel return (0); 99119815Smarcel actual_baud = rclk / (divisor << 4); 100119815Smarcel 101119815Smarcel /* 10 times error in percent: */ 102119815Smarcel error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 103119815Smarcel 104119815Smarcel /* 3.0% maximum error tolerance: */ 105119815Smarcel if (error < -30 || error > 30) 106119815Smarcel return (0); 107119815Smarcel 108119815Smarcel return (divisor); 109119815Smarcel} 110119815Smarcel 111119815Smarcelstatic int 112119815Smarcelns8250_drain(struct uart_bas *bas, int what) 113119815Smarcel{ 114119815Smarcel int delay, limit; 115119815Smarcel 116119815Smarcel delay = ns8250_delay(bas); 117119815Smarcel 118119815Smarcel if (what & UART_DRAIN_TRANSMITTER) { 119119815Smarcel /* 120119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 121119815Smarcel * an infinite loop when the hardware is broken. Make the 122119815Smarcel * limit high enough to handle large FIFOs. 123119815Smarcel */ 124119815Smarcel limit = 10*1024; 125119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 126119815Smarcel DELAY(delay); 127119815Smarcel if (limit == 0) { 128119815Smarcel /* printf("ns8250: transmitter appears stuck... "); */ 129119815Smarcel return (EIO); 130119815Smarcel } 131119815Smarcel } 132119815Smarcel 133119815Smarcel if (what & UART_DRAIN_RECEIVER) { 134119815Smarcel /* 135119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 136119815Smarcel * an infinite loop when the hardware is broken. Make the 137119815Smarcel * limit high enough to handle large FIFOs and integrated 138119815Smarcel * UARTs. The HP rx2600 for example has 3 UARTs on the 139119815Smarcel * management board that tend to get a lot of data send 140119815Smarcel * to it when the UART is first activated. 141119815Smarcel */ 142119815Smarcel limit=10*4096; 143119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 144119815Smarcel (void)uart_getreg(bas, REG_DATA); 145119815Smarcel uart_barrier(bas); 146119815Smarcel DELAY(delay << 2); 147119815Smarcel } 148119815Smarcel if (limit == 0) { 149119815Smarcel /* printf("ns8250: receiver appears broken... "); */ 150119815Smarcel return (EIO); 151119815Smarcel } 152119815Smarcel } 153119815Smarcel 154119815Smarcel return (0); 155119815Smarcel} 156119815Smarcel 157119815Smarcel/* 158119815Smarcel * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 159119815Smarcel * drained. WARNING: this function clobbers the FIFO setting! 160119815Smarcel */ 161119815Smarcelstatic void 162119815Smarcelns8250_flush(struct uart_bas *bas, int what) 163119815Smarcel{ 164119815Smarcel uint8_t fcr; 165119815Smarcel 166119815Smarcel fcr = FCR_ENABLE; 167119815Smarcel if (what & UART_FLUSH_TRANSMITTER) 168119815Smarcel fcr |= FCR_XMT_RST; 169119815Smarcel if (what & UART_FLUSH_RECEIVER) 170119815Smarcel fcr |= FCR_RCV_RST; 171119815Smarcel uart_setreg(bas, REG_FCR, fcr); 172119815Smarcel uart_barrier(bas); 173119815Smarcel} 174119815Smarcel 175119815Smarcelstatic int 176119815Smarcelns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 177119815Smarcel int parity) 178119815Smarcel{ 179119815Smarcel int divisor; 180119815Smarcel uint8_t lcr; 181119815Smarcel 182119815Smarcel lcr = 0; 183119815Smarcel if (databits >= 8) 184119815Smarcel lcr |= LCR_8BITS; 185119815Smarcel else if (databits == 7) 186119815Smarcel lcr |= LCR_7BITS; 187119815Smarcel else if (databits == 6) 188119815Smarcel lcr |= LCR_6BITS; 189119815Smarcel else 190119815Smarcel lcr |= LCR_5BITS; 191119815Smarcel if (stopbits > 1) 192119815Smarcel lcr |= LCR_STOPB; 193119815Smarcel lcr |= parity << 3; 194119815Smarcel 195119815Smarcel /* Set baudrate. */ 196119815Smarcel if (baudrate > 0) { 197119815Smarcel divisor = ns8250_divisor(bas->rclk, baudrate); 198119815Smarcel if (divisor == 0) 199119815Smarcel return (EINVAL); 200157989Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 201157989Smarcel uart_barrier(bas); 202119815Smarcel uart_setdreg(bas, REG_DL, divisor); 203119815Smarcel uart_barrier(bas); 204119815Smarcel } 205119815Smarcel 206119815Smarcel /* Set LCR and clear DLAB. */ 207119815Smarcel uart_setreg(bas, REG_LCR, lcr); 208119815Smarcel uart_barrier(bas); 209119815Smarcel return (0); 210119815Smarcel} 211119815Smarcel 212119815Smarcel/* 213119815Smarcel * Low-level UART interface. 214119815Smarcel */ 215119815Smarcelstatic int ns8250_probe(struct uart_bas *bas); 216119815Smarcelstatic void ns8250_init(struct uart_bas *bas, int, int, int, int); 217119815Smarcelstatic void ns8250_term(struct uart_bas *bas); 218119815Smarcelstatic void ns8250_putc(struct uart_bas *bas, int); 219119815Smarcelstatic int ns8250_poll(struct uart_bas *bas); 220157380Smarcelstatic int ns8250_getc(struct uart_bas *bas, struct mtx *); 221119815Smarcel 222119815Smarcelstruct uart_ops uart_ns8250_ops = { 223119815Smarcel .probe = ns8250_probe, 224119815Smarcel .init = ns8250_init, 225119815Smarcel .term = ns8250_term, 226119815Smarcel .putc = ns8250_putc, 227119815Smarcel .poll = ns8250_poll, 228119815Smarcel .getc = ns8250_getc, 229119815Smarcel}; 230119815Smarcel 231119815Smarcelstatic int 232119815Smarcelns8250_probe(struct uart_bas *bas) 233119815Smarcel{ 234119815Smarcel u_char lcr, val; 235119815Smarcel 236119815Smarcel /* Check known 0 bits that don't depend on DLAB. */ 237119815Smarcel val = uart_getreg(bas, REG_IIR); 238119815Smarcel if (val & 0x30) 239119815Smarcel return (ENXIO); 240119815Smarcel val = uart_getreg(bas, REG_MCR); 241119815Smarcel if (val & 0xe0) 242119815Smarcel return (ENXIO); 243119815Smarcel 244119815Smarcel lcr = uart_getreg(bas, REG_LCR); 245119815Smarcel uart_setreg(bas, REG_LCR, lcr & ~LCR_DLAB); 246119815Smarcel uart_barrier(bas); 247119815Smarcel 248119815Smarcel /* Check known 0 bits that depend on !DLAB. */ 249119815Smarcel val = uart_getreg(bas, REG_IER); 250119815Smarcel if (val & 0xf0) 251119815Smarcel goto fail; 252119815Smarcel 253119815Smarcel uart_setreg(bas, REG_LCR, lcr); 254119815Smarcel uart_barrier(bas); 255119815Smarcel return (0); 256119815Smarcel 257119815Smarcel fail: 258119815Smarcel uart_setreg(bas, REG_LCR, lcr); 259119815Smarcel uart_barrier(bas); 260119815Smarcel return (ENXIO); 261119815Smarcel} 262119815Smarcel 263119815Smarcelstatic void 264119815Smarcelns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 265119815Smarcel int parity) 266119815Smarcel{ 267119815Smarcel 268119815Smarcel if (bas->rclk == 0) 269119815Smarcel bas->rclk = DEFAULT_RCLK; 270119815Smarcel ns8250_param(bas, baudrate, databits, stopbits, parity); 271119815Smarcel 272119815Smarcel /* Disable all interrupt sources. */ 273119815Smarcel uart_setreg(bas, REG_IER, 0); 274119815Smarcel uart_barrier(bas); 275119815Smarcel 276119815Smarcel /* Disable the FIFO (if present). */ 277119815Smarcel uart_setreg(bas, REG_FCR, 0); 278119815Smarcel uart_barrier(bas); 279119815Smarcel 280119815Smarcel /* Set RTS & DTR. */ 281119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 282119815Smarcel uart_barrier(bas); 283119815Smarcel 284119815Smarcel ns8250_clrint(bas); 285119815Smarcel} 286119815Smarcel 287119815Smarcelstatic void 288119815Smarcelns8250_term(struct uart_bas *bas) 289119815Smarcel{ 290119815Smarcel 291119815Smarcel /* Clear RTS & DTR. */ 292119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE); 293119815Smarcel uart_barrier(bas); 294119815Smarcel} 295119815Smarcel 296119815Smarcelstatic void 297119815Smarcelns8250_putc(struct uart_bas *bas, int c) 298119815Smarcel{ 299119815Smarcel int delay, limit; 300119815Smarcel 301119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 302119815Smarcel delay = ns8250_delay(bas); 303119815Smarcel 304119815Smarcel limit = 20; 305119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 306119815Smarcel DELAY(delay); 307119815Smarcel uart_setreg(bas, REG_DATA, c); 308127742Smarcel uart_barrier(bas); 309119815Smarcel limit = 40; 310119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 311119815Smarcel DELAY(delay); 312119815Smarcel} 313119815Smarcel 314119815Smarcelstatic int 315119815Smarcelns8250_poll(struct uart_bas *bas) 316119815Smarcel{ 317119815Smarcel 318119815Smarcel if (uart_getreg(bas, REG_LSR) & LSR_RXRDY) 319119815Smarcel return (uart_getreg(bas, REG_DATA)); 320119815Smarcel return (-1); 321119815Smarcel} 322119815Smarcel 323119815Smarcelstatic int 324157380Smarcelns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 325119815Smarcel{ 326157380Smarcel int c, delay; 327119815Smarcel 328157380Smarcel uart_lock(hwmtx); 329157380Smarcel 330119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 331119815Smarcel delay = ns8250_delay(bas); 332119815Smarcel 333157380Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 334157380Smarcel uart_unlock(hwmtx); 335119815Smarcel DELAY(delay); 336157380Smarcel uart_lock(hwmtx); 337157380Smarcel } 338157380Smarcel 339157380Smarcel c = uart_getreg(bas, REG_DATA); 340157380Smarcel 341157380Smarcel uart_unlock(hwmtx); 342157380Smarcel 343157380Smarcel return (c); 344119815Smarcel} 345119815Smarcel 346119815Smarcel/* 347119815Smarcel * High-level UART interface. 348119815Smarcel */ 349119815Smarcelstruct ns8250_softc { 350119815Smarcel struct uart_softc base; 351119815Smarcel uint8_t fcr; 352119815Smarcel uint8_t ier; 353119815Smarcel uint8_t mcr; 354119815Smarcel}; 355119815Smarcel 356119815Smarcelstatic int ns8250_bus_attach(struct uart_softc *); 357119815Smarcelstatic int ns8250_bus_detach(struct uart_softc *); 358119815Smarcelstatic int ns8250_bus_flush(struct uart_softc *, int); 359119815Smarcelstatic int ns8250_bus_getsig(struct uart_softc *); 360119815Smarcelstatic int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 361119815Smarcelstatic int ns8250_bus_ipend(struct uart_softc *); 362119815Smarcelstatic int ns8250_bus_param(struct uart_softc *, int, int, int, int); 363119815Smarcelstatic int ns8250_bus_probe(struct uart_softc *); 364119815Smarcelstatic int ns8250_bus_receive(struct uart_softc *); 365119815Smarcelstatic int ns8250_bus_setsig(struct uart_softc *, int); 366119815Smarcelstatic int ns8250_bus_transmit(struct uart_softc *); 367119815Smarcel 368119815Smarcelstatic kobj_method_t ns8250_methods[] = { 369119815Smarcel KOBJMETHOD(uart_attach, ns8250_bus_attach), 370119815Smarcel KOBJMETHOD(uart_detach, ns8250_bus_detach), 371119815Smarcel KOBJMETHOD(uart_flush, ns8250_bus_flush), 372119815Smarcel KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 373119815Smarcel KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 374119815Smarcel KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 375119815Smarcel KOBJMETHOD(uart_param, ns8250_bus_param), 376119815Smarcel KOBJMETHOD(uart_probe, ns8250_bus_probe), 377119815Smarcel KOBJMETHOD(uart_receive, ns8250_bus_receive), 378119815Smarcel KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 379119815Smarcel KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 380119815Smarcel { 0, 0 } 381119815Smarcel}; 382119815Smarcel 383119815Smarcelstruct uart_class uart_ns8250_class = { 384119815Smarcel "ns8250 class", 385119815Smarcel ns8250_methods, 386119815Smarcel sizeof(struct ns8250_softc), 387119815Smarcel .uc_range = 8, 388119815Smarcel .uc_rclk = DEFAULT_RCLK 389119815Smarcel}; 390119815Smarcel 391119815Smarcel#define SIGCHG(c, i, s, d) \ 392119815Smarcel if (c) { \ 393119815Smarcel i |= (i & s) ? s : s | d; \ 394119815Smarcel } else { \ 395119815Smarcel i = (i & s) ? (i & ~s) | d : i; \ 396119815Smarcel } 397119815Smarcel 398119815Smarcelstatic int 399119815Smarcelns8250_bus_attach(struct uart_softc *sc) 400119815Smarcel{ 401119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 402119815Smarcel struct uart_bas *bas; 403119815Smarcel 404119815Smarcel bas = &sc->sc_bas; 405119815Smarcel 406119815Smarcel ns8250->mcr = uart_getreg(bas, REG_MCR); 407119815Smarcel ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH; 408119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 409119815Smarcel uart_barrier(bas); 410119815Smarcel ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 411119815Smarcel 412119815Smarcel if (ns8250->mcr & MCR_DTR) 413131043Sphk sc->sc_hwsig |= SER_DTR; 414119815Smarcel if (ns8250->mcr & MCR_RTS) 415131043Sphk sc->sc_hwsig |= SER_RTS; 416119815Smarcel ns8250_bus_getsig(sc); 417119815Smarcel 418119815Smarcel ns8250_clrint(bas); 419119815Smarcel ns8250->ier = IER_EMSC | IER_ERLS | IER_ERXRDY; 420119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier); 421119815Smarcel uart_barrier(bas); 422119815Smarcel return (0); 423119815Smarcel} 424119815Smarcel 425119815Smarcelstatic int 426119815Smarcelns8250_bus_detach(struct uart_softc *sc) 427119815Smarcel{ 428119815Smarcel struct uart_bas *bas; 429119815Smarcel 430119815Smarcel bas = &sc->sc_bas; 431119815Smarcel uart_setreg(bas, REG_IER, 0); 432119815Smarcel uart_barrier(bas); 433119815Smarcel ns8250_clrint(bas); 434119815Smarcel return (0); 435119815Smarcel} 436119815Smarcel 437119815Smarcelstatic int 438119815Smarcelns8250_bus_flush(struct uart_softc *sc, int what) 439119815Smarcel{ 440119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 441119815Smarcel struct uart_bas *bas; 442120143Smarcel int error; 443119815Smarcel 444119815Smarcel bas = &sc->sc_bas; 445157300Smarcel uart_lock(sc->sc_hwmtx); 446157418Smarcel if (sc->sc_rxfifosz > 1) { 447119815Smarcel ns8250_flush(bas, what); 448119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 449119815Smarcel uart_barrier(bas); 450120143Smarcel error = 0; 451120143Smarcel } else 452120143Smarcel error = ns8250_drain(bas, what); 453157300Smarcel uart_unlock(sc->sc_hwmtx); 454120143Smarcel return (error); 455119815Smarcel} 456119815Smarcel 457119815Smarcelstatic int 458119815Smarcelns8250_bus_getsig(struct uart_softc *sc) 459119815Smarcel{ 460119815Smarcel uint32_t new, old, sig; 461119815Smarcel uint8_t msr; 462119815Smarcel 463119815Smarcel do { 464119815Smarcel old = sc->sc_hwsig; 465119815Smarcel sig = old; 466157300Smarcel uart_lock(sc->sc_hwmtx); 467119815Smarcel msr = uart_getreg(&sc->sc_bas, REG_MSR); 468157300Smarcel uart_unlock(sc->sc_hwmtx); 469131043Sphk SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 470131043Sphk SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 471131043Sphk SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 472131043Sphk SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 473155973Smarcel new = sig & ~SER_MASK_DELTA; 474119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 475119815Smarcel return (sig); 476119815Smarcel} 477119815Smarcel 478119815Smarcelstatic int 479119815Smarcelns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 480119815Smarcel{ 481119815Smarcel struct uart_bas *bas; 482137709Smarcel int baudrate, divisor, error; 483120022Smarcel uint8_t efr, lcr; 484119815Smarcel 485119815Smarcel bas = &sc->sc_bas; 486120143Smarcel error = 0; 487157300Smarcel uart_lock(sc->sc_hwmtx); 488119815Smarcel switch (request) { 489119815Smarcel case UART_IOCTL_BREAK: 490119815Smarcel lcr = uart_getreg(bas, REG_LCR); 491119815Smarcel if (data) 492119815Smarcel lcr |= LCR_SBREAK; 493119815Smarcel else 494119815Smarcel lcr &= ~LCR_SBREAK; 495119815Smarcel uart_setreg(bas, REG_LCR, lcr); 496119815Smarcel uart_barrier(bas); 497119815Smarcel break; 498120022Smarcel case UART_IOCTL_IFLOW: 499120022Smarcel lcr = uart_getreg(bas, REG_LCR); 500120022Smarcel uart_barrier(bas); 501120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 502120022Smarcel uart_barrier(bas); 503120022Smarcel efr = uart_getreg(bas, REG_EFR); 504120022Smarcel if (data) 505120022Smarcel efr |= EFR_RTS; 506120022Smarcel else 507120022Smarcel efr &= ~EFR_RTS; 508120022Smarcel uart_setreg(bas, REG_EFR, efr); 509120022Smarcel uart_barrier(bas); 510120022Smarcel uart_setreg(bas, REG_LCR, lcr); 511120022Smarcel uart_barrier(bas); 512120022Smarcel break; 513120022Smarcel case UART_IOCTL_OFLOW: 514120022Smarcel lcr = uart_getreg(bas, REG_LCR); 515120022Smarcel uart_barrier(bas); 516120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 517120022Smarcel uart_barrier(bas); 518120022Smarcel efr = uart_getreg(bas, REG_EFR); 519120022Smarcel if (data) 520120022Smarcel efr |= EFR_CTS; 521120022Smarcel else 522120022Smarcel efr &= ~EFR_CTS; 523120022Smarcel uart_setreg(bas, REG_EFR, efr); 524120022Smarcel uart_barrier(bas); 525120022Smarcel uart_setreg(bas, REG_LCR, lcr); 526120022Smarcel uart_barrier(bas); 527120022Smarcel break; 528137707Smarcel case UART_IOCTL_BAUD: 529137707Smarcel lcr = uart_getreg(bas, REG_LCR); 530137707Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 531137707Smarcel uart_barrier(bas); 532137707Smarcel divisor = uart_getdreg(bas, REG_DL); 533137707Smarcel uart_barrier(bas); 534137707Smarcel uart_setreg(bas, REG_LCR, lcr); 535137707Smarcel uart_barrier(bas); 536137709Smarcel baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 537137709Smarcel if (baudrate > 0) 538137709Smarcel *(int*)data = baudrate; 539137709Smarcel else 540137709Smarcel error = ENXIO; 541137707Smarcel break; 542119815Smarcel default: 543120143Smarcel error = EINVAL; 544120143Smarcel break; 545119815Smarcel } 546157300Smarcel uart_unlock(sc->sc_hwmtx); 547120143Smarcel return (error); 548119815Smarcel} 549119815Smarcel 550119815Smarcelstatic int 551119815Smarcelns8250_bus_ipend(struct uart_softc *sc) 552119815Smarcel{ 553119815Smarcel struct uart_bas *bas; 554119815Smarcel int ipend; 555119815Smarcel uint8_t iir, lsr; 556119815Smarcel 557119815Smarcel bas = &sc->sc_bas; 558157300Smarcel uart_lock(sc->sc_hwmtx); 559119815Smarcel iir = uart_getreg(bas, REG_IIR); 560120143Smarcel if (iir & IIR_NOPEND) { 561157300Smarcel uart_unlock(sc->sc_hwmtx); 562119815Smarcel return (0); 563120143Smarcel } 564119815Smarcel ipend = 0; 565119815Smarcel if (iir & IIR_RXRDY) { 566119815Smarcel lsr = uart_getreg(bas, REG_LSR); 567157300Smarcel uart_unlock(sc->sc_hwmtx); 568119815Smarcel if (lsr & LSR_OE) 569155971Smarcel ipend |= SER_INT_OVERRUN; 570119815Smarcel if (lsr & LSR_BI) 571155971Smarcel ipend |= SER_INT_BREAK; 572119815Smarcel if (lsr & LSR_RXRDY) 573155971Smarcel ipend |= SER_INT_RXREADY; 574119815Smarcel } else { 575157300Smarcel uart_unlock(sc->sc_hwmtx); 576119815Smarcel if (iir & IIR_TXRDY) 577155971Smarcel ipend |= SER_INT_TXIDLE; 578119815Smarcel else 579155971Smarcel ipend |= SER_INT_SIGCHG; 580119815Smarcel } 581119815Smarcel return ((sc->sc_leaving) ? 0 : ipend); 582119815Smarcel} 583119815Smarcel 584119815Smarcelstatic int 585119815Smarcelns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 586119815Smarcel int stopbits, int parity) 587119815Smarcel{ 588119815Smarcel struct uart_bas *bas; 589120143Smarcel int error; 590119815Smarcel 591119815Smarcel bas = &sc->sc_bas; 592157300Smarcel uart_lock(sc->sc_hwmtx); 593120143Smarcel error = ns8250_param(bas, baudrate, databits, stopbits, parity); 594157300Smarcel uart_unlock(sc->sc_hwmtx); 595120143Smarcel return (error); 596119815Smarcel} 597119815Smarcel 598119815Smarcelstatic int 599119815Smarcelns8250_bus_probe(struct uart_softc *sc) 600119815Smarcel{ 601119815Smarcel struct uart_bas *bas; 602119815Smarcel int count, delay, error, limit; 603129757Stmm uint8_t lsr, mcr; 604119815Smarcel 605119815Smarcel bas = &sc->sc_bas; 606119815Smarcel 607119815Smarcel error = ns8250_probe(bas); 608119815Smarcel if (error) 609119815Smarcel return (error); 610119815Smarcel 611119815Smarcel mcr = MCR_IE; 612119815Smarcel if (sc->sc_sysdev == NULL) { 613119815Smarcel /* By using ns8250_init() we also set DTR and RTS. */ 614119815Smarcel ns8250_init(bas, 9600, 8, 1, UART_PARITY_NONE); 615119815Smarcel } else 616119815Smarcel mcr |= MCR_DTR | MCR_RTS; 617119815Smarcel 618119815Smarcel error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 619119815Smarcel if (error) 620119815Smarcel return (error); 621119815Smarcel 622119815Smarcel /* 623119815Smarcel * Set loopback mode. This avoids having garbage on the wire and 624119815Smarcel * also allows us send and receive data. We set DTR and RTS to 625119815Smarcel * avoid the possibility that automatic flow-control prevents 626129757Stmm * any data from being sent. 627119815Smarcel */ 628129757Stmm uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 629119815Smarcel uart_barrier(bas); 630119815Smarcel 631119815Smarcel /* 632119815Smarcel * Enable FIFOs. And check that the UART has them. If not, we're 633129757Stmm * done. Since this is the first time we enable the FIFOs, we reset 634129757Stmm * them. 635119815Smarcel */ 636119815Smarcel uart_setreg(bas, REG_FCR, FCR_ENABLE); 637119815Smarcel uart_barrier(bas); 638157418Smarcel if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 639119815Smarcel /* 640119815Smarcel * NS16450 or INS8250. We don't bother to differentiate 641119815Smarcel * between them. They're too old to be interesting. 642119815Smarcel */ 643119815Smarcel uart_setreg(bas, REG_MCR, mcr); 644119815Smarcel uart_barrier(bas); 645157418Smarcel sc->sc_rxfifosz = sc->sc_txfifosz = 1; 646119815Smarcel device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 647119815Smarcel return (0); 648119815Smarcel } 649119815Smarcel 650129757Stmm uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 651119815Smarcel uart_barrier(bas); 652119815Smarcel 653119815Smarcel count = 0; 654119815Smarcel delay = ns8250_delay(bas); 655119815Smarcel 656119815Smarcel /* We have FIFOs. Drain the transmitter and receiver. */ 657119815Smarcel error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 658119815Smarcel if (error) { 659119815Smarcel uart_setreg(bas, REG_MCR, mcr); 660119815Smarcel uart_setreg(bas, REG_FCR, 0); 661119815Smarcel uart_barrier(bas); 662119815Smarcel goto describe; 663119815Smarcel } 664119815Smarcel 665119815Smarcel /* 666119815Smarcel * We should have a sufficiently clean "pipe" to determine the 667119815Smarcel * size of the FIFOs. We send as much characters as is reasonable 668129757Stmm * and wait for the the overflow bit in the LSR register to be 669129757Stmm * asserted, counting the characters as we send them. Based on 670129757Stmm * that count we know the FIFO size. 671119815Smarcel */ 672129757Stmm do { 673119815Smarcel uart_setreg(bas, REG_DATA, 0); 674119815Smarcel uart_barrier(bas); 675119815Smarcel count++; 676119815Smarcel 677119815Smarcel limit = 30; 678129757Stmm lsr = 0; 679129757Stmm /* 680129757Stmm * LSR bits are cleared upon read, so we must accumulate 681129757Stmm * them to be able to test LSR_OE below. 682129757Stmm */ 683129757Stmm while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 684129757Stmm --limit) 685119815Smarcel DELAY(delay); 686119815Smarcel if (limit == 0) { 687119815Smarcel uart_setreg(bas, REG_IER, 0); 688119815Smarcel uart_setreg(bas, REG_MCR, mcr); 689119815Smarcel uart_setreg(bas, REG_FCR, 0); 690119815Smarcel uart_barrier(bas); 691119815Smarcel count = 0; 692119815Smarcel goto describe; 693119815Smarcel } 694132650Smarcel } while ((lsr & LSR_OE) == 0 && count < 130); 695129757Stmm count--; 696119815Smarcel 697119815Smarcel uart_setreg(bas, REG_MCR, mcr); 698119815Smarcel 699119815Smarcel /* Reset FIFOs. */ 700119815Smarcel ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 701119815Smarcel 702119815Smarcel describe: 703129757Stmm if (count >= 14 && count <= 16) { 704119815Smarcel sc->sc_rxfifosz = 16; 705119815Smarcel device_set_desc(sc->sc_dev, "16550 or compatible"); 706129757Stmm } else if (count >= 28 && count <= 32) { 707119815Smarcel sc->sc_rxfifosz = 32; 708119815Smarcel device_set_desc(sc->sc_dev, "16650 or compatible"); 709129757Stmm } else if (count >= 56 && count <= 64) { 710119815Smarcel sc->sc_rxfifosz = 64; 711119815Smarcel device_set_desc(sc->sc_dev, "16750 or compatible"); 712129757Stmm } else if (count >= 112 && count <= 128) { 713119815Smarcel sc->sc_rxfifosz = 128; 714119815Smarcel device_set_desc(sc->sc_dev, "16950 or compatible"); 715119815Smarcel } else { 716119943Smarcel sc->sc_rxfifosz = 16; 717119815Smarcel device_set_desc(sc->sc_dev, 718119815Smarcel "Non-standard ns8250 class UART with FIFOs"); 719119815Smarcel } 720119815Smarcel 721119815Smarcel /* 722119815Smarcel * Force the Tx FIFO size to 16 bytes for now. We don't program the 723119815Smarcel * Tx trigger. Also, we assume that all data has been sent when the 724119815Smarcel * interrupt happens. 725119815Smarcel */ 726119815Smarcel sc->sc_txfifosz = 16; 727119815Smarcel 728133220Smarcel#if 0 729133220Smarcel /* 730133220Smarcel * XXX there are some issues related to hardware flow control and 731133220Smarcel * it's likely that uart(4) is the cause. This basicly needs more 732133220Smarcel * investigation, but we avoid using for hardware flow control 733133220Smarcel * until then. 734133220Smarcel */ 735120022Smarcel /* 16650s or higher have automatic flow control. */ 736120022Smarcel if (sc->sc_rxfifosz > 16) { 737120022Smarcel sc->sc_hwiflow = 1; 738120022Smarcel sc->sc_hwoflow = 1; 739120022Smarcel } 740133220Smarcel#endif 741120022Smarcel 742119815Smarcel return (0); 743119815Smarcel} 744119815Smarcel 745119815Smarcelstatic int 746119815Smarcelns8250_bus_receive(struct uart_softc *sc) 747119815Smarcel{ 748119815Smarcel struct uart_bas *bas; 749119815Smarcel int xc; 750119815Smarcel uint8_t lsr; 751119815Smarcel 752119815Smarcel bas = &sc->sc_bas; 753157300Smarcel uart_lock(sc->sc_hwmtx); 754120146Smarcel lsr = uart_getreg(bas, REG_LSR); 755120146Smarcel while (lsr & LSR_RXRDY) { 756120146Smarcel if (uart_rx_full(sc)) { 757120146Smarcel sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 758119815Smarcel break; 759120146Smarcel } 760119815Smarcel xc = uart_getreg(bas, REG_DATA); 761119815Smarcel if (lsr & LSR_FE) 762119815Smarcel xc |= UART_STAT_FRAMERR; 763119815Smarcel if (lsr & LSR_PE) 764119815Smarcel xc |= UART_STAT_PARERR; 765119815Smarcel uart_rx_put(sc, xc); 766120146Smarcel lsr = uart_getreg(bas, REG_LSR); 767119815Smarcel } 768120146Smarcel /* Discard everything left in the Rx FIFO. */ 769120146Smarcel while (lsr & LSR_RXRDY) { 770120146Smarcel (void)uart_getreg(bas, REG_DATA); 771120146Smarcel uart_barrier(bas); 772120146Smarcel lsr = uart_getreg(bas, REG_LSR); 773120146Smarcel } 774157300Smarcel uart_unlock(sc->sc_hwmtx); 775119815Smarcel return (0); 776119815Smarcel} 777119815Smarcel 778119815Smarcelstatic int 779119815Smarcelns8250_bus_setsig(struct uart_softc *sc, int sig) 780119815Smarcel{ 781119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 782119815Smarcel struct uart_bas *bas; 783119815Smarcel uint32_t new, old; 784119815Smarcel 785119815Smarcel bas = &sc->sc_bas; 786119815Smarcel do { 787119815Smarcel old = sc->sc_hwsig; 788119815Smarcel new = old; 789131043Sphk if (sig & SER_DDTR) { 790131043Sphk SIGCHG(sig & SER_DTR, new, SER_DTR, 791131043Sphk SER_DDTR); 792119815Smarcel } 793131043Sphk if (sig & SER_DRTS) { 794131043Sphk SIGCHG(sig & SER_RTS, new, SER_RTS, 795131043Sphk SER_DRTS); 796119815Smarcel } 797119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 798157300Smarcel uart_lock(sc->sc_hwmtx); 799119815Smarcel ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 800131043Sphk if (new & SER_DTR) 801119815Smarcel ns8250->mcr |= MCR_DTR; 802131043Sphk if (new & SER_RTS) 803119815Smarcel ns8250->mcr |= MCR_RTS; 804119815Smarcel uart_setreg(bas, REG_MCR, ns8250->mcr); 805119815Smarcel uart_barrier(bas); 806157300Smarcel uart_unlock(sc->sc_hwmtx); 807119815Smarcel return (0); 808119815Smarcel} 809119815Smarcel 810119815Smarcelstatic int 811119815Smarcelns8250_bus_transmit(struct uart_softc *sc) 812119815Smarcel{ 813119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 814119815Smarcel struct uart_bas *bas; 815119815Smarcel int i; 816119815Smarcel 817119815Smarcel bas = &sc->sc_bas; 818157300Smarcel uart_lock(sc->sc_hwmtx); 819119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 820119815Smarcel ; 821119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 822119815Smarcel uart_barrier(bas); 823119815Smarcel for (i = 0; i < sc->sc_txdatasz; i++) { 824119815Smarcel uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 825119815Smarcel uart_barrier(bas); 826119815Smarcel } 827119815Smarcel sc->sc_txbusy = 1; 828157300Smarcel uart_unlock(sc->sc_hwmtx); 829119815Smarcel return (0); 830119815Smarcel} 831