1/* 2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 3 * Copyright (c) 2004-05 Vinod Kashyap. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: releng/10.3/sys/dev/twa/tw_osl.h 246713 2013-02-12 16:57:20Z kib $ 28 */ 29 30/* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 * Modifications by: Adam Radford 35 * Modifications by: Manjunath Ranganathaiah 36 */ 37 38 39 40#ifndef TW_OSL_H 41 42#define TW_OSL_H 43 44 45/* 46 * OS Layer internal macros, structures and functions. 47 */ 48 49 50#define TW_OSLI_DEVICE_NAME "3ware 9000 series Storage Controller" 51 52#define TW_OSLI_MALLOC_CLASS M_TWA 53#define TW_OSLI_MAX_NUM_REQUESTS TW_CL_MAX_SIMULTANEOUS_REQUESTS 54/* Reserve two command packets. One for ioctls and one for AENs */ 55#define TW_OSLI_MAX_NUM_IOS (TW_OSLI_MAX_NUM_REQUESTS - 2) 56#define TW_OSLI_MAX_NUM_AENS 0x100 57 58/* Possible values of req->state. */ 59#define TW_OSLI_REQ_STATE_INIT 0x0 /* being initialized */ 60#define TW_OSLI_REQ_STATE_BUSY 0x1 /* submitted to CL */ 61#define TW_OSLI_REQ_STATE_PENDING 0x2 /* in pending queue */ 62#define TW_OSLI_REQ_STATE_COMPLETE 0x3 /* completed by CL */ 63 64/* Possible values of req->flags. */ 65#define TW_OSLI_REQ_FLAGS_DATA_IN (1<<0) /* read request */ 66#define TW_OSLI_REQ_FLAGS_DATA_OUT (1<<1) /* write request */ 67#define TW_OSLI_REQ_FLAGS_DATA_COPY_NEEDED (1<<2)/* data in ccb is misaligned, 68 have to copy to/from private buffer */ 69#define TW_OSLI_REQ_FLAGS_MAPPED (1<<3) /* request has been mapped */ 70#define TW_OSLI_REQ_FLAGS_IN_PROGRESS (1<<4) /* bus_dmamap_load returned 71 EINPROGRESS */ 72#define TW_OSLI_REQ_FLAGS_PASSTHRU (1<<5) /* pass through request */ 73#define TW_OSLI_REQ_FLAGS_SLEEPING (1<<6) /* owner sleeping on this cmd */ 74#define TW_OSLI_REQ_FLAGS_FAILED (1<<7) /* bus_dmamap_load() failed */ 75#define TW_OSLI_REQ_FLAGS_CCB (1<<8) /* req is ccb. */ 76 77 78#ifdef TW_OSL_DEBUG 79struct tw_osli_q_stats { 80 TW_UINT32 cur_len; /* current # of items in q */ 81 TW_UINT32 max_len; /* max value reached by q_length */ 82}; 83#endif /* TW_OSL_DEBUG */ 84 85 86/* Queues of OSL internal request context packets. */ 87#define TW_OSLI_FREE_Q 0 /* free q */ 88#define TW_OSLI_BUSY_Q 1 /* q of reqs submitted to CL */ 89#define TW_OSLI_Q_COUNT 2 /* total number of queues */ 90 91/* Driver's request packet. */ 92struct tw_osli_req_context { 93 struct tw_cl_req_handle req_handle;/* tag to track req b/w OSL & CL */ 94 struct mtx ioctl_wake_timeout_lock_handle;/* non-spin lock used to detect ioctl timeout */ 95 struct mtx *ioctl_wake_timeout_lock;/* ptr to above lock */ 96 struct twa_softc *ctlr; /* ptr to OSL's controller context */ 97 TW_VOID *data; /* ptr to data being passed to CL */ 98 TW_UINT32 length; /* length of buf being passed to CL */ 99 TW_UINT64 deadline;/* request timeout (in absolute time) */ 100 101 /* 102 * ptr to, and length of data passed to us from above, in case a buffer 103 * copy was done due to non-compliance to alignment requirements 104 */ 105 TW_VOID *real_data; 106 TW_UINT32 real_length; 107 108 TW_UINT32 state; /* request state */ 109 TW_UINT32 flags; /* request flags */ 110 111 /* error encountered before request submission to CL */ 112 TW_UINT32 error_code; 113 114 /* ptr to orig req for use during callback */ 115 TW_VOID *orig_req; 116 117 struct tw_cl_link link; /* to link this request in a list */ 118 bus_dmamap_t dma_map;/* DMA map for data */ 119 struct tw_cl_req_packet req_pkt;/* req pkt understood by CL */ 120}; 121 122 123/* Per-controller structure. */ 124struct twa_softc { 125 struct tw_cl_ctlr_handle ctlr_handle; 126 struct tw_osli_req_context *req_ctx_buf; 127 128 /* Controller state. */ 129 TW_UINT8 open; 130 TW_UINT32 flags; 131 132 TW_INT32 device_id; 133 TW_UINT32 alignment; 134 TW_UINT32 sg_size_factor; 135 136 TW_VOID *non_dma_mem; 137 TW_VOID *dma_mem; 138 TW_UINT64 dma_mem_phys; 139 140 /* Request queues and arrays. */ 141 struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT]; 142 143 struct task deferred_intr_callback;/* taskqueue function */ 144 struct mtx io_lock_handle;/* general purpose lock */ 145 struct mtx *io_lock;/* ptr to general purpose lock */ 146 struct mtx q_lock_handle; /* queue manipulation lock */ 147 struct mtx *q_lock;/* ptr to queue manipulation lock */ 148 struct mtx sim_lock_handle;/* sim lock shared with cam */ 149 struct mtx *sim_lock;/* ptr to sim lock */ 150 151 struct callout watchdog_callout[2]; /* For command timeout */ 152 TW_UINT32 watchdog_index; 153 154#ifdef TW_OSL_DEBUG 155 struct tw_osli_q_stats q_stats[TW_OSLI_Q_COUNT];/* queue statistics */ 156#endif /* TW_OSL_DEBUG */ 157 158 device_t bus_dev; /* bus device */ 159 struct cdev *ctrl_dev; /* control device */ 160 struct resource *reg_res; /* register interface window */ 161 TW_INT32 reg_res_id; /* register resource id */ 162 bus_space_handle_t bus_handle; /* bus space handle */ 163 bus_space_tag_t bus_tag; /* bus space tag */ 164 bus_dma_tag_t parent_tag; /* parent DMA tag */ 165 bus_dma_tag_t cmd_tag; /* DMA tag for CL's DMA'able mem */ 166 bus_dma_tag_t dma_tag; /* data buffer DMA tag */ 167 bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */ 168 bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */ 169 bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */ 170 struct resource *irq_res; /* interrupt resource */ 171 TW_INT32 irq_res_id; /* register resource id */ 172 TW_VOID *intr_handle; /* interrupt handle */ 173 174 struct sysctl_ctx_list sysctl_ctxt; /* sysctl context */ 175 struct sysctl_oid *sysctl_tree; /* sysctl oid */ 176 177 struct cam_sim *sim; /* sim for this controller */ 178 struct cam_path *path; /* peripheral, path, tgt, lun 179 associated with this controller */ 180}; 181 182 183 184/* 185 * Queue primitives. 186 */ 187 188#ifdef TW_OSL_DEBUG 189 190#define TW_OSLI_Q_INIT(sc, q_type) do { \ 191 (sc)->q_stats[q_type].cur_len = 0; \ 192 (sc)->q_stats[q_type].max_len = 0; \ 193} while(0) 194 195 196#define TW_OSLI_Q_INSERT(sc, q_type) do { \ 197 struct tw_osli_q_stats *q_stats = &((sc)->q_stats[q_type]); \ 198 \ 199 if (++(q_stats->cur_len) > q_stats->max_len) \ 200 q_stats->max_len = q_stats->cur_len; \ 201} while(0) 202 203 204#define TW_OSLI_Q_REMOVE(sc, q_type) \ 205 (sc)->q_stats[q_type].cur_len-- 206 207 208#else /* TW_OSL_DEBUG */ 209 210#define TW_OSLI_Q_INIT(sc, q_index) 211#define TW_OSLI_Q_INSERT(sc, q_index) 212#define TW_OSLI_Q_REMOVE(sc, q_index) 213 214#endif /* TW_OSL_DEBUG */ 215 216 217 218/* Initialize a queue of requests. */ 219static __inline TW_VOID 220tw_osli_req_q_init(struct twa_softc *sc, TW_UINT8 q_type) 221{ 222 TW_CL_Q_INIT(&(sc->req_q_head[q_type])); 223 TW_OSLI_Q_INIT(sc, q_type); 224} 225 226 227 228/* Insert the given request at the head of the given queue (q_type). */ 229static __inline TW_VOID 230tw_osli_req_q_insert_head(struct tw_osli_req_context *req, TW_UINT8 q_type) 231{ 232 mtx_lock_spin(req->ctlr->q_lock); 233 TW_CL_Q_INSERT_HEAD(&(req->ctlr->req_q_head[q_type]), &(req->link)); 234 TW_OSLI_Q_INSERT(req->ctlr, q_type); 235 mtx_unlock_spin(req->ctlr->q_lock); 236} 237 238 239 240/* Insert the given request at the tail of the given queue (q_type). */ 241static __inline TW_VOID 242tw_osli_req_q_insert_tail(struct tw_osli_req_context *req, TW_UINT8 q_type) 243{ 244 mtx_lock_spin(req->ctlr->q_lock); 245 TW_CL_Q_INSERT_TAIL(&(req->ctlr->req_q_head[q_type]), &(req->link)); 246 TW_OSLI_Q_INSERT(req->ctlr, q_type); 247 mtx_unlock_spin(req->ctlr->q_lock); 248} 249 250 251 252/* Remove and return the request at the head of the given queue (q_type). */ 253static __inline struct tw_osli_req_context * 254tw_osli_req_q_remove_head(struct twa_softc *sc, TW_UINT8 q_type) 255{ 256 struct tw_osli_req_context *req = NULL; 257 struct tw_cl_link *link; 258 259 mtx_lock_spin(sc->q_lock); 260 if ((link = TW_CL_Q_FIRST_ITEM(&(sc->req_q_head[q_type]))) != 261 TW_CL_NULL) { 262 req = TW_CL_STRUCT_HEAD(link, 263 struct tw_osli_req_context, link); 264 TW_CL_Q_REMOVE_ITEM(&(sc->req_q_head[q_type]), &(req->link)); 265 TW_OSLI_Q_REMOVE(sc, q_type); 266 } 267 mtx_unlock_spin(sc->q_lock); 268 return(req); 269} 270 271 272 273/* Remove the given request from the given queue (q_type). */ 274static __inline TW_VOID 275tw_osli_req_q_remove_item(struct tw_osli_req_context *req, TW_UINT8 q_type) 276{ 277 mtx_lock_spin(req->ctlr->q_lock); 278 TW_CL_Q_REMOVE_ITEM(&(req->ctlr->req_q_head[q_type]), &(req->link)); 279 TW_OSLI_Q_REMOVE(req->ctlr, q_type); 280 mtx_unlock_spin(req->ctlr->q_lock); 281} 282 283 284 285#ifdef TW_OSL_DEBUG 286 287extern TW_INT32 TW_DEBUG_LEVEL_FOR_OSL; 288 289#define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) \ 290 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \ 291 device_printf(sc->bus_dev, "%s: " fmt "\n", \ 292 __func__, ##args) 293 294 295#define tw_osli_dbg_printf(dbg_level, fmt, args...) \ 296 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \ 297 printf("%s: " fmt "\n", __func__, ##args) 298 299#else /* TW_OSL_DEBUG */ 300 301#define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) 302#define tw_osli_dbg_printf(dbg_level, fmt, args...) 303 304#endif /* TW_OSL_DEBUG */ 305 306 307/* For regular printing. */ 308#define twa_printf(sc, fmt, args...) \ 309 device_printf(((struct twa_softc *)(sc))->bus_dev, fmt, ##args) 310 311/* For printing in the "consistent error reporting" format. */ 312#define tw_osli_printf(sc, err_specific_desc, args...) \ 313 device_printf((sc)->bus_dev, \ 314 "%s: (0x%02X: 0x%04X): %s: " err_specific_desc "\n", ##args) 315 316 317 318#endif /* TW_OSL_H */ 319