1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: releng/10.3/sys/dev/sis/if_sis.c 280657 2015-03-26 04:55:22Z yongari $"); 36 37/* 38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 39 * available from http://www.sis.com.tw. 40 * 41 * This driver also supports the NatSemi DP83815. Datasheets are 42 * available from http://www.national.com. 43 * 44 * Written by Bill Paul <wpaul@ee.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48/* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61#ifdef HAVE_KERNEL_OPTION_HEADERS 62#include "opt_device_polling.h" 63#endif 64 65#include <sys/param.h> 66#include <sys/systm.h> 67#include <sys/bus.h> 68#include <sys/endian.h> 69#include <sys/kernel.h> 70#include <sys/lock.h> 71#include <sys/malloc.h> 72#include <sys/mbuf.h> 73#include <sys/module.h> 74#include <sys/socket.h> 75#include <sys/sockio.h> 76#include <sys/sysctl.h> 77 78#include <net/if.h> 79#include <net/if_arp.h> 80#include <net/ethernet.h> 81#include <net/if_dl.h> 82#include <net/if_media.h> 83#include <net/if_types.h> 84#include <net/if_vlan_var.h> 85 86#include <net/bpf.h> 87 88#include <machine/bus.h> 89#include <machine/resource.h> 90#include <sys/rman.h> 91 92#include <dev/mii/mii.h> 93#include <dev/mii/mii_bitbang.h> 94#include <dev/mii/miivar.h> 95 96#include <dev/pci/pcireg.h> 97#include <dev/pci/pcivar.h> 98 99#define SIS_USEIOSPACE 100 101#include <dev/sis/if_sisreg.h> 102 103MODULE_DEPEND(sis, pci, 1, 1, 1); 104MODULE_DEPEND(sis, ether, 1, 1, 1); 105MODULE_DEPEND(sis, miibus, 1, 1, 1); 106 107/* "device miibus" required. See GENERIC if you get errors here. */ 108#include "miibus_if.h" 109 110#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 111#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 112#define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 113 114/* 115 * register space access macros 116 */ 117#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 118 119#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 120 121#define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 122 123#define CSR_BARRIER(sc, reg, length, flags) \ 124 bus_barrier(sc->sis_res[0], reg, length, flags) 125 126/* 127 * Various supported device vendors/types and their names. 128 */ 129static const struct sis_type sis_devs[] = { 130 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 131 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 132 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 133 { 0, 0, NULL } 134}; 135 136static int sis_detach(device_t); 137static __inline void sis_discard_rxbuf(struct sis_rxdesc *); 138static int sis_dma_alloc(struct sis_softc *); 139static void sis_dma_free(struct sis_softc *); 140static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t, 141 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 142static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int); 143#ifndef __NO_STRICT_ALIGNMENT 144static __inline void sis_fixup_rx(struct mbuf *); 145#endif 146static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147static int sis_ifmedia_upd(struct ifnet *); 148static void sis_init(void *); 149static void sis_initl(struct sis_softc *); 150static void sis_intr(void *); 151static int sis_ioctl(struct ifnet *, u_long, caddr_t); 152static uint32_t sis_mii_bitbang_read(device_t); 153static void sis_mii_bitbang_write(device_t, uint32_t); 154static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *); 155static int sis_resume(device_t); 156static int sis_rxeof(struct sis_softc *); 157static void sis_rxfilter(struct sis_softc *); 158static void sis_rxfilter_ns(struct sis_softc *); 159static void sis_rxfilter_sis(struct sis_softc *); 160static void sis_start(struct ifnet *); 161static void sis_startl(struct ifnet *); 162static void sis_stop(struct sis_softc *); 163static int sis_suspend(device_t); 164static void sis_add_sysctls(struct sis_softc *); 165static void sis_watchdog(struct sis_softc *); 166static void sis_wol(struct sis_softc *); 167 168/* 169 * MII bit-bang glue 170 */ 171static const struct mii_bitbang_ops sis_mii_bitbang_ops = { 172 sis_mii_bitbang_read, 173 sis_mii_bitbang_write, 174 { 175 SIS_MII_DATA, /* MII_BIT_MDO */ 176 SIS_MII_DATA, /* MII_BIT_MDI */ 177 SIS_MII_CLK, /* MII_BIT_MDC */ 178 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 179 0, /* MII_BIT_DIR_PHY_HOST */ 180 } 181}; 182 183static struct resource_spec sis_res_spec[] = { 184#ifdef SIS_USEIOSPACE 185 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 186#else 187 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 188#endif 189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 190 { -1, 0 } 191}; 192 193#define SIS_SETBIT(sc, reg, x) \ 194 CSR_WRITE_4(sc, reg, \ 195 CSR_READ_4(sc, reg) | (x)) 196 197#define SIS_CLRBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, \ 199 CSR_READ_4(sc, reg) & ~(x)) 200 201#define SIO_SET(x) \ 202 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 203 204#define SIO_CLR(x) \ 205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 206 207/* 208 * Routine to reverse the bits in a word. Stolen almost 209 * verbatim from /usr/games/fortune. 210 */ 211static uint16_t 212sis_reverse(uint16_t n) 213{ 214 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 215 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 216 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 217 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 218 219 return (n); 220} 221 222static void 223sis_delay(struct sis_softc *sc) 224{ 225 int idx; 226 227 for (idx = (300 / 33) + 1; idx > 0; idx--) 228 CSR_READ_4(sc, SIS_CSR); 229} 230 231static void 232sis_eeprom_idle(struct sis_softc *sc) 233{ 234 int i; 235 236 SIO_SET(SIS_EECTL_CSEL); 237 sis_delay(sc); 238 SIO_SET(SIS_EECTL_CLK); 239 sis_delay(sc); 240 241 for (i = 0; i < 25; i++) { 242 SIO_CLR(SIS_EECTL_CLK); 243 sis_delay(sc); 244 SIO_SET(SIS_EECTL_CLK); 245 sis_delay(sc); 246 } 247 248 SIO_CLR(SIS_EECTL_CLK); 249 sis_delay(sc); 250 SIO_CLR(SIS_EECTL_CSEL); 251 sis_delay(sc); 252 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 253} 254 255/* 256 * Send a read command and address to the EEPROM, check for ACK. 257 */ 258static void 259sis_eeprom_putbyte(struct sis_softc *sc, int addr) 260{ 261 int d, i; 262 263 d = addr | SIS_EECMD_READ; 264 265 /* 266 * Feed in each bit and stobe the clock. 267 */ 268 for (i = 0x400; i; i >>= 1) { 269 if (d & i) { 270 SIO_SET(SIS_EECTL_DIN); 271 } else { 272 SIO_CLR(SIS_EECTL_DIN); 273 } 274 sis_delay(sc); 275 SIO_SET(SIS_EECTL_CLK); 276 sis_delay(sc); 277 SIO_CLR(SIS_EECTL_CLK); 278 sis_delay(sc); 279 } 280} 281 282/* 283 * Read a word of data stored in the EEPROM at address 'addr.' 284 */ 285static void 286sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 287{ 288 int i; 289 uint16_t word = 0; 290 291 /* Force EEPROM to idle state. */ 292 sis_eeprom_idle(sc); 293 294 /* Enter EEPROM access mode. */ 295 sis_delay(sc); 296 SIO_CLR(SIS_EECTL_CLK); 297 sis_delay(sc); 298 SIO_SET(SIS_EECTL_CSEL); 299 sis_delay(sc); 300 301 /* 302 * Send address of word we want to read. 303 */ 304 sis_eeprom_putbyte(sc, addr); 305 306 /* 307 * Start reading bits from EEPROM. 308 */ 309 for (i = 0x8000; i; i >>= 1) { 310 SIO_SET(SIS_EECTL_CLK); 311 sis_delay(sc); 312 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 313 word |= i; 314 sis_delay(sc); 315 SIO_CLR(SIS_EECTL_CLK); 316 sis_delay(sc); 317 } 318 319 /* Turn off EEPROM access mode. */ 320 sis_eeprom_idle(sc); 321 322 *dest = word; 323} 324 325/* 326 * Read a sequence of words from the EEPROM. 327 */ 328static void 329sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 330{ 331 int i; 332 uint16_t word = 0, *ptr; 333 334 for (i = 0; i < cnt; i++) { 335 sis_eeprom_getword(sc, off + i, &word); 336 ptr = (uint16_t *)(dest + (i * 2)); 337 if (swap) 338 *ptr = ntohs(word); 339 else 340 *ptr = word; 341 } 342} 343 344#if defined(__i386__) || defined(__amd64__) 345static device_t 346sis_find_bridge(device_t dev) 347{ 348 devclass_t pci_devclass; 349 device_t *pci_devices; 350 int pci_count = 0; 351 device_t *pci_children; 352 int pci_childcount = 0; 353 device_t *busp, *childp; 354 device_t child = NULL; 355 int i, j; 356 357 if ((pci_devclass = devclass_find("pci")) == NULL) 358 return (NULL); 359 360 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 361 362 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 363 if (device_get_children(*busp, &pci_children, &pci_childcount)) 364 continue; 365 for (j = 0, childp = pci_children; 366 j < pci_childcount; j++, childp++) { 367 if (pci_get_vendor(*childp) == SIS_VENDORID && 368 pci_get_device(*childp) == 0x0008) { 369 child = *childp; 370 free(pci_children, M_TEMP); 371 goto done; 372 } 373 } 374 free(pci_children, M_TEMP); 375 } 376 377done: 378 free(pci_devices, M_TEMP); 379 return (child); 380} 381 382static void 383sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 384{ 385 device_t bridge; 386 uint8_t reg; 387 int i; 388 bus_space_tag_t btag; 389 390 bridge = sis_find_bridge(dev); 391 if (bridge == NULL) 392 return; 393 reg = pci_read_config(bridge, 0x48, 1); 394 pci_write_config(bridge, 0x48, reg|0x40, 1); 395 396 /* XXX */ 397#if defined(__amd64__) || defined(__i386__) 398 btag = X86_BUS_SPACE_IO; 399#endif 400 401 for (i = 0; i < cnt; i++) { 402 bus_space_write_1(btag, 0x0, 0x70, i + off); 403 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 404 } 405 406 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 407} 408 409static void 410sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 411{ 412 uint32_t filtsave, csrsave; 413 414 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 415 csrsave = CSR_READ_4(sc, SIS_CSR); 416 417 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 418 CSR_WRITE_4(sc, SIS_CSR, 0); 419 420 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 421 422 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 423 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 424 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 425 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 426 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 427 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 428 429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 430 CSR_WRITE_4(sc, SIS_CSR, csrsave); 431} 432#endif 433 434/* 435 * Read the MII serial port for the MII bit-bang module. 436 */ 437static uint32_t 438sis_mii_bitbang_read(device_t dev) 439{ 440 struct sis_softc *sc; 441 uint32_t val; 442 443 sc = device_get_softc(dev); 444 445 val = CSR_READ_4(sc, SIS_EECTL); 446 CSR_BARRIER(sc, SIS_EECTL, 4, 447 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 448 return (val); 449} 450 451/* 452 * Write the MII serial port for the MII bit-bang module. 453 */ 454static void 455sis_mii_bitbang_write(device_t dev, uint32_t val) 456{ 457 struct sis_softc *sc; 458 459 sc = device_get_softc(dev); 460 461 CSR_WRITE_4(sc, SIS_EECTL, val); 462 CSR_BARRIER(sc, SIS_EECTL, 4, 463 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 464} 465 466static int 467sis_miibus_readreg(device_t dev, int phy, int reg) 468{ 469 struct sis_softc *sc; 470 471 sc = device_get_softc(dev); 472 473 if (sc->sis_type == SIS_TYPE_83815) { 474 if (phy != 0) 475 return (0); 476 /* 477 * The NatSemi chip can take a while after 478 * a reset to come ready, during which the BMSR 479 * returns a value of 0. This is *never* supposed 480 * to happen: some of the BMSR bits are meant to 481 * be hardwired in the on position, and this can 482 * confuse the miibus code a bit during the probe 483 * and attach phase. So we make an effort to check 484 * for this condition and wait for it to clear. 485 */ 486 if (!CSR_READ_4(sc, NS_BMSR)) 487 DELAY(1000); 488 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 489 } 490 491 /* 492 * Chipsets < SIS_635 seem not to be able to read/write 493 * through mdio. Use the enhanced PHY access register 494 * again for them. 495 */ 496 if (sc->sis_type == SIS_TYPE_900 && 497 sc->sis_rev < SIS_REV_635) { 498 int i, val = 0; 499 500 if (phy != 0) 501 return (0); 502 503 CSR_WRITE_4(sc, SIS_PHYCTL, 504 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 505 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 506 507 for (i = 0; i < SIS_TIMEOUT; i++) { 508 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 509 break; 510 } 511 512 if (i == SIS_TIMEOUT) { 513 device_printf(sc->sis_dev, 514 "PHY failed to come ready\n"); 515 return (0); 516 } 517 518 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 519 520 if (val == 0xFFFF) 521 return (0); 522 523 return (val); 524 } else 525 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy, 526 reg)); 527} 528 529static int 530sis_miibus_writereg(device_t dev, int phy, int reg, int data) 531{ 532 struct sis_softc *sc; 533 534 sc = device_get_softc(dev); 535 536 if (sc->sis_type == SIS_TYPE_83815) { 537 if (phy != 0) 538 return (0); 539 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 540 return (0); 541 } 542 543 /* 544 * Chipsets < SIS_635 seem not to be able to read/write 545 * through mdio. Use the enhanced PHY access register 546 * again for them. 547 */ 548 if (sc->sis_type == SIS_TYPE_900 && 549 sc->sis_rev < SIS_REV_635) { 550 int i; 551 552 if (phy != 0) 553 return (0); 554 555 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 556 (reg << 6) | SIS_PHYOP_WRITE); 557 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 558 559 for (i = 0; i < SIS_TIMEOUT; i++) { 560 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 561 break; 562 } 563 564 if (i == SIS_TIMEOUT) 565 device_printf(sc->sis_dev, 566 "PHY failed to come ready\n"); 567 } else 568 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg, 569 data); 570 return (0); 571} 572 573static void 574sis_miibus_statchg(device_t dev) 575{ 576 struct sis_softc *sc; 577 struct mii_data *mii; 578 struct ifnet *ifp; 579 uint32_t reg; 580 581 sc = device_get_softc(dev); 582 SIS_LOCK_ASSERT(sc); 583 584 mii = device_get_softc(sc->sis_miibus); 585 ifp = sc->sis_ifp; 586 if (mii == NULL || ifp == NULL || 587 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 588 return; 589 590 sc->sis_flags &= ~SIS_FLAG_LINK; 591 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 592 (IFM_ACTIVE | IFM_AVALID)) { 593 switch (IFM_SUBTYPE(mii->mii_media_active)) { 594 case IFM_10_T: 595 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 596 sc->sis_flags |= SIS_FLAG_LINK; 597 break; 598 case IFM_100_TX: 599 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 600 sc->sis_flags |= SIS_FLAG_LINK; 601 break; 602 default: 603 break; 604 } 605 } 606 607 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) { 608 /* 609 * Stopping MACs seem to reset SIS_TX_LISTPTR and 610 * SIS_RX_LISTPTR which in turn requires resetting 611 * TX/RX buffers. So just don't do anything for 612 * lost link. 613 */ 614 return; 615 } 616 617 /* Set full/half duplex mode. */ 618 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 619 SIS_SETBIT(sc, SIS_TX_CFG, 620 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 621 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 622 } else { 623 SIS_CLRBIT(sc, SIS_TX_CFG, 624 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 625 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 626 } 627 628 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 629 /* 630 * MPII03.D: Half Duplex Excessive Collisions. 631 * Also page 49 in 83816 manual 632 */ 633 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 634 } 635 636 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 637 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 638 /* 639 * Short Cable Receive Errors (MP21.E) 640 */ 641 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 642 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 643 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 644 DELAY(100); 645 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 646 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 647 device_printf(sc->sis_dev, 648 "Applying short cable fix (reg=%x)\n", reg); 649 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 650 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 651 } 652 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 653 } 654 /* Enable TX/RX MACs. */ 655 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 656 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE); 657} 658 659static uint32_t 660sis_mchash(struct sis_softc *sc, const uint8_t *addr) 661{ 662 uint32_t crc; 663 664 /* Compute CRC for the address value. */ 665 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 666 667 /* 668 * return the filter bit position 669 * 670 * The NatSemi chip has a 512-bit filter, which is 671 * different than the SiS, so we special-case it. 672 */ 673 if (sc->sis_type == SIS_TYPE_83815) 674 return (crc >> 23); 675 else if (sc->sis_rev >= SIS_REV_635 || 676 sc->sis_rev == SIS_REV_900B) 677 return (crc >> 24); 678 else 679 return (crc >> 25); 680} 681 682static void 683sis_rxfilter(struct sis_softc *sc) 684{ 685 686 SIS_LOCK_ASSERT(sc); 687 688 if (sc->sis_type == SIS_TYPE_83815) 689 sis_rxfilter_ns(sc); 690 else 691 sis_rxfilter_sis(sc); 692} 693 694static void 695sis_rxfilter_ns(struct sis_softc *sc) 696{ 697 struct ifnet *ifp; 698 struct ifmultiaddr *ifma; 699 uint32_t h, i, filter; 700 int bit, index; 701 702 ifp = sc->sis_ifp; 703 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 704 if (filter & SIS_RXFILTCTL_ENABLE) { 705 /* 706 * Filter should be disabled to program other bits. 707 */ 708 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 709 CSR_READ_4(sc, SIS_RXFILT_CTL); 710 } 711 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT | 712 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 713 SIS_RXFILTCTL_ALLMULTI); 714 715 if (ifp->if_flags & IFF_BROADCAST) 716 filter |= SIS_RXFILTCTL_BROAD; 717 /* 718 * For the NatSemi chip, we have to explicitly enable the 719 * reception of ARP frames, as well as turn on the 'perfect 720 * match' filter where we store the station address, otherwise 721 * we won't receive unicasts meant for this host. 722 */ 723 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT; 724 725 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 726 filter |= SIS_RXFILTCTL_ALLMULTI; 727 if (ifp->if_flags & IFF_PROMISC) 728 filter |= SIS_RXFILTCTL_ALLPHYS; 729 } else { 730 /* 731 * We have to explicitly enable the multicast hash table 732 * on the NatSemi chip if we want to use it, which we do. 733 */ 734 filter |= NS_RXFILTCTL_MCHASH; 735 736 /* first, zot all the existing hash bits */ 737 for (i = 0; i < 32; i++) { 738 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 739 (i * 2)); 740 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 741 } 742 743 if_maddr_rlock(ifp); 744 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 745 if (ifma->ifma_addr->sa_family != AF_LINK) 746 continue; 747 h = sis_mchash(sc, 748 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 749 index = h >> 3; 750 bit = h & 0x1F; 751 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 752 index); 753 if (bit > 0xF) 754 bit -= 0x10; 755 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 756 } 757 if_maddr_runlock(ifp); 758 } 759 760 /* Turn the receive filter on */ 761 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE); 762 CSR_READ_4(sc, SIS_RXFILT_CTL); 763} 764 765static void 766sis_rxfilter_sis(struct sis_softc *sc) 767{ 768 struct ifnet *ifp; 769 struct ifmultiaddr *ifma; 770 uint32_t filter, h, i, n; 771 uint16_t hashes[16]; 772 773 ifp = sc->sis_ifp; 774 775 /* hash table size */ 776 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 777 n = 16; 778 else 779 n = 8; 780 781 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 782 if (filter & SIS_RXFILTCTL_ENABLE) { 783 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 784 CSR_READ_4(sc, SIS_RXFILT_CTL); 785 } 786 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 787 SIS_RXFILTCTL_ALLMULTI); 788 if (ifp->if_flags & IFF_BROADCAST) 789 filter |= SIS_RXFILTCTL_BROAD; 790 791 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 792 filter |= SIS_RXFILTCTL_ALLMULTI; 793 if (ifp->if_flags & IFF_PROMISC) 794 filter |= SIS_RXFILTCTL_ALLPHYS; 795 for (i = 0; i < n; i++) 796 hashes[i] = ~0; 797 } else { 798 for (i = 0; i < n; i++) 799 hashes[i] = 0; 800 i = 0; 801 if_maddr_rlock(ifp); 802 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 803 if (ifma->ifma_addr->sa_family != AF_LINK) 804 continue; 805 h = sis_mchash(sc, 806 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 807 hashes[h >> 4] |= 1 << (h & 0xf); 808 i++; 809 } 810 if_maddr_runlock(ifp); 811 if (i > n) { 812 filter |= SIS_RXFILTCTL_ALLMULTI; 813 for (i = 0; i < n; i++) 814 hashes[i] = ~0; 815 } 816 } 817 818 for (i = 0; i < n; i++) { 819 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 820 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 821 } 822 823 /* Turn the receive filter on */ 824 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE); 825 CSR_READ_4(sc, SIS_RXFILT_CTL); 826} 827 828static void 829sis_reset(struct sis_softc *sc) 830{ 831 int i; 832 833 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 834 835 for (i = 0; i < SIS_TIMEOUT; i++) { 836 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 837 break; 838 } 839 840 if (i == SIS_TIMEOUT) 841 device_printf(sc->sis_dev, "reset never completed\n"); 842 843 /* Wait a little while for the chip to get its brains in order. */ 844 DELAY(1000); 845 846 /* 847 * If this is a NetSemi chip, make sure to clear 848 * PME mode. 849 */ 850 if (sc->sis_type == SIS_TYPE_83815) { 851 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 852 CSR_WRITE_4(sc, NS_CLKRUN, 0); 853 } else { 854 /* Disable WOL functions. */ 855 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0); 856 } 857} 858 859/* 860 * Probe for an SiS chip. Check the PCI vendor and device 861 * IDs against our list and return a device name if we find a match. 862 */ 863static int 864sis_probe(device_t dev) 865{ 866 const struct sis_type *t; 867 868 t = sis_devs; 869 870 while (t->sis_name != NULL) { 871 if ((pci_get_vendor(dev) == t->sis_vid) && 872 (pci_get_device(dev) == t->sis_did)) { 873 device_set_desc(dev, t->sis_name); 874 return (BUS_PROBE_DEFAULT); 875 } 876 t++; 877 } 878 879 return (ENXIO); 880} 881 882/* 883 * Attach the interface. Allocate softc structures, do ifmedia 884 * setup and ethernet/BPF attach. 885 */ 886static int 887sis_attach(device_t dev) 888{ 889 u_char eaddr[ETHER_ADDR_LEN]; 890 struct sis_softc *sc; 891 struct ifnet *ifp; 892 int error = 0, pmc, waittime = 0; 893 894 waittime = 0; 895 sc = device_get_softc(dev); 896 897 sc->sis_dev = dev; 898 899 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 900 MTX_DEF); 901 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 902 903 if (pci_get_device(dev) == SIS_DEVICEID_900) 904 sc->sis_type = SIS_TYPE_900; 905 if (pci_get_device(dev) == SIS_DEVICEID_7016) 906 sc->sis_type = SIS_TYPE_7016; 907 if (pci_get_vendor(dev) == NS_VENDORID) 908 sc->sis_type = SIS_TYPE_83815; 909 910 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 911 /* 912 * Map control/status registers. 913 */ 914 pci_enable_busmaster(dev); 915 916 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 917 if (error) { 918 device_printf(dev, "couldn't allocate resources\n"); 919 goto fail; 920 } 921 922 /* Reset the adapter. */ 923 sis_reset(sc); 924 925 if (sc->sis_type == SIS_TYPE_900 && 926 (sc->sis_rev == SIS_REV_635 || 927 sc->sis_rev == SIS_REV_900B)) { 928 SIO_SET(SIS_CFG_RND_CNT); 929 SIO_SET(SIS_CFG_PERR_DETECT); 930 } 931 932 /* 933 * Get station address from the EEPROM. 934 */ 935 switch (pci_get_vendor(dev)) { 936 case NS_VENDORID: 937 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 938 939 /* We can't update the device description, so spew */ 940 if (sc->sis_srr == NS_SRR_15C) 941 device_printf(dev, "Silicon Revision: DP83815C\n"); 942 else if (sc->sis_srr == NS_SRR_15D) 943 device_printf(dev, "Silicon Revision: DP83815D\n"); 944 else if (sc->sis_srr == NS_SRR_16A) 945 device_printf(dev, "Silicon Revision: DP83816A\n"); 946 else 947 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 948 949 /* 950 * Reading the MAC address out of the EEPROM on 951 * the NatSemi chip takes a bit more work than 952 * you'd expect. The address spans 4 16-bit words, 953 * with the first word containing only a single bit. 954 * You have to shift everything over one bit to 955 * get it aligned properly. Also, the bits are 956 * stored backwards (the LSB is really the MSB, 957 * and so on) so you have to reverse them in order 958 * to get the MAC address into the form we want. 959 * Why? Who the hell knows. 960 */ 961 { 962 uint16_t tmp[4]; 963 964 sis_read_eeprom(sc, (caddr_t)&tmp, 965 NS_EE_NODEADDR, 4, 0); 966 967 /* Shift everything over one bit. */ 968 tmp[3] = tmp[3] >> 1; 969 tmp[3] |= tmp[2] << 15; 970 tmp[2] = tmp[2] >> 1; 971 tmp[2] |= tmp[1] << 15; 972 tmp[1] = tmp[1] >> 1; 973 tmp[1] |= tmp[0] << 15; 974 975 /* Now reverse all the bits. */ 976 tmp[3] = sis_reverse(tmp[3]); 977 tmp[2] = sis_reverse(tmp[2]); 978 tmp[1] = sis_reverse(tmp[1]); 979 980 eaddr[0] = (tmp[1] >> 0) & 0xFF; 981 eaddr[1] = (tmp[1] >> 8) & 0xFF; 982 eaddr[2] = (tmp[2] >> 0) & 0xFF; 983 eaddr[3] = (tmp[2] >> 8) & 0xFF; 984 eaddr[4] = (tmp[3] >> 0) & 0xFF; 985 eaddr[5] = (tmp[3] >> 8) & 0xFF; 986 } 987 break; 988 case SIS_VENDORID: 989 default: 990#if defined(__i386__) || defined(__amd64__) 991 /* 992 * If this is a SiS 630E chipset with an embedded 993 * SiS 900 controller, we have to read the MAC address 994 * from the APC CMOS RAM. Our method for doing this 995 * is very ugly since we have to reach out and grab 996 * ahold of hardware for which we cannot properly 997 * allocate resources. This code is only compiled on 998 * the i386 architecture since the SiS 630E chipset 999 * is for x86 motherboards only. Note that there are 1000 * a lot of magic numbers in this hack. These are 1001 * taken from SiS's Linux driver. I'd like to replace 1002 * them with proper symbolic definitions, but that 1003 * requires some datasheets that I don't have access 1004 * to at the moment. 1005 */ 1006 if (sc->sis_rev == SIS_REV_630S || 1007 sc->sis_rev == SIS_REV_630E || 1008 sc->sis_rev == SIS_REV_630EA1) 1009 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1010 1011 else if (sc->sis_rev == SIS_REV_635 || 1012 sc->sis_rev == SIS_REV_630ET) 1013 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1014 else if (sc->sis_rev == SIS_REV_96x) { 1015 /* Allow to read EEPROM from LAN. It is shared 1016 * between a 1394 controller and the NIC and each 1017 * time we access it, we need to set SIS_EECMD_REQ. 1018 */ 1019 SIO_SET(SIS_EECMD_REQ); 1020 for (waittime = 0; waittime < SIS_TIMEOUT; 1021 waittime++) { 1022 /* Force EEPROM to idle state. */ 1023 sis_eeprom_idle(sc); 1024 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1025 sis_read_eeprom(sc, (caddr_t)&eaddr, 1026 SIS_EE_NODEADDR, 3, 0); 1027 break; 1028 } 1029 DELAY(1); 1030 } 1031 /* 1032 * Set SIS_EECTL_CLK to high, so a other master 1033 * can operate on the i2c bus. 1034 */ 1035 SIO_SET(SIS_EECTL_CLK); 1036 /* Refuse EEPROM access by LAN */ 1037 SIO_SET(SIS_EECMD_DONE); 1038 } else 1039#endif 1040 sis_read_eeprom(sc, (caddr_t)&eaddr, 1041 SIS_EE_NODEADDR, 3, 0); 1042 break; 1043 } 1044 1045 sis_add_sysctls(sc); 1046 1047 /* Allocate DMA'able memory. */ 1048 if ((error = sis_dma_alloc(sc)) != 0) 1049 goto fail; 1050 1051 ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1052 if (ifp == NULL) { 1053 device_printf(dev, "can not if_alloc()\n"); 1054 error = ENOSPC; 1055 goto fail; 1056 } 1057 ifp->if_softc = sc; 1058 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1059 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1060 ifp->if_ioctl = sis_ioctl; 1061 ifp->if_start = sis_start; 1062 ifp->if_init = sis_init; 1063 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1064 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1065 IFQ_SET_READY(&ifp->if_snd); 1066 1067 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { 1068 if (sc->sis_type == SIS_TYPE_83815) 1069 ifp->if_capabilities |= IFCAP_WOL; 1070 else 1071 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1072 ifp->if_capenable = ifp->if_capabilities; 1073 } 1074 1075 /* 1076 * Do MII setup. 1077 */ 1078 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd, 1079 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1080 if (error != 0) { 1081 device_printf(dev, "attaching PHYs failed\n"); 1082 goto fail; 1083 } 1084 1085 /* 1086 * Call MI attach routine. 1087 */ 1088 ether_ifattach(ifp, eaddr); 1089 1090 /* 1091 * Tell the upper layer(s) we support long frames. 1092 */ 1093 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1094 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1095 ifp->if_capenable = ifp->if_capabilities; 1096#ifdef DEVICE_POLLING 1097 ifp->if_capabilities |= IFCAP_POLLING; 1098#endif 1099 1100 /* Hook interrupt last to avoid having to lock softc */ 1101 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1102 NULL, sis_intr, sc, &sc->sis_intrhand); 1103 1104 if (error) { 1105 device_printf(dev, "couldn't set up irq\n"); 1106 ether_ifdetach(ifp); 1107 goto fail; 1108 } 1109 1110fail: 1111 if (error) 1112 sis_detach(dev); 1113 1114 return (error); 1115} 1116 1117/* 1118 * Shutdown hardware and free up resources. This can be called any 1119 * time after the mutex has been initialized. It is called in both 1120 * the error case in attach and the normal detach case so it needs 1121 * to be careful about only freeing resources that have actually been 1122 * allocated. 1123 */ 1124static int 1125sis_detach(device_t dev) 1126{ 1127 struct sis_softc *sc; 1128 struct ifnet *ifp; 1129 1130 sc = device_get_softc(dev); 1131 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1132 ifp = sc->sis_ifp; 1133 1134#ifdef DEVICE_POLLING 1135 if (ifp->if_capenable & IFCAP_POLLING) 1136 ether_poll_deregister(ifp); 1137#endif 1138 1139 /* These should only be active if attach succeeded. */ 1140 if (device_is_attached(dev)) { 1141 SIS_LOCK(sc); 1142 sis_stop(sc); 1143 SIS_UNLOCK(sc); 1144 callout_drain(&sc->sis_stat_ch); 1145 ether_ifdetach(ifp); 1146 } 1147 if (sc->sis_miibus) 1148 device_delete_child(dev, sc->sis_miibus); 1149 bus_generic_detach(dev); 1150 1151 if (sc->sis_intrhand) 1152 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1153 bus_release_resources(dev, sis_res_spec, sc->sis_res); 1154 1155 if (ifp) 1156 if_free(ifp); 1157 1158 sis_dma_free(sc); 1159 1160 mtx_destroy(&sc->sis_mtx); 1161 1162 return (0); 1163} 1164 1165struct sis_dmamap_arg { 1166 bus_addr_t sis_busaddr; 1167}; 1168 1169static void 1170sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1171{ 1172 struct sis_dmamap_arg *ctx; 1173 1174 if (error != 0) 1175 return; 1176 1177 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1178 1179 ctx = (struct sis_dmamap_arg *)arg; 1180 ctx->sis_busaddr = segs[0].ds_addr; 1181} 1182 1183static int 1184sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment, 1185 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 1186 bus_addr_t *paddr, const char *msg) 1187{ 1188 struct sis_dmamap_arg ctx; 1189 int error; 1190 1191 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0, 1192 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, 1193 maxsize, 0, NULL, NULL, tag); 1194 if (error != 0) { 1195 device_printf(sc->sis_dev, 1196 "could not create %s dma tag\n", msg); 1197 return (ENOMEM); 1198 } 1199 /* Allocate DMA'able memory for ring. */ 1200 error = bus_dmamem_alloc(*tag, (void **)ring, 1201 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1202 if (error != 0) { 1203 device_printf(sc->sis_dev, 1204 "could not allocate DMA'able memory for %s\n", msg); 1205 return (ENOMEM); 1206 } 1207 /* Load the address of the ring. */ 1208 ctx.sis_busaddr = 0; 1209 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb, 1210 &ctx, BUS_DMA_NOWAIT); 1211 if (error != 0) { 1212 device_printf(sc->sis_dev, 1213 "could not load DMA'able memory for %s\n", msg); 1214 return (ENOMEM); 1215 } 1216 *paddr = ctx.sis_busaddr; 1217 return (0); 1218} 1219 1220static int 1221sis_dma_alloc(struct sis_softc *sc) 1222{ 1223 struct sis_rxdesc *rxd; 1224 struct sis_txdesc *txd; 1225 int error, i; 1226 1227 /* Allocate the parent bus DMA tag appropriate for PCI. */ 1228 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev), 1229 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1230 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 1231 0, NULL, NULL, &sc->sis_parent_tag); 1232 if (error != 0) { 1233 device_printf(sc->sis_dev, 1234 "could not allocate parent dma tag\n"); 1235 return (ENOMEM); 1236 } 1237 1238 /* Create RX ring. */ 1239 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ, 1240 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list, 1241 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring"); 1242 if (error) 1243 return (error); 1244 1245 /* Create TX ring. */ 1246 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ, 1247 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list, 1248 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring"); 1249 if (error) 1250 return (error); 1251 1252 /* Create tag for RX mbufs. */ 1253 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0, 1254 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1255 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag); 1256 if (error) { 1257 device_printf(sc->sis_dev, "could not allocate RX dma tag\n"); 1258 return (error); 1259 } 1260 1261 /* Create tag for TX mbufs. */ 1262 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0, 1263 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1264 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1265 &sc->sis_tx_tag); 1266 if (error) { 1267 device_printf(sc->sis_dev, "could not allocate TX dma tag\n"); 1268 return (error); 1269 } 1270 1271 /* Create DMA maps for RX buffers. */ 1272 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap); 1273 if (error) { 1274 device_printf(sc->sis_dev, 1275 "can't create spare DMA map for RX\n"); 1276 return (error); 1277 } 1278 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1279 rxd = &sc->sis_rxdesc[i]; 1280 rxd->rx_m = NULL; 1281 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap); 1282 if (error) { 1283 device_printf(sc->sis_dev, 1284 "can't create DMA map for RX\n"); 1285 return (error); 1286 } 1287 } 1288 1289 /* Create DMA maps for TX buffers. */ 1290 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1291 txd = &sc->sis_txdesc[i]; 1292 txd->tx_m = NULL; 1293 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap); 1294 if (error) { 1295 device_printf(sc->sis_dev, 1296 "can't create DMA map for TX\n"); 1297 return (error); 1298 } 1299 } 1300 1301 return (0); 1302} 1303 1304static void 1305sis_dma_free(struct sis_softc *sc) 1306{ 1307 struct sis_rxdesc *rxd; 1308 struct sis_txdesc *txd; 1309 int i; 1310 1311 /* Destroy DMA maps for RX buffers. */ 1312 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1313 rxd = &sc->sis_rxdesc[i]; 1314 if (rxd->rx_dmamap) 1315 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap); 1316 } 1317 if (sc->sis_rx_sparemap) 1318 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap); 1319 1320 /* Destroy DMA maps for TX buffers. */ 1321 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1322 txd = &sc->sis_txdesc[i]; 1323 if (txd->tx_dmamap) 1324 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap); 1325 } 1326 1327 if (sc->sis_rx_tag) 1328 bus_dma_tag_destroy(sc->sis_rx_tag); 1329 if (sc->sis_tx_tag) 1330 bus_dma_tag_destroy(sc->sis_tx_tag); 1331 1332 /* Destroy RX ring. */ 1333 if (sc->sis_rx_list_map) 1334 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map); 1335 if (sc->sis_rx_list_map && sc->sis_rx_list) 1336 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list, 1337 sc->sis_rx_list_map); 1338 1339 if (sc->sis_rx_list_tag) 1340 bus_dma_tag_destroy(sc->sis_rx_list_tag); 1341 1342 /* Destroy TX ring. */ 1343 if (sc->sis_tx_list_map) 1344 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map); 1345 1346 if (sc->sis_tx_list_map && sc->sis_tx_list) 1347 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list, 1348 sc->sis_tx_list_map); 1349 1350 if (sc->sis_tx_list_tag) 1351 bus_dma_tag_destroy(sc->sis_tx_list_tag); 1352 1353 /* Destroy the parent tag. */ 1354 if (sc->sis_parent_tag) 1355 bus_dma_tag_destroy(sc->sis_parent_tag); 1356} 1357 1358/* 1359 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1360 * we arrange the descriptors in a closed ring, so that the last descriptor 1361 * points back to the first. 1362 */ 1363static int 1364sis_ring_init(struct sis_softc *sc) 1365{ 1366 struct sis_rxdesc *rxd; 1367 struct sis_txdesc *txd; 1368 bus_addr_t next; 1369 int error, i; 1370 1371 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ); 1372 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1373 txd = &sc->sis_txdesc[i]; 1374 txd->tx_m = NULL; 1375 if (i == SIS_TX_LIST_CNT - 1) 1376 next = SIS_TX_RING_ADDR(sc, 0); 1377 else 1378 next = SIS_TX_RING_ADDR(sc, i + 1); 1379 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next)); 1380 } 1381 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1382 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1383 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1384 1385 sc->sis_rx_cons = 0; 1386 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ); 1387 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1388 rxd = &sc->sis_rxdesc[i]; 1389 rxd->rx_desc = &sc->sis_rx_list[i]; 1390 if (i == SIS_RX_LIST_CNT - 1) 1391 next = SIS_RX_RING_ADDR(sc, 0); 1392 else 1393 next = SIS_RX_RING_ADDR(sc, i + 1); 1394 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next)); 1395 error = sis_newbuf(sc, rxd); 1396 if (error) 1397 return (error); 1398 } 1399 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1400 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1401 1402 return (0); 1403} 1404 1405/* 1406 * Initialize an RX descriptor and attach an MBUF cluster. 1407 */ 1408static int 1409sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd) 1410{ 1411 struct mbuf *m; 1412 bus_dma_segment_t segs[1]; 1413 bus_dmamap_t map; 1414 int nsegs; 1415 1416 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1417 if (m == NULL) 1418 return (ENOBUFS); 1419 m->m_len = m->m_pkthdr.len = SIS_RXLEN; 1420#ifndef __NO_STRICT_ALIGNMENT 1421 m_adj(m, SIS_RX_BUF_ALIGN); 1422#endif 1423 1424 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m, 1425 segs, &nsegs, 0) != 0) { 1426 m_freem(m); 1427 return (ENOBUFS); 1428 } 1429 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1430 1431 if (rxd->rx_m != NULL) { 1432 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 1433 BUS_DMASYNC_POSTREAD); 1434 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 1435 } 1436 map = rxd->rx_dmamap; 1437 rxd->rx_dmamap = sc->sis_rx_sparemap; 1438 sc->sis_rx_sparemap = map; 1439 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); 1440 rxd->rx_m = m; 1441 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr)); 1442 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1443 return (0); 1444} 1445 1446static __inline void 1447sis_discard_rxbuf(struct sis_rxdesc *rxd) 1448{ 1449 1450 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1451} 1452 1453#ifndef __NO_STRICT_ALIGNMENT 1454static __inline void 1455sis_fixup_rx(struct mbuf *m) 1456{ 1457 uint16_t *src, *dst; 1458 int i; 1459 1460 src = mtod(m, uint16_t *); 1461 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src); 1462 1463 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1464 *dst++ = *src++; 1465 1466 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN; 1467} 1468#endif 1469 1470/* 1471 * A frame has been uploaded: pass the resulting mbuf chain up to 1472 * the higher level protocols. 1473 */ 1474static int 1475sis_rxeof(struct sis_softc *sc) 1476{ 1477 struct mbuf *m; 1478 struct ifnet *ifp; 1479 struct sis_rxdesc *rxd; 1480 struct sis_desc *cur_rx; 1481 int prog, rx_cons, rx_npkts = 0, total_len; 1482 uint32_t rxstat; 1483 1484 SIS_LOCK_ASSERT(sc); 1485 1486 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1487 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1488 1489 rx_cons = sc->sis_rx_cons; 1490 ifp = sc->sis_ifp; 1491 1492 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1493 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) { 1494#ifdef DEVICE_POLLING 1495 if (ifp->if_capenable & IFCAP_POLLING) { 1496 if (sc->rxcycles <= 0) 1497 break; 1498 sc->rxcycles--; 1499 } 1500#endif 1501 cur_rx = &sc->sis_rx_list[rx_cons]; 1502 rxstat = le32toh(cur_rx->sis_cmdsts); 1503 if ((rxstat & SIS_CMDSTS_OWN) == 0) 1504 break; 1505 rxd = &sc->sis_rxdesc[rx_cons]; 1506 1507 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN; 1508 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 && 1509 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - 1510 ETHER_CRC_LEN)) 1511 rxstat &= ~SIS_RXSTAT_GIANT; 1512 if (SIS_RXSTAT_ERROR(rxstat) != 0) { 1513 ifp->if_ierrors++; 1514 if (rxstat & SIS_RXSTAT_COLL) 1515 ifp->if_collisions++; 1516 sis_discard_rxbuf(rxd); 1517 continue; 1518 } 1519 1520 /* Add a new receive buffer to the ring. */ 1521 m = rxd->rx_m; 1522 if (sis_newbuf(sc, rxd) != 0) { 1523 ifp->if_iqdrops++; 1524 sis_discard_rxbuf(rxd); 1525 continue; 1526 } 1527 1528 /* No errors; receive the packet. */ 1529 m->m_pkthdr.len = m->m_len = total_len; 1530#ifndef __NO_STRICT_ALIGNMENT 1531 /* 1532 * On architectures without alignment problems we try to 1533 * allocate a new buffer for the receive ring, and pass up 1534 * the one where the packet is already, saving the expensive 1535 * copy operation. 1536 */ 1537 sis_fixup_rx(m); 1538#endif 1539 ifp->if_ipackets++; 1540 m->m_pkthdr.rcvif = ifp; 1541 1542 SIS_UNLOCK(sc); 1543 (*ifp->if_input)(ifp, m); 1544 SIS_LOCK(sc); 1545 rx_npkts++; 1546 } 1547 1548 if (prog > 0) { 1549 sc->sis_rx_cons = rx_cons; 1550 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1551 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1552 } 1553 1554 return (rx_npkts); 1555} 1556 1557/* 1558 * A frame was downloaded to the chip. It's safe for us to clean up 1559 * the list buffers. 1560 */ 1561 1562static void 1563sis_txeof(struct sis_softc *sc) 1564{ 1565 struct ifnet *ifp; 1566 struct sis_desc *cur_tx; 1567 struct sis_txdesc *txd; 1568 uint32_t cons, txstat; 1569 1570 SIS_LOCK_ASSERT(sc); 1571 1572 cons = sc->sis_tx_cons; 1573 if (cons == sc->sis_tx_prod) 1574 return; 1575 1576 ifp = sc->sis_ifp; 1577 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1578 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1579 1580 /* 1581 * Go through our tx list and free mbufs for those 1582 * frames that have been transmitted. 1583 */ 1584 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) { 1585 cur_tx = &sc->sis_tx_list[cons]; 1586 txstat = le32toh(cur_tx->sis_cmdsts); 1587 if ((txstat & SIS_CMDSTS_OWN) != 0) 1588 break; 1589 txd = &sc->sis_txdesc[cons]; 1590 if (txd->tx_m != NULL) { 1591 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 1592 BUS_DMASYNC_POSTWRITE); 1593 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1594 m_freem(txd->tx_m); 1595 txd->tx_m = NULL; 1596 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) { 1597 ifp->if_opackets++; 1598 ifp->if_collisions += 1599 (txstat & SIS_TXSTAT_COLLCNT) >> 16; 1600 } else { 1601 ifp->if_oerrors++; 1602 if (txstat & SIS_TXSTAT_EXCESSCOLLS) 1603 ifp->if_collisions++; 1604 if (txstat & SIS_TXSTAT_OUTOFWINCOLL) 1605 ifp->if_collisions++; 1606 } 1607 } 1608 sc->sis_tx_cnt--; 1609 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1610 } 1611 sc->sis_tx_cons = cons; 1612 if (sc->sis_tx_cnt == 0) 1613 sc->sis_watchdog_timer = 0; 1614} 1615 1616static void 1617sis_tick(void *xsc) 1618{ 1619 struct sis_softc *sc; 1620 struct mii_data *mii; 1621 1622 sc = xsc; 1623 SIS_LOCK_ASSERT(sc); 1624 1625 mii = device_get_softc(sc->sis_miibus); 1626 mii_tick(mii); 1627 sis_watchdog(sc); 1628 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) 1629 sis_miibus_statchg(sc->sis_dev); 1630 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1631} 1632 1633#ifdef DEVICE_POLLING 1634static poll_handler_t sis_poll; 1635 1636static int 1637sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1638{ 1639 struct sis_softc *sc = ifp->if_softc; 1640 int rx_npkts = 0; 1641 1642 SIS_LOCK(sc); 1643 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1644 SIS_UNLOCK(sc); 1645 return (rx_npkts); 1646 } 1647 1648 /* 1649 * On the sis, reading the status register also clears it. 1650 * So before returning to intr mode we must make sure that all 1651 * possible pending sources of interrupts have been served. 1652 * In practice this means run to completion the *eof routines, 1653 * and then call the interrupt routine 1654 */ 1655 sc->rxcycles = count; 1656 rx_npkts = sis_rxeof(sc); 1657 sis_txeof(sc); 1658 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1659 sis_startl(ifp); 1660 1661 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1662 uint32_t status; 1663 1664 /* Reading the ISR register clears all interrupts. */ 1665 status = CSR_READ_4(sc, SIS_ISR); 1666 1667 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1668 ifp->if_ierrors++; 1669 1670 if (status & (SIS_ISR_RX_IDLE)) 1671 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1672 1673 if (status & SIS_ISR_SYSERR) { 1674 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1675 sis_initl(sc); 1676 } 1677 } 1678 1679 SIS_UNLOCK(sc); 1680 return (rx_npkts); 1681} 1682#endif /* DEVICE_POLLING */ 1683 1684static void 1685sis_intr(void *arg) 1686{ 1687 struct sis_softc *sc; 1688 struct ifnet *ifp; 1689 uint32_t status; 1690 1691 sc = arg; 1692 ifp = sc->sis_ifp; 1693 1694 SIS_LOCK(sc); 1695#ifdef DEVICE_POLLING 1696 if (ifp->if_capenable & IFCAP_POLLING) { 1697 SIS_UNLOCK(sc); 1698 return; 1699 } 1700#endif 1701 1702 /* Reading the ISR register clears all interrupts. */ 1703 status = CSR_READ_4(sc, SIS_ISR); 1704 if ((status & SIS_INTRS) == 0) { 1705 /* Not ours. */ 1706 SIS_UNLOCK(sc); 1707 return; 1708 } 1709 1710 /* Disable interrupts. */ 1711 CSR_WRITE_4(sc, SIS_IER, 0); 1712 1713 for (;(status & SIS_INTRS) != 0;) { 1714 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1715 break; 1716 if (status & 1717 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1718 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1719 sis_txeof(sc); 1720 1721 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1722 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) 1723 sis_rxeof(sc); 1724 1725 if (status & SIS_ISR_RX_OFLOW) 1726 ifp->if_ierrors++; 1727 1728 if (status & (SIS_ISR_RX_IDLE)) 1729 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1730 1731 if (status & SIS_ISR_SYSERR) { 1732 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1733 sis_initl(sc); 1734 SIS_UNLOCK(sc); 1735 return; 1736 } 1737 status = CSR_READ_4(sc, SIS_ISR); 1738 } 1739 1740 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1741 /* Re-enable interrupts. */ 1742 CSR_WRITE_4(sc, SIS_IER, 1); 1743 1744 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1745 sis_startl(ifp); 1746 } 1747 1748 SIS_UNLOCK(sc); 1749} 1750 1751/* 1752 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1753 * pointers to the fragment pointers. 1754 */ 1755static int 1756sis_encap(struct sis_softc *sc, struct mbuf **m_head) 1757{ 1758 struct mbuf *m; 1759 struct sis_txdesc *txd; 1760 struct sis_desc *f; 1761 bus_dma_segment_t segs[SIS_MAXTXSEGS]; 1762 bus_dmamap_t map; 1763 int error, i, frag, nsegs, prod; 1764 int padlen; 1765 1766 prod = sc->sis_tx_prod; 1767 txd = &sc->sis_txdesc[prod]; 1768 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 && 1769 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) { 1770 m = *m_head; 1771 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len; 1772 if (M_WRITABLE(m) == 0) { 1773 /* Get a writable copy. */ 1774 m = m_dup(*m_head, M_NOWAIT); 1775 m_freem(*m_head); 1776 if (m == NULL) { 1777 *m_head = NULL; 1778 return (ENOBUFS); 1779 } 1780 *m_head = m; 1781 } 1782 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1783 m = m_defrag(m, M_NOWAIT); 1784 if (m == NULL) { 1785 m_freem(*m_head); 1786 *m_head = NULL; 1787 return (ENOBUFS); 1788 } 1789 } 1790 /* 1791 * Manually pad short frames, and zero the pad space 1792 * to avoid leaking data. 1793 */ 1794 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1795 m->m_pkthdr.len += padlen; 1796 m->m_len = m->m_pkthdr.len; 1797 *m_head = m; 1798 } 1799 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1800 *m_head, segs, &nsegs, 0); 1801 if (error == EFBIG) { 1802 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS); 1803 if (m == NULL) { 1804 m_freem(*m_head); 1805 *m_head = NULL; 1806 return (ENOBUFS); 1807 } 1808 *m_head = m; 1809 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1810 *m_head, segs, &nsegs, 0); 1811 if (error != 0) { 1812 m_freem(*m_head); 1813 *m_head = NULL; 1814 return (error); 1815 } 1816 } else if (error != 0) 1817 return (error); 1818 1819 /* Check for descriptor overruns. */ 1820 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) { 1821 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1822 return (ENOBUFS); 1823 } 1824 1825 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); 1826 1827 frag = prod; 1828 for (i = 0; i < nsegs; i++) { 1829 f = &sc->sis_tx_list[prod]; 1830 if (i == 0) 1831 f->sis_cmdsts = htole32(segs[i].ds_len | 1832 SIS_CMDSTS_MORE); 1833 else 1834 f->sis_cmdsts = htole32(segs[i].ds_len | 1835 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE); 1836 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr)); 1837 SIS_INC(prod, SIS_TX_LIST_CNT); 1838 sc->sis_tx_cnt++; 1839 } 1840 1841 /* Update producer index. */ 1842 sc->sis_tx_prod = prod; 1843 1844 /* Remove MORE flag on the last descriptor. */ 1845 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1); 1846 f = &sc->sis_tx_list[prod]; 1847 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE); 1848 1849 /* Lastly transfer ownership of packet to the controller. */ 1850 f = &sc->sis_tx_list[frag]; 1851 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN); 1852 1853 /* Swap the last and the first dmamaps. */ 1854 map = txd->tx_dmamap; 1855 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap; 1856 sc->sis_txdesc[prod].tx_dmamap = map; 1857 sc->sis_txdesc[prod].tx_m = *m_head; 1858 1859 return (0); 1860} 1861 1862static void 1863sis_start(struct ifnet *ifp) 1864{ 1865 struct sis_softc *sc; 1866 1867 sc = ifp->if_softc; 1868 SIS_LOCK(sc); 1869 sis_startl(ifp); 1870 SIS_UNLOCK(sc); 1871} 1872 1873static void 1874sis_startl(struct ifnet *ifp) 1875{ 1876 struct sis_softc *sc; 1877 struct mbuf *m_head; 1878 int queued; 1879 1880 sc = ifp->if_softc; 1881 1882 SIS_LOCK_ASSERT(sc); 1883 1884 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1885 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0) 1886 return; 1887 1888 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1889 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) { 1890 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1891 if (m_head == NULL) 1892 break; 1893 1894 if (sis_encap(sc, &m_head) != 0) { 1895 if (m_head == NULL) 1896 break; 1897 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1898 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1899 break; 1900 } 1901 1902 queued++; 1903 1904 /* 1905 * If there's a BPF listener, bounce a copy of this frame 1906 * to him. 1907 */ 1908 BPF_MTAP(ifp, m_head); 1909 } 1910 1911 if (queued) { 1912 /* Transmit */ 1913 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1914 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1915 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1916 1917 /* 1918 * Set a timeout in case the chip goes out to lunch. 1919 */ 1920 sc->sis_watchdog_timer = 5; 1921 } 1922} 1923 1924static void 1925sis_init(void *xsc) 1926{ 1927 struct sis_softc *sc = xsc; 1928 1929 SIS_LOCK(sc); 1930 sis_initl(sc); 1931 SIS_UNLOCK(sc); 1932} 1933 1934static void 1935sis_initl(struct sis_softc *sc) 1936{ 1937 struct ifnet *ifp = sc->sis_ifp; 1938 struct mii_data *mii; 1939 uint8_t *eaddr; 1940 1941 SIS_LOCK_ASSERT(sc); 1942 1943 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1944 return; 1945 1946 /* 1947 * Cancel pending I/O and free all RX/TX buffers. 1948 */ 1949 sis_stop(sc); 1950 /* 1951 * Reset the chip to a known state. 1952 */ 1953 sis_reset(sc); 1954#ifdef notyet 1955 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1956 /* 1957 * Configure 400usec of interrupt holdoff. This is based 1958 * on emperical tests on a Soekris 4801. 1959 */ 1960 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1961 } 1962#endif 1963 1964 mii = device_get_softc(sc->sis_miibus); 1965 1966 /* Set MAC address */ 1967 eaddr = IF_LLADDR(sc->sis_ifp); 1968 if (sc->sis_type == SIS_TYPE_83815) { 1969 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1970 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1971 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1972 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1973 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1974 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1975 } else { 1976 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1977 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1978 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1979 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1981 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1982 } 1983 1984 /* Init circular TX/RX lists. */ 1985 if (sis_ring_init(sc) != 0) { 1986 device_printf(sc->sis_dev, 1987 "initialization failed: no memory for rx buffers\n"); 1988 sis_stop(sc); 1989 return; 1990 } 1991 1992 if (sc->sis_type == SIS_TYPE_83815) { 1993 if (sc->sis_manual_pad != 0) 1994 sc->sis_flags |= SIS_FLAG_MANUAL_PAD; 1995 else 1996 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD; 1997 } 1998 1999 /* 2000 * Short Cable Receive Errors (MP21.E) 2001 * also: Page 78 of the DP83815 data sheet (september 2002 version) 2002 * recommends the following register settings "for optimum 2003 * performance." for rev 15C. Set this also for 15D parts as 2004 * they require it in practice. 2005 */ 2006 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 2007 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2008 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2009 /* set val for c2 */ 2010 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2011 /* load/kill c2 */ 2012 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2013 /* rais SD off, from 4 to c */ 2014 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2015 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2016 } 2017 2018 sis_rxfilter(sc); 2019 2020 /* 2021 * Load the address of the RX and TX lists. 2022 */ 2023 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr)); 2024 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr)); 2025 2026 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2027 * the PCI bus. When this bit is set, the Max DMA Burst Size 2028 * for TX/RX DMA should be no larger than 16 double words. 2029 */ 2030 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2031 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2032 } else { 2033 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2034 } 2035 2036 /* Accept Long Packets for VLAN support */ 2037 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2038 2039 /* 2040 * Assume 100Mbps link, actual MAC configuration is done 2041 * after getting a valid link. 2042 */ 2043 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2044 2045 /* 2046 * Enable interrupts. 2047 */ 2048 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2049#ifdef DEVICE_POLLING 2050 /* 2051 * ... only enable interrupts if we are not polling, make sure 2052 * they are off otherwise. 2053 */ 2054 if (ifp->if_capenable & IFCAP_POLLING) 2055 CSR_WRITE_4(sc, SIS_IER, 0); 2056 else 2057#endif 2058 CSR_WRITE_4(sc, SIS_IER, 1); 2059 2060 /* Clear MAC disable. */ 2061 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 2062 2063 sc->sis_flags &= ~SIS_FLAG_LINK; 2064 mii_mediachg(mii); 2065 2066 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2067 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2068 2069 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2070} 2071 2072/* 2073 * Set media options. 2074 */ 2075static int 2076sis_ifmedia_upd(struct ifnet *ifp) 2077{ 2078 struct sis_softc *sc; 2079 struct mii_data *mii; 2080 struct mii_softc *miisc; 2081 int error; 2082 2083 sc = ifp->if_softc; 2084 2085 SIS_LOCK(sc); 2086 mii = device_get_softc(sc->sis_miibus); 2087 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2088 PHY_RESET(miisc); 2089 error = mii_mediachg(mii); 2090 SIS_UNLOCK(sc); 2091 2092 return (error); 2093} 2094 2095/* 2096 * Report current media status. 2097 */ 2098static void 2099sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2100{ 2101 struct sis_softc *sc; 2102 struct mii_data *mii; 2103 2104 sc = ifp->if_softc; 2105 2106 SIS_LOCK(sc); 2107 mii = device_get_softc(sc->sis_miibus); 2108 mii_pollstat(mii); 2109 ifmr->ifm_active = mii->mii_media_active; 2110 ifmr->ifm_status = mii->mii_media_status; 2111 SIS_UNLOCK(sc); 2112} 2113 2114static int 2115sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2116{ 2117 struct sis_softc *sc = ifp->if_softc; 2118 struct ifreq *ifr = (struct ifreq *) data; 2119 struct mii_data *mii; 2120 int error = 0, mask; 2121 2122 switch (command) { 2123 case SIOCSIFFLAGS: 2124 SIS_LOCK(sc); 2125 if (ifp->if_flags & IFF_UP) { 2126 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2127 ((ifp->if_flags ^ sc->sis_if_flags) & 2128 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2129 sis_rxfilter(sc); 2130 else 2131 sis_initl(sc); 2132 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2133 sis_stop(sc); 2134 sc->sis_if_flags = ifp->if_flags; 2135 SIS_UNLOCK(sc); 2136 break; 2137 case SIOCADDMULTI: 2138 case SIOCDELMULTI: 2139 SIS_LOCK(sc); 2140 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2141 sis_rxfilter(sc); 2142 SIS_UNLOCK(sc); 2143 break; 2144 case SIOCGIFMEDIA: 2145 case SIOCSIFMEDIA: 2146 mii = device_get_softc(sc->sis_miibus); 2147 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2148 break; 2149 case SIOCSIFCAP: 2150 SIS_LOCK(sc); 2151 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2152#ifdef DEVICE_POLLING 2153 if ((mask & IFCAP_POLLING) != 0 && 2154 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 2155 ifp->if_capenable ^= IFCAP_POLLING; 2156 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 2157 error = ether_poll_register(sis_poll, ifp); 2158 if (error != 0) { 2159 SIS_UNLOCK(sc); 2160 break; 2161 } 2162 /* Disable interrupts. */ 2163 CSR_WRITE_4(sc, SIS_IER, 0); 2164 } else { 2165 error = ether_poll_deregister(ifp); 2166 /* Enable interrupts. */ 2167 CSR_WRITE_4(sc, SIS_IER, 1); 2168 } 2169 } 2170#endif /* DEVICE_POLLING */ 2171 if ((mask & IFCAP_WOL) != 0 && 2172 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2173 if ((mask & IFCAP_WOL_UCAST) != 0) 2174 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2175 if ((mask & IFCAP_WOL_MCAST) != 0) 2176 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2177 if ((mask & IFCAP_WOL_MAGIC) != 0) 2178 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2179 } 2180 SIS_UNLOCK(sc); 2181 break; 2182 default: 2183 error = ether_ioctl(ifp, command, data); 2184 break; 2185 } 2186 2187 return (error); 2188} 2189 2190static void 2191sis_watchdog(struct sis_softc *sc) 2192{ 2193 2194 SIS_LOCK_ASSERT(sc); 2195 2196 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) 2197 return; 2198 2199 device_printf(sc->sis_dev, "watchdog timeout\n"); 2200 sc->sis_ifp->if_oerrors++; 2201 2202 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2203 sis_initl(sc); 2204 2205 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd)) 2206 sis_startl(sc->sis_ifp); 2207} 2208 2209/* 2210 * Stop the adapter and free any mbufs allocated to the 2211 * RX and TX lists. 2212 */ 2213static void 2214sis_stop(struct sis_softc *sc) 2215{ 2216 struct ifnet *ifp; 2217 struct sis_rxdesc *rxd; 2218 struct sis_txdesc *txd; 2219 int i; 2220 2221 SIS_LOCK_ASSERT(sc); 2222 2223 ifp = sc->sis_ifp; 2224 sc->sis_watchdog_timer = 0; 2225 2226 callout_stop(&sc->sis_stat_ch); 2227 2228 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2229 CSR_WRITE_4(sc, SIS_IER, 0); 2230 CSR_WRITE_4(sc, SIS_IMR, 0); 2231 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2232 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2233 DELAY(1000); 2234 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2235 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2236 2237 sc->sis_flags &= ~SIS_FLAG_LINK; 2238 2239 /* 2240 * Free data in the RX lists. 2241 */ 2242 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2243 rxd = &sc->sis_rxdesc[i]; 2244 if (rxd->rx_m != NULL) { 2245 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 2246 BUS_DMASYNC_POSTREAD); 2247 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 2248 m_freem(rxd->rx_m); 2249 rxd->rx_m = NULL; 2250 } 2251 } 2252 2253 /* 2254 * Free the TX list buffers. 2255 */ 2256 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2257 txd = &sc->sis_txdesc[i]; 2258 if (txd->tx_m != NULL) { 2259 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 2260 BUS_DMASYNC_POSTWRITE); 2261 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 2262 m_freem(txd->tx_m); 2263 txd->tx_m = NULL; 2264 } 2265 } 2266} 2267 2268/* 2269 * Stop all chip I/O so that the kernel's probe routines don't 2270 * get confused by errant DMAs when rebooting. 2271 */ 2272static int 2273sis_shutdown(device_t dev) 2274{ 2275 2276 return (sis_suspend(dev)); 2277} 2278 2279static int 2280sis_suspend(device_t dev) 2281{ 2282 struct sis_softc *sc; 2283 2284 sc = device_get_softc(dev); 2285 SIS_LOCK(sc); 2286 sis_stop(sc); 2287 sis_wol(sc); 2288 SIS_UNLOCK(sc); 2289 return (0); 2290} 2291 2292static int 2293sis_resume(device_t dev) 2294{ 2295 struct sis_softc *sc; 2296 struct ifnet *ifp; 2297 2298 sc = device_get_softc(dev); 2299 SIS_LOCK(sc); 2300 ifp = sc->sis_ifp; 2301 if ((ifp->if_flags & IFF_UP) != 0) { 2302 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2303 sis_initl(sc); 2304 } 2305 SIS_UNLOCK(sc); 2306 return (0); 2307} 2308 2309static void 2310sis_wol(struct sis_softc *sc) 2311{ 2312 struct ifnet *ifp; 2313 uint32_t val; 2314 uint16_t pmstat; 2315 int pmc; 2316 2317 ifp = sc->sis_ifp; 2318 if ((ifp->if_capenable & IFCAP_WOL) == 0) 2319 return; 2320 2321 if (sc->sis_type == SIS_TYPE_83815) { 2322 /* Reset RXDP. */ 2323 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2324 2325 /* Configure WOL events. */ 2326 CSR_READ_4(sc, NS_WCSR); 2327 val = 0; 2328 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2329 val |= NS_WCSR_WAKE_UCAST; 2330 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2331 val |= NS_WCSR_WAKE_MCAST; 2332 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2333 val |= NS_WCSR_WAKE_MAGIC; 2334 CSR_WRITE_4(sc, NS_WCSR, val); 2335 /* Enable PME and clear PMESTS. */ 2336 val = CSR_READ_4(sc, NS_CLKRUN); 2337 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS; 2338 CSR_WRITE_4(sc, NS_CLKRUN, val); 2339 /* Enable silent RX mode. */ 2340 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2341 } else { 2342 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0) 2343 return; 2344 val = 0; 2345 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2346 val |= SIS_PWRMAN_WOL_MAGIC; 2347 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val); 2348 /* Request PME. */ 2349 pmstat = pci_read_config(sc->sis_dev, 2350 pmc + PCIR_POWER_STATUS, 2); 2351 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2352 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2353 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2354 pci_write_config(sc->sis_dev, 2355 pmc + PCIR_POWER_STATUS, pmstat, 2); 2356 } 2357} 2358 2359static void 2360sis_add_sysctls(struct sis_softc *sc) 2361{ 2362 struct sysctl_ctx_list *ctx; 2363 struct sysctl_oid_list *children; 2364 char tn[32]; 2365 int unit; 2366 2367 ctx = device_get_sysctl_ctx(sc->sis_dev); 2368 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev)); 2369 2370 unit = device_get_unit(sc->sis_dev); 2371 /* 2372 * Unlike most other controllers, NS DP83815/DP83816 controllers 2373 * seem to pad with 0xFF when it encounter short frames. According 2374 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable 2375 * on will have driver pad manully but it's disabled by default 2376 * because it will consume extra CPU cycles for short frames. 2377 */ 2378 sc->sis_manual_pad = 0; 2379 snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit); 2380 TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad); 2381 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad", 2382 CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames"); 2383} 2384 2385static device_method_t sis_methods[] = { 2386 /* Device interface */ 2387 DEVMETHOD(device_probe, sis_probe), 2388 DEVMETHOD(device_attach, sis_attach), 2389 DEVMETHOD(device_detach, sis_detach), 2390 DEVMETHOD(device_shutdown, sis_shutdown), 2391 DEVMETHOD(device_suspend, sis_suspend), 2392 DEVMETHOD(device_resume, sis_resume), 2393 2394 /* MII interface */ 2395 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2396 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2397 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2398 2399 DEVMETHOD_END 2400}; 2401 2402static driver_t sis_driver = { 2403 "sis", 2404 sis_methods, 2405 sizeof(struct sis_softc) 2406}; 2407 2408static devclass_t sis_devclass; 2409 2410DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2411DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 2412