1/*-
2 * Copyright (c) 2009-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: releng/10.3/sys/dev/sfxge/common/siena_impl.h 294389 2016-01-20 08:05:56Z arybchik $
31 */
32
33#ifndef _SYS_SIENA_IMPL_H
34#define	_SYS_SIENA_IMPL_H
35
36#include "efx.h"
37#include "efx_regs.h"
38#include "efx_mcdi.h"
39#include "siena_flash.h"
40
41#ifdef	__cplusplus
42extern "C" {
43#endif
44
45#if EFSYS_OPT_PHY_PROPS
46
47/* START MKCONFIG GENERATED SienaPhyHeaderPropsBlock a8db1f8eb5106efd */
48typedef enum siena_phy_prop_e {
49	SIENA_PHY_NPROPS
50} siena_phy_prop_t;
51
52/* END MKCONFIG GENERATED SienaPhyHeaderPropsBlock */
53
54#endif  /* EFSYS_OPT_PHY_PROPS */
55
56#define	SIENA_NVRAM_CHUNK 0x80
57
58extern	__checkReturn	efx_rc_t
59siena_nic_probe(
60	__in		efx_nic_t *enp);
61
62#if EFSYS_OPT_PCIE_TUNE
63
64extern	__checkReturn	efx_rc_t
65siena_nic_pcie_extended_sync(
66	__in		efx_nic_t *enp);
67
68#endif
69
70extern	__checkReturn	efx_rc_t
71siena_nic_reset(
72	__in		efx_nic_t *enp);
73
74extern	__checkReturn	efx_rc_t
75siena_nic_init(
76	__in		efx_nic_t *enp);
77
78#if EFSYS_OPT_DIAG
79
80extern	__checkReturn	efx_rc_t
81siena_nic_register_test(
82	__in		efx_nic_t *enp);
83
84#endif	/* EFSYS_OPT_DIAG */
85
86extern			void
87siena_nic_fini(
88	__in		efx_nic_t *enp);
89
90extern			void
91siena_nic_unprobe(
92	__in		efx_nic_t *enp);
93
94#define	SIENA_SRAM_ROWS	0x12000
95
96extern			void
97siena_sram_init(
98	__in		efx_nic_t *enp);
99
100#if EFSYS_OPT_DIAG
101
102extern	__checkReturn	efx_rc_t
103siena_sram_test(
104	__in		efx_nic_t *enp,
105	__in		efx_sram_pattern_fn_t func);
106
107#endif	/* EFSYS_OPT_DIAG */
108
109#if EFSYS_OPT_MCDI
110
111extern	__checkReturn	efx_rc_t
112siena_mcdi_init(
113	__in		efx_nic_t *enp,
114	__in		const efx_mcdi_transport_t *mtp);
115
116extern			void
117siena_mcdi_send_request(
118	__in		efx_nic_t *enp,
119	__in		void *hdrp,
120	__in		size_t hdr_len,
121	__in		void *sdup,
122	__in		size_t sdu_len);
123
124extern	__checkReturn	boolean_t
125siena_mcdi_poll_response(
126	__in		efx_nic_t *enp);
127
128extern			void
129siena_mcdi_read_response(
130	__in			efx_nic_t *enp,
131	__out_bcount(length)	void *bufferp,
132	__in			size_t offset,
133	__in			size_t length);
134
135extern			efx_rc_t
136siena_mcdi_poll_reboot(
137	__in		efx_nic_t *enp);
138
139extern			void
140siena_mcdi_fini(
141	__in		efx_nic_t *enp);
142
143extern	__checkReturn	efx_rc_t
144siena_mcdi_feature_supported(
145	__in		efx_nic_t *enp,
146	__in		efx_mcdi_feature_id_t id,
147	__out		boolean_t *supportedp);
148
149#endif /* EFSYS_OPT_MCDI */
150
151#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
152
153extern	__checkReturn		efx_rc_t
154siena_nvram_partn_lock(
155	__in			efx_nic_t *enp,
156	__in			uint32_t partn);
157
158extern				void
159siena_nvram_partn_unlock(
160	__in			efx_nic_t *enp,
161	__in			uint32_t partn);
162
163extern	__checkReturn		efx_rc_t
164siena_nvram_get_dynamic_cfg(
165	__in			efx_nic_t *enp,
166	__in			uint32_t partn,
167	__in			boolean_t vpd,
168	__out			siena_mc_dynamic_config_hdr_t **dcfgp,
169	__out			size_t *sizep);
170
171#endif	/* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
172
173#if EFSYS_OPT_NVRAM
174
175#if EFSYS_OPT_DIAG
176
177extern	__checkReturn		efx_rc_t
178siena_nvram_test(
179	__in			efx_nic_t *enp);
180
181#endif	/* EFSYS_OPT_DIAG */
182
183extern	__checkReturn		efx_rc_t
184siena_nvram_get_subtype(
185	__in			efx_nic_t *enp,
186	__in			uint32_t partn,
187	__out			uint32_t *subtypep);
188
189extern	__checkReturn		efx_rc_t
190siena_nvram_type_to_partn(
191	__in			efx_nic_t *enp,
192	__in			efx_nvram_type_t type,
193	__out			uint32_t *partnp);
194
195extern	__checkReturn		efx_rc_t
196siena_nvram_partn_size(
197	__in			efx_nic_t *enp,
198	__in			uint32_t partn,
199	__out			size_t *sizep);
200
201extern	__checkReturn		efx_rc_t
202siena_nvram_partn_rw_start(
203	__in			efx_nic_t *enp,
204	__in			uint32_t partn,
205	__out			size_t *chunk_sizep);
206
207extern	__checkReturn		efx_rc_t
208siena_nvram_partn_read(
209	__in			efx_nic_t *enp,
210	__in			uint32_t partn,
211	__in			unsigned int offset,
212	__out_bcount(size)	caddr_t data,
213	__in			size_t size);
214
215extern	__checkReturn		efx_rc_t
216siena_nvram_partn_erase(
217	__in			efx_nic_t *enp,
218	__in			uint32_t partn,
219	__in			unsigned int offset,
220	__in			size_t size);
221
222extern	__checkReturn		efx_rc_t
223siena_nvram_partn_write(
224	__in			efx_nic_t *enp,
225	__in			uint32_t partn,
226	__in			unsigned int offset,
227	__out_bcount(size)	caddr_t data,
228	__in			size_t size);
229
230extern				void
231siena_nvram_partn_rw_finish(
232	__in			efx_nic_t *enp,
233	__in			uint32_t partn);
234
235extern	__checkReturn		efx_rc_t
236siena_nvram_partn_get_version(
237	__in			efx_nic_t *enp,
238	__in			uint32_t partn,
239	__out			uint32_t *subtypep,
240	__out_ecount(4)		uint16_t version[4]);
241
242extern	__checkReturn		efx_rc_t
243siena_nvram_partn_set_version(
244	__in			efx_nic_t *enp,
245	__in			uint32_t partn,
246	__in_ecount(4)		uint16_t version[4]);
247
248#endif	/* EFSYS_OPT_NVRAM */
249
250#if EFSYS_OPT_VPD
251
252extern	__checkReturn		efx_rc_t
253siena_vpd_init(
254	__in			efx_nic_t *enp);
255
256extern	__checkReturn		efx_rc_t
257siena_vpd_size(
258	__in			efx_nic_t *enp,
259	__out			size_t *sizep);
260
261extern	__checkReturn		efx_rc_t
262siena_vpd_read(
263	__in			efx_nic_t *enp,
264	__out_bcount(size)	caddr_t data,
265	__in			size_t size);
266
267extern	__checkReturn		efx_rc_t
268siena_vpd_verify(
269	__in			efx_nic_t *enp,
270	__in_bcount(size)	caddr_t data,
271	__in			size_t size);
272
273extern	__checkReturn		efx_rc_t
274siena_vpd_reinit(
275	__in			efx_nic_t *enp,
276	__in_bcount(size)	caddr_t data,
277	__in			size_t size);
278
279extern	__checkReturn		efx_rc_t
280siena_vpd_get(
281	__in			efx_nic_t *enp,
282	__in_bcount(size)	caddr_t data,
283	__in			size_t size,
284	__inout			efx_vpd_value_t *evvp);
285
286extern	__checkReturn		efx_rc_t
287siena_vpd_set(
288	__in			efx_nic_t *enp,
289	__in_bcount(size)	caddr_t data,
290	__in			size_t size,
291	__in			efx_vpd_value_t *evvp);
292
293extern	__checkReturn		efx_rc_t
294siena_vpd_next(
295	__in			efx_nic_t *enp,
296	__in_bcount(size)	caddr_t data,
297	__in			size_t size,
298	__out			efx_vpd_value_t *evvp,
299	__inout			unsigned int *contp);
300
301extern __checkReturn		efx_rc_t
302siena_vpd_write(
303	__in			efx_nic_t *enp,
304	__in_bcount(size)	caddr_t data,
305	__in			size_t size);
306
307extern				void
308siena_vpd_fini(
309	__in			efx_nic_t *enp);
310
311#endif	/* EFSYS_OPT_VPD */
312
313typedef struct siena_link_state_s {
314	uint32_t		sls_adv_cap_mask;
315	uint32_t		sls_lp_cap_mask;
316	unsigned int 		sls_fcntl;
317	efx_link_mode_t		sls_link_mode;
318#if EFSYS_OPT_LOOPBACK
319	efx_loopback_type_t	sls_loopback;
320#endif
321	boolean_t		sls_mac_up;
322} siena_link_state_t;
323
324extern			void
325siena_phy_link_ev(
326	__in		efx_nic_t *enp,
327	__in		efx_qword_t *eqp,
328	__out		efx_link_mode_t *link_modep);
329
330extern	__checkReturn	efx_rc_t
331siena_phy_get_link(
332	__in		efx_nic_t *enp,
333	__out		siena_link_state_t *slsp);
334
335extern	__checkReturn	efx_rc_t
336siena_phy_power(
337	__in		efx_nic_t *enp,
338	__in		boolean_t on);
339
340extern	__checkReturn	efx_rc_t
341siena_phy_reconfigure(
342	__in		efx_nic_t *enp);
343
344extern	__checkReturn	efx_rc_t
345siena_phy_verify(
346	__in		efx_nic_t *enp);
347
348extern	__checkReturn	efx_rc_t
349siena_phy_oui_get(
350	__in		efx_nic_t *enp,
351	__out		uint32_t *ouip);
352
353#if EFSYS_OPT_PHY_STATS
354
355extern						void
356siena_phy_decode_stats(
357	__in					efx_nic_t *enp,
358	__in					uint32_t vmask,
359	__in_opt				efsys_mem_t *esmp,
360	__out_opt				uint64_t *smaskp,
361	__inout_ecount_opt(EFX_PHY_NSTATS)	uint32_t *stat);
362
363extern	__checkReturn			efx_rc_t
364siena_phy_stats_update(
365	__in				efx_nic_t *enp,
366	__in				efsys_mem_t *esmp,
367	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
368
369#endif	/* EFSYS_OPT_PHY_STATS */
370
371#if EFSYS_OPT_PHY_PROPS
372
373#if EFSYS_OPT_NAMES
374
375extern		const char *
376siena_phy_prop_name(
377	__in	efx_nic_t *enp,
378	__in	unsigned int id);
379
380#endif	/* EFSYS_OPT_NAMES */
381
382extern	__checkReturn	efx_rc_t
383siena_phy_prop_get(
384	__in		efx_nic_t *enp,
385	__in		unsigned int id,
386	__in		uint32_t flags,
387	__out		uint32_t *valp);
388
389extern	__checkReturn	efx_rc_t
390siena_phy_prop_set(
391	__in		efx_nic_t *enp,
392	__in		unsigned int id,
393	__in		uint32_t val);
394
395#endif	/* EFSYS_OPT_PHY_PROPS */
396
397#if EFSYS_OPT_BIST
398
399extern	__checkReturn		efx_rc_t
400siena_phy_bist_start(
401	__in			efx_nic_t *enp,
402	__in			efx_bist_type_t type);
403
404extern	__checkReturn		efx_rc_t
405siena_phy_bist_poll(
406	__in			efx_nic_t *enp,
407	__in			efx_bist_type_t type,
408	__out			efx_bist_result_t *resultp,
409	__out_opt __drv_when(count > 0, __notnull)
410	uint32_t 	*value_maskp,
411	__out_ecount_opt(count)	__drv_when(count > 0, __notnull)
412	unsigned long	*valuesp,
413	__in			size_t count);
414
415extern				void
416siena_phy_bist_stop(
417	__in			efx_nic_t *enp,
418	__in			efx_bist_type_t type);
419
420#endif	/* EFSYS_OPT_BIST */
421
422extern	__checkReturn	efx_rc_t
423siena_mac_poll(
424	__in		efx_nic_t *enp,
425	__out		efx_link_mode_t *link_modep);
426
427extern	__checkReturn	efx_rc_t
428siena_mac_up(
429	__in		efx_nic_t *enp,
430	__out		boolean_t *mac_upp);
431
432extern	__checkReturn	efx_rc_t
433siena_mac_reconfigure(
434	__in	efx_nic_t *enp);
435
436#if EFSYS_OPT_LOOPBACK
437
438extern	__checkReturn	efx_rc_t
439siena_mac_loopback_set(
440	__in		efx_nic_t *enp,
441	__in		efx_link_mode_t link_mode,
442	__in		efx_loopback_type_t loopback_type);
443
444#endif	/* EFSYS_OPT_LOOPBACK */
445
446#if EFSYS_OPT_MAC_STATS
447
448extern	__checkReturn			efx_rc_t
449siena_mac_stats_update(
450	__in				efx_nic_t *enp,
451	__in				efsys_mem_t *esmp,
452	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
453	__inout_opt			uint32_t *generationp);
454
455#endif	/* EFSYS_OPT_MAC_STATS */
456
457#ifdef	__cplusplus
458}
459#endif
460
461#endif	/* _SYS_SIENA_IMPL_H */
462