efx.h revision 294017
1244390Srwatson/*- 2156283Srwatson * Copyright (c) 2006-2015 Solarflare Communications Inc. 3156283Srwatson * All rights reserved. 4244390Srwatson * 5244390Srwatson * Redistribution and use in source and binary forms, with or without 6156283Srwatson * modification, are permitted provided that the following conditions are met: 7156283Srwatson * 8156283Srwatson * 1. Redistributions of source code must retain the above copyright notice, 9156283Srwatson * this list of conditions and the following disclaimer. 10156283Srwatson * 2. Redistributions in binary form must reproduce the above copyright notice, 11156283Srwatson * this list of conditions and the following disclaimer in the documentation 12156283Srwatson * and/or other materials provided with the distribution. 13156283Srwatson * 14156283Srwatson * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15156283Srwatson * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16156283Srwatson * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17244390Srwatson * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18244390Srwatson * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19244390Srwatson * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20244390Srwatson * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21244390Srwatson * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22244390Srwatson * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23244390Srwatson * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24244390Srwatson * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25244390Srwatson * 26244390Srwatson * The views and conclusions contained in the software and documentation are 27244390Srwatson * those of the authors and should not be interpreted as representing official 28244390Srwatson * policies, either expressed or implied, of the FreeBSD Project. 29244390Srwatson * 30244390Srwatson * $FreeBSD: stable/10/sys/dev/sfxge/common/efx.h 294017 2016-01-14 16:28:21Z arybchik $ 31244390Srwatson */ 32244390Srwatson 33244390Srwatson#ifndef _SYS_EFX_H 34156283Srwatson#define _SYS_EFX_H 35244390Srwatson 36156283Srwatson#include "efsys.h" 37244390Srwatson#include "efx_phy_ids.h" 38156283Srwatson 39156283Srwatson#ifdef __cplusplus 40156283Srwatsonextern "C" { 41156283Srwatson#endif 42156283Srwatson 43156283Srwatson#define EFX_STATIC_ASSERT(_cond) \ 44156283Srwatson ((void)sizeof(char[(_cond) ? 1 : -1])) 45156283Srwatson 46156283Srwatson#define EFX_ARRAY_SIZE(_array) \ 47156283Srwatson (sizeof(_array) / sizeof((_array)[0])) 48156283Srwatson 49156283Srwatson#define EFX_FIELD_OFFSET(_type, _field) \ 50156283Srwatson ((size_t) &(((_type *)0)->_field)) 51156283Srwatson 52156283Srwatson/* Return codes */ 53156283Srwatson 54156283Srwatsontypedef __success(return == 0) int efx_rc_t; 55156283Srwatson 56156283Srwatson 57156283Srwatson/* Chip families */ 58156283Srwatson 59156283Srwatsontypedef enum efx_family_e { 60156283Srwatson EFX_FAMILY_INVALID, 61156283Srwatson EFX_FAMILY_FALCON, 62156283Srwatson EFX_FAMILY_SIENA, 63156283Srwatson EFX_FAMILY_HUNTINGTON, 64156283Srwatson EFX_FAMILY_MEDFORD, 65244390Srwatson EFX_FAMILY_NTYPES 66156283Srwatson} efx_family_t; 67156283Srwatson 68156283Srwatsonextern __checkReturn efx_rc_t 69156283Srwatsonefx_family( 70173143Srwatson __in uint16_t venid, 71173143Srwatson __in uint16_t devid, 72173143Srwatson __out efx_family_t *efp); 73173143Srwatson 74173143Srwatsonextern __checkReturn efx_rc_t 75244390Srwatsonefx_infer_family( 76244390Srwatson __in efsys_bar_t *esbp, 77244390Srwatson __out efx_family_t *efp); 78244390Srwatson 79244390Srwatson#define EFX_PCI_VENID_SFC 0x1924 80173143Srwatson 81173143Srwatson#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 82244390Srwatson 83244390Srwatson#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 84244390Srwatson#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 85156283Srwatson#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 86156283Srwatson 87244390Srwatson#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 88244390Srwatson#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 89156283Srwatson#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 90244390Srwatson 91244390Srwatson#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 92244390Srwatson#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 93244390Srwatson 94244390Srwatson#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 95244390Srwatson#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 96244390Srwatson#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 97244390Srwatson 98244390Srwatson#define EFX_MEM_BAR 2 99244390Srwatson 100244390Srwatson/* Error codes */ 101244390Srwatson 102244390Srwatsonenum { 103244390Srwatson EFX_ERR_INVALID, 104244390Srwatson EFX_ERR_SRAM_OOB, 105244390Srwatson EFX_ERR_BUFID_DC_OOB, 106244390Srwatson EFX_ERR_MEM_PERR, 107244390Srwatson EFX_ERR_RBUF_OWN, 108244390Srwatson EFX_ERR_TBUF_OWN, 109244390Srwatson EFX_ERR_RDESQ_OWN, 110244390Srwatson EFX_ERR_TDESQ_OWN, 111244390Srwatson EFX_ERR_EVQ_OWN, 112244390Srwatson EFX_ERR_EVFF_OFLO, 113244390Srwatson EFX_ERR_ILL_ADDR, 114244390Srwatson EFX_ERR_SRAM_PERR, 115156283Srwatson EFX_ERR_NCODES 116156283Srwatson}; 117156283Srwatson 118156283Srwatson/* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 119156283Srwatsonextern __checkReturn uint32_t 120156283Srwatsonefx_crc32_calculate( 121156283Srwatson __in uint32_t crc_init, 122156283Srwatson __in_ecount(length) uint8_t const *input, 123156283Srwatson __in int length); 124156283Srwatson 125156283Srwatson 126156283Srwatson/* Type prototypes */ 127156283Srwatson 128156283Srwatsontypedef struct efx_rxq_s efx_rxq_t; 129156283Srwatson 130244390Srwatson/* NIC */ 131191273Srwatson 132244390Srwatsontypedef struct efx_nic_s efx_nic_t; 133156283Srwatson 134156283Srwatson#define EFX_NIC_FUNC_PRIMARY 0x00000001 135156283Srwatson#define EFX_NIC_FUNC_LINKCTRL 0x00000002 136156283Srwatson#define EFX_NIC_FUNC_TRUSTED 0x00000004 137156283Srwatson 138244390Srwatson 139173143Srwatsonextern __checkReturn efx_rc_t 140173143Srwatsonefx_nic_create( 141156283Srwatson __in efx_family_t family, 142156283Srwatson __in efsys_identifier_t *esip, 143156283Srwatson __in efsys_bar_t *esbp, 144156283Srwatson __in efsys_lock_t *eslp, 145244390Srwatson __deref_out efx_nic_t **enpp); 146156283Srwatson 147244390Srwatsonextern __checkReturn efx_rc_t 148244390Srwatsonefx_nic_probe( 149244390Srwatson __in efx_nic_t *enp); 150156283Srwatson 151156283Srwatson#if EFSYS_OPT_PCIE_TUNE 152156283Srwatson 153244390Srwatsonextern __checkReturn efx_rc_t 154156283Srwatsonefx_nic_pcie_tune( 155156283Srwatson __in efx_nic_t *enp, 156156283Srwatson unsigned int nlanes); 157156283Srwatson 158244390Srwatsonextern __checkReturn efx_rc_t 159185573Srwatsonefx_nic_pcie_extended_sync( 160173143Srwatson __in efx_nic_t *enp); 161244390Srwatson 162191273Srwatson#endif /* EFSYS_OPT_PCIE_TUNE */ 163244390Srwatson 164156283Srwatsonextern __checkReturn efx_rc_t 165244390Srwatsonefx_nic_init( 166244390Srwatson __in efx_nic_t *enp); 167156283Srwatson 168156283Srwatsonextern __checkReturn efx_rc_t 169156283Srwatsonefx_nic_reset( 170156283Srwatson __in efx_nic_t *enp); 171156283Srwatson 172244390Srwatson#if EFSYS_OPT_DIAG 173156283Srwatson 174156283Srwatsonextern __checkReturn efx_rc_t 175156283Srwatsonefx_nic_register_test( 176173143Srwatson __in efx_nic_t *enp); 177156283Srwatson 178156283Srwatson#endif /* EFSYS_OPT_DIAG */ 179156283Srwatson 180156283Srwatsonextern void 181244390Srwatsonefx_nic_fini( 182244390Srwatson __in efx_nic_t *enp); 183173143Srwatson 184173143Srwatsonextern void 185173143Srwatsonefx_nic_unprobe( 186173143Srwatson __in efx_nic_t *enp); 187244390Srwatson 188156283Srwatsonextern void 189244390Srwatsonefx_nic_destroy( 190156283Srwatson __in efx_nic_t *enp); 191156283Srwatson 192156283Srwatson#if EFSYS_OPT_MCDI 193156283Srwatson 194156283Srwatson#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 195156283Srwatson/* Huntington and Medford require MCDIv2 commands */ 196156283Srwatson#define WITH_MCDI_V2 1 197156283Srwatson#endif 198156283Srwatson 199156283Srwatsontypedef struct efx_mcdi_req_s efx_mcdi_req_t; 200156283Srwatson 201173143Srwatsontypedef enum efx_mcdi_exception_e { 202156283Srwatson EFX_MCDI_EXCEPTION_MC_REBOOT, 203173143Srwatson EFX_MCDI_EXCEPTION_MC_BADASSERT, 204173143Srwatson} efx_mcdi_exception_t; 205173143Srwatson 206156283Srwatson#if EFSYS_OPT_MCDI_LOGGING 207156283Srwatsontypedef enum efx_log_msg_e 208156283Srwatson{ 209156283Srwatson EFX_LOG_INVALID, 210156283Srwatson EFX_LOG_MCDI_REQUEST, 211156283Srwatson EFX_LOG_MCDI_RESPONSE, 212173143Srwatson} efx_log_msg_t; 213156283Srwatson#endif /* EFSYS_OPT_MCDI_LOGGING */ 214156283Srwatson 215156283Srwatsontypedef struct efx_mcdi_transport_s { 216156283Srwatson void *emt_context; 217156283Srwatson efsys_mem_t *emt_dma_mem; 218173143Srwatson void (*emt_execute)(void *, efx_mcdi_req_t *); 219156283Srwatson void (*emt_ev_cpl)(void *); 220156283Srwatson void (*emt_exception)(void *, efx_mcdi_exception_t); 221156283Srwatson#if EFSYS_OPT_MCDI_LOGGING 222156283Srwatson void (*emt_logger)(void *, efx_log_msg_t, 223173143Srwatson void *, size_t, void *, size_t); 224156283Srwatson#endif /* EFSYS_OPT_MCDI_LOGGING */ 225156283Srwatson#if EFSYS_OPT_MCDI_PROXY_AUTH 226173143Srwatson void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 227156283Srwatson#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 228156283Srwatson} efx_mcdi_transport_t; 229173143Srwatson 230156283Srwatsonextern __checkReturn efx_rc_t 231156283Srwatsonefx_mcdi_init( 232191273Srwatson __in efx_nic_t *enp, 233173143Srwatson __in const efx_mcdi_transport_t *mtp); 234173143Srwatson 235244390Srwatsonextern __checkReturn efx_rc_t 236156283Srwatsonefx_mcdi_reboot( 237156283Srwatson __in efx_nic_t *enp); 238156283Srwatson 239156283Srwatson void 240156283Srwatsonefx_mcdi_new_epoch( 241156283Srwatson __in efx_nic_t *enp); 242156283Srwatson 243244390Srwatsonextern void 244244390Srwatsonefx_mcdi_request_start( 245156283Srwatson __in efx_nic_t *enp, 246156283Srwatson __in efx_mcdi_req_t *emrp, 247156283Srwatson __in boolean_t ev_cpl); 248244390Srwatson 249244390Srwatsonextern __checkReturn boolean_t 250244390Srwatsonefx_mcdi_request_poll( 251156283Srwatson __in efx_nic_t *enp); 252156283Srwatson 253156283Srwatsonextern __checkReturn boolean_t 254156283Srwatsonefx_mcdi_request_abort( 255156283Srwatson __in efx_nic_t *enp); 256156283Srwatson 257156283Srwatsonextern void 258156283Srwatsonefx_mcdi_fini( 259156283Srwatson __in efx_nic_t *enp); 260156283Srwatson 261156283Srwatson#endif /* EFSYS_OPT_MCDI */ 262156283Srwatson 263156283Srwatson/* INTR */ 264156283Srwatson 265156283Srwatson#define EFX_NINTR_FALCON 64 266156283Srwatson#define EFX_NINTR_SIENA 1024 267156283Srwatson 268244390Srwatsontypedef enum efx_intr_type_e { 269156283Srwatson EFX_INTR_INVALID = 0, 270156283Srwatson EFX_INTR_LINE, 271156283Srwatson EFX_INTR_MESSAGE, 272156283Srwatson EFX_INTR_NTYPES 273156283Srwatson} efx_intr_type_t; 274156283Srwatson 275156283Srwatson#define EFX_INTR_SIZE (sizeof (efx_oword_t)) 276156283Srwatson 277244390Srwatsonextern __checkReturn efx_rc_t 278244390Srwatsonefx_intr_init( 279244390Srwatson __in efx_nic_t *enp, 280244390Srwatson __in efx_intr_type_t type, 281244390Srwatson __in efsys_mem_t *esmp); 282244390Srwatson 283244390Srwatsonextern void 284156283Srwatsonefx_intr_enable( 285156283Srwatson __in efx_nic_t *enp); 286156283Srwatson 287156283Srwatsonextern void 288156283Srwatsonefx_intr_disable( 289156283Srwatson __in efx_nic_t *enp); 290156283Srwatson 291156283Srwatsonextern void 292244390Srwatsonefx_intr_disable_unlocked( 293244390Srwatson __in efx_nic_t *enp); 294244390Srwatson 295244390Srwatson#define EFX_INTR_NEVQS 32 296244390Srwatson 297156283Srwatsonextern __checkReturn efx_rc_t 298156283Srwatsonefx_intr_trigger( 299156283Srwatson __in efx_nic_t *enp, 300156283Srwatson __in unsigned int level); 301156283Srwatson 302156283Srwatsonextern void 303156283Srwatsonefx_intr_status_line( 304244390Srwatson __in efx_nic_t *enp, 305156283Srwatson __out boolean_t *fatalp, 306156283Srwatson __out uint32_t *maskp); 307156283Srwatson 308156283Srwatsonextern void 309156283Srwatsonefx_intr_status_message( 310156283Srwatson __in efx_nic_t *enp, 311156283Srwatson __in unsigned int message, 312244390Srwatson __out boolean_t *fatalp); 313156283Srwatson 314156283Srwatsonextern void 315156283Srwatsonefx_intr_fatal( 316244390Srwatson __in efx_nic_t *enp); 317156283Srwatson 318244390Srwatsonextern void 319244390Srwatsonefx_intr_fini( 320244390Srwatson __in efx_nic_t *enp); 321244390Srwatson 322156283Srwatson/* MAC */ 323156283Srwatson 324156283Srwatson#if EFSYS_OPT_MAC_STATS 325156283Srwatson 326156283Srwatson/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ 327156283Srwatsontypedef enum efx_mac_stat_e { 328244390Srwatson EFX_MAC_RX_OCTETS, 329191273Srwatson EFX_MAC_RX_PKTS, 330156283Srwatson EFX_MAC_RX_UNICST_PKTS, 331156283Srwatson EFX_MAC_RX_MULTICST_PKTS, 332156283Srwatson EFX_MAC_RX_BRDCST_PKTS, 333156283Srwatson EFX_MAC_RX_PAUSE_PKTS, 334156283Srwatson EFX_MAC_RX_LE_64_PKTS, 335244390Srwatson EFX_MAC_RX_65_TO_127_PKTS, 336156283Srwatson EFX_MAC_RX_128_TO_255_PKTS, 337156283Srwatson EFX_MAC_RX_256_TO_511_PKTS, 338156283Srwatson EFX_MAC_RX_512_TO_1023_PKTS, 339156283Srwatson EFX_MAC_RX_1024_TO_15XX_PKTS, 340156283Srwatson EFX_MAC_RX_GE_15XX_PKTS, 341156283Srwatson EFX_MAC_RX_ERRORS, 342156283Srwatson EFX_MAC_RX_FCS_ERRORS, 343156283Srwatson EFX_MAC_RX_DROP_EVENTS, 344156283Srwatson EFX_MAC_RX_FALSE_CARRIER_ERRORS, 345156283Srwatson EFX_MAC_RX_SYMBOL_ERRORS, 346156283Srwatson EFX_MAC_RX_ALIGN_ERRORS, 347244390Srwatson EFX_MAC_RX_INTERNAL_ERRORS, 348156283Srwatson EFX_MAC_RX_JABBER_PKTS, 349156283Srwatson EFX_MAC_RX_LANE0_CHAR_ERR, 350156283Srwatson EFX_MAC_RX_LANE1_CHAR_ERR, 351156283Srwatson EFX_MAC_RX_LANE2_CHAR_ERR, 352156283Srwatson EFX_MAC_RX_LANE3_CHAR_ERR, 353156283Srwatson EFX_MAC_RX_LANE0_DISP_ERR, 354191273Srwatson EFX_MAC_RX_LANE1_DISP_ERR, 355191273Srwatson EFX_MAC_RX_LANE2_DISP_ERR, 356244390Srwatson EFX_MAC_RX_LANE3_DISP_ERR, 357244390Srwatson EFX_MAC_RX_MATCH_FAULT, 358156283Srwatson EFX_MAC_RX_NODESC_DROP_CNT, 359244390Srwatson EFX_MAC_TX_OCTETS, 360244390Srwatson EFX_MAC_TX_PKTS, 361244390Srwatson EFX_MAC_TX_UNICST_PKTS, 362244390Srwatson EFX_MAC_TX_MULTICST_PKTS, 363244390Srwatson EFX_MAC_TX_BRDCST_PKTS, 364244390Srwatson EFX_MAC_TX_PAUSE_PKTS, 365244390Srwatson EFX_MAC_TX_LE_64_PKTS, 366156283Srwatson EFX_MAC_TX_65_TO_127_PKTS, 367156283Srwatson EFX_MAC_TX_128_TO_255_PKTS, 368156283Srwatson EFX_MAC_TX_256_TO_511_PKTS, 369156283Srwatson EFX_MAC_TX_512_TO_1023_PKTS, 370156283Srwatson EFX_MAC_TX_1024_TO_15XX_PKTS, 371156283Srwatson EFX_MAC_TX_GE_15XX_PKTS, 372156283Srwatson EFX_MAC_TX_ERRORS, 373156283Srwatson EFX_MAC_TX_SGL_COL_PKTS, 374191273Srwatson EFX_MAC_TX_MULT_COL_PKTS, 375191273Srwatson EFX_MAC_TX_EX_COL_PKTS, 376244390Srwatson EFX_MAC_TX_LATE_COL_PKTS, 377156283Srwatson EFX_MAC_TX_DEF_PKTS, 378244390Srwatson EFX_MAC_TX_EX_DEF_PKTS, 379156283Srwatson EFX_MAC_PM_TRUNC_BB_OVERFLOW, 380156283Srwatson EFX_MAC_PM_DISCARD_BB_OVERFLOW, 381156283Srwatson EFX_MAC_PM_TRUNC_VFIFO_FULL, 382244390Srwatson EFX_MAC_PM_DISCARD_VFIFO_FULL, 383244390Srwatson EFX_MAC_PM_TRUNC_QBB, 384156283Srwatson EFX_MAC_PM_DISCARD_QBB, 385244390Srwatson EFX_MAC_PM_DISCARD_MAPPING, 386244390Srwatson EFX_MAC_RXDP_Q_DISABLED_PKTS, 387244390Srwatson EFX_MAC_RXDP_DI_DROPPED_PKTS, 388244390Srwatson EFX_MAC_RXDP_STREAMING_PKTS, 389244390Srwatson EFX_MAC_RXDP_HLB_FETCH, 390244390Srwatson EFX_MAC_RXDP_HLB_WAIT, 391244390Srwatson EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 392244390Srwatson EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 393244390Srwatson EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 394244390Srwatson EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 395244390Srwatson EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 396244390Srwatson EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 397244390Srwatson EFX_MAC_VADAPTER_RX_BAD_PACKETS, 398244390Srwatson EFX_MAC_VADAPTER_RX_BAD_BYTES, 399156283Srwatson EFX_MAC_VADAPTER_RX_OVERFLOW, 400156283Srwatson EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 401156283Srwatson EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 402156283Srwatson EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 403173143Srwatson EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 404173143Srwatson EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 405173143Srwatson EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 406173143Srwatson EFX_MAC_VADAPTER_TX_BAD_PACKETS, 407173143Srwatson EFX_MAC_VADAPTER_TX_BAD_BYTES, 408173143Srwatson EFX_MAC_VADAPTER_TX_OVERFLOW, 409173143Srwatson EFX_MAC_NSTATS 410173143Srwatson} efx_mac_stat_t; 411173143Srwatson 412173143Srwatson/* END MKCONFIG GENERATED EfxHeaderMacBlock */ 413173143Srwatson 414173143Srwatson#endif /* EFSYS_OPT_MAC_STATS */ 415156283Srwatson 416156283Srwatsontypedef enum efx_link_mode_e { 417173143Srwatson EFX_LINK_UNKNOWN = 0, 418244390Srwatson EFX_LINK_DOWN, 419244390Srwatson EFX_LINK_10HDX, 420244390Srwatson EFX_LINK_10FDX, 421156283Srwatson EFX_LINK_100HDX, 422244390Srwatson EFX_LINK_100FDX, 423244390Srwatson EFX_LINK_1000HDX, 424156283Srwatson EFX_LINK_1000FDX, 425244390Srwatson EFX_LINK_10000FDX, 426156283Srwatson EFX_LINK_40000FDX, 427244390Srwatson EFX_LINK_NMODES 428244390Srwatson} efx_link_mode_t; 429156283Srwatson 430156283Srwatson#define EFX_MAC_ADDR_LEN 6 431156283Srwatson 432244390Srwatson#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01) 433156283Srwatson 434244390Srwatson#define EFX_MAC_MULTICAST_LIST_MAX 256 435244390Srwatson 436244390Srwatson#define EFX_MAC_SDU_MAX 9202 437244390Srwatson 438244390Srwatson#define EFX_MAC_PDU(_sdu) \ 439244390Srwatson P2ROUNDUP(((_sdu) \ 440244390Srwatson + /* EtherII */ 14 \ 441244390Srwatson + /* VLAN */ 4 \ 442244390Srwatson + /* CRC */ 4 \ 443244390Srwatson + /* bug16011 */ 16), \ 444244390Srwatson (1 << 3)) 445244390Srwatson 446244390Srwatson#define EFX_MAC_PDU_MIN 60 447156283Srwatson#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 448244390Srwatson 449244390Srwatsonextern __checkReturn efx_rc_t 450173143Srwatsonefx_mac_pdu_set( 451173143Srwatson __in efx_nic_t *enp, 452244390Srwatson __in size_t pdu); 453156283Srwatson 454156283Srwatsonextern __checkReturn efx_rc_t 455156283Srwatsonefx_mac_addr_set( 456156283Srwatson __in efx_nic_t *enp, 457156283Srwatson __in uint8_t *addr); 458156283Srwatson 459156283Srwatsonextern __checkReturn efx_rc_t 460156283Srwatsonefx_mac_filter_set( 461156283Srwatson __in efx_nic_t *enp, 462156283Srwatson __in boolean_t all_unicst, 463156283Srwatson __in boolean_t mulcst, 464156283Srwatson __in boolean_t all_mulcst, 465156283Srwatson __in boolean_t brdcst); 466156283Srwatson 467156283Srwatsonextern __checkReturn efx_rc_t 468156283Srwatsonefx_mac_multicast_list_set( 469156283Srwatson __in efx_nic_t *enp, 470156283Srwatson __in_ecount(6*count) uint8_t const *addrs, 471156283Srwatson __in int count); 472244390Srwatson 473244390Srwatsonextern __checkReturn efx_rc_t 474244390Srwatsonefx_mac_filter_default_rxq_set( 475244390Srwatson __in efx_nic_t *enp, 476244390Srwatson __in efx_rxq_t *erp, 477244390Srwatson __in boolean_t using_rss); 478244390Srwatson 479244390Srwatsonextern void 480244390Srwatsonefx_mac_filter_default_rxq_clear( 481156283Srwatson __in efx_nic_t *enp); 482156283Srwatson 483156283Srwatsonextern __checkReturn efx_rc_t 484156283Srwatsonefx_mac_drain( 485156283Srwatson __in efx_nic_t *enp, 486156283Srwatson __in boolean_t enabled); 487244390Srwatson 488156283Srwatsonextern __checkReturn efx_rc_t 489156283Srwatsonefx_mac_up( 490156283Srwatson __in efx_nic_t *enp, 491156283Srwatson __out boolean_t *mac_upp); 492156283Srwatson 493156283Srwatson#define EFX_FCNTL_RESPOND 0x00000001 494156283Srwatson#define EFX_FCNTL_GENERATE 0x00000002 495156283Srwatson 496156283Srwatsonextern __checkReturn efx_rc_t 497156283Srwatsonefx_mac_fcntl_set( 498173143Srwatson __in efx_nic_t *enp, 499156283Srwatson __in unsigned int fcntl, 500156283Srwatson __in boolean_t autoneg); 501156283Srwatson 502156283Srwatsonextern void 503156283Srwatsonefx_mac_fcntl_get( 504156283Srwatson __in efx_nic_t *enp, 505156283Srwatson __out unsigned int *fcntl_wantedp, 506244390Srwatson __out unsigned int *fcntl_linkp); 507244390Srwatson 508156283Srwatson 509156283Srwatson#if EFSYS_OPT_MAC_STATS 510156283Srwatson 511156283Srwatson#if EFSYS_OPT_NAMES 512156283Srwatson 513156283Srwatsonextern __checkReturn const char * 514173143Srwatsonefx_mac_stat_name( 515173143Srwatson __in efx_nic_t *enp, 516244390Srwatson __in unsigned int id); 517244390Srwatson 518156283Srwatson#endif /* EFSYS_OPT_NAMES */ 519156283Srwatson 520173143Srwatson#define EFX_MAC_STATS_SIZE 0x400 521173143Srwatson 522244390Srwatson/* 523244390Srwatson * Upload mac statistics supported by the hardware into the given buffer. 524156283Srwatson * 525156283Srwatson * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 526244390Srwatson * and page aligned. 527244390Srwatson * 528156283Srwatson * The hardware will only DMA statistics that it understands (of course). 529156283Srwatson * Drivers should not make any assumptions about which statistics are 530173143Srwatson * supported, especially when the statistics are generated by firmware. 531173143Srwatson * 532244390Srwatson * Thus, drivers should zero this buffer before use, so that not-understood 533244390Srwatson * statistics read back as zero. 534173143Srwatson */ 535173143Srwatsonextern __checkReturn efx_rc_t 536244390Srwatsonefx_mac_stats_upload( 537244390Srwatson __in efx_nic_t *enp, 538156283Srwatson __in efsys_mem_t *esmp); 539156283Srwatson 540156283Srwatsonextern __checkReturn efx_rc_t 541156283Srwatsonefx_mac_stats_periodic( 542156283Srwatson __in efx_nic_t *enp, 543156283Srwatson __in efsys_mem_t *esmp, 544156283Srwatson __in uint16_t period_ms, 545156283Srwatson __in boolean_t events); 546156283Srwatson 547156283Srwatsonextern __checkReturn efx_rc_t 548156283Srwatsonefx_mac_stats_update( 549156283Srwatson __in efx_nic_t *enp, 550156283Srwatson __in efsys_mem_t *esmp, 551156283Srwatson __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 552156283Srwatson __inout_opt uint32_t *generationp); 553156283Srwatson 554156283Srwatson#endif /* EFSYS_OPT_MAC_STATS */ 555156283Srwatson 556173143Srwatson/* MON */ 557156283Srwatson 558244390Srwatsontypedef enum efx_mon_type_e { 559244390Srwatson EFX_MON_INVALID = 0, 560244390Srwatson EFX_MON_NULL, 561156283Srwatson EFX_MON_LM87, 562173143Srwatson EFX_MON_MAX6647, 563173143Srwatson EFX_MON_SFC90X0, 564244390Srwatson EFX_MON_SFC91X0, 565244390Srwatson EFX_MON_SFC92X0, 566244390Srwatson EFX_MON_NTYPES 567244390Srwatson} efx_mon_type_t; 568244390Srwatson 569244390Srwatson#if EFSYS_OPT_NAMES 570244390Srwatson 571244390Srwatsonextern const char * 572244390Srwatsonefx_mon_name( 573244390Srwatson __in efx_nic_t *enp); 574244390Srwatson 575156283Srwatson#endif /* EFSYS_OPT_NAMES */ 576244390Srwatson 577156283Srwatsonextern __checkReturn efx_rc_t 578156283Srwatsonefx_mon_init( 579156283Srwatson __in efx_nic_t *enp); 580 581#if EFSYS_OPT_MON_STATS 582 583#define EFX_MON_STATS_PAGE_SIZE 0x100 584#define EFX_MON_MASK_ELEMENT_SIZE 32 585 586/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c09b13f732431f23 */ 587typedef enum efx_mon_stat_e { 588 EFX_MON_STAT_2_5V, 589 EFX_MON_STAT_VCCP1, 590 EFX_MON_STAT_VCC, 591 EFX_MON_STAT_5V, 592 EFX_MON_STAT_12V, 593 EFX_MON_STAT_VCCP2, 594 EFX_MON_STAT_EXT_TEMP, 595 EFX_MON_STAT_INT_TEMP, 596 EFX_MON_STAT_AIN1, 597 EFX_MON_STAT_AIN2, 598 EFX_MON_STAT_INT_COOLING, 599 EFX_MON_STAT_EXT_COOLING, 600 EFX_MON_STAT_1V, 601 EFX_MON_STAT_1_2V, 602 EFX_MON_STAT_1_8V, 603 EFX_MON_STAT_3_3V, 604 EFX_MON_STAT_1_2VA, 605 EFX_MON_STAT_VREF, 606 EFX_MON_STAT_VAOE, 607 EFX_MON_STAT_AOE_TEMP, 608 EFX_MON_STAT_PSU_AOE_TEMP, 609 EFX_MON_STAT_PSU_TEMP, 610 EFX_MON_STAT_FAN0, 611 EFX_MON_STAT_FAN1, 612 EFX_MON_STAT_FAN2, 613 EFX_MON_STAT_FAN3, 614 EFX_MON_STAT_FAN4, 615 EFX_MON_STAT_VAOE_IN, 616 EFX_MON_STAT_IAOE, 617 EFX_MON_STAT_IAOE_IN, 618 EFX_MON_STAT_NIC_POWER, 619 EFX_MON_STAT_0_9V, 620 EFX_MON_STAT_I0_9V, 621 EFX_MON_STAT_I1_2V, 622 EFX_MON_STAT_0_9V_ADC, 623 EFX_MON_STAT_INT_TEMP2, 624 EFX_MON_STAT_VREG_TEMP, 625 EFX_MON_STAT_VREG_0_9V_TEMP, 626 EFX_MON_STAT_VREG_1_2V_TEMP, 627 EFX_MON_STAT_INT_VPTAT, 628 EFX_MON_STAT_INT_ADC_TEMP, 629 EFX_MON_STAT_EXT_VPTAT, 630 EFX_MON_STAT_EXT_ADC_TEMP, 631 EFX_MON_STAT_AMBIENT_TEMP, 632 EFX_MON_STAT_AIRFLOW, 633 EFX_MON_STAT_VDD08D_VSS08D_CSR, 634 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 635 EFX_MON_STAT_HOTPOINT_TEMP, 636 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, 637 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, 638 EFX_MON_STAT_MUM_VCC, 639 EFX_MON_STAT_0V9_A, 640 EFX_MON_STAT_I0V9_A, 641 EFX_MON_STAT_0V9_A_TEMP, 642 EFX_MON_STAT_0V9_B, 643 EFX_MON_STAT_I0V9_B, 644 EFX_MON_STAT_0V9_B_TEMP, 645 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 646 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, 647 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 648 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, 649 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 650 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 651 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, 652 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, 653 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 654 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 655 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, 656 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, 657 EFX_MON_STAT_SODIMM_VOUT, 658 EFX_MON_STAT_SODIMM_0_TEMP, 659 EFX_MON_STAT_SODIMM_1_TEMP, 660 EFX_MON_STAT_PHY0_VCC, 661 EFX_MON_STAT_PHY1_VCC, 662 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 663 EFX_MON_NSTATS 664} efx_mon_stat_t; 665 666/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 667 668typedef enum efx_mon_stat_state_e { 669 EFX_MON_STAT_STATE_OK = 0, 670 EFX_MON_STAT_STATE_WARNING = 1, 671 EFX_MON_STAT_STATE_FATAL = 2, 672 EFX_MON_STAT_STATE_BROKEN = 3, 673 EFX_MON_STAT_STATE_NO_READING = 4, 674} efx_mon_stat_state_t; 675 676typedef struct efx_mon_stat_value_s { 677 uint16_t emsv_value; 678 uint16_t emsv_state; 679} efx_mon_stat_value_t; 680 681#if EFSYS_OPT_NAMES 682 683extern const char * 684efx_mon_stat_name( 685 __in efx_nic_t *enp, 686 __in efx_mon_stat_t id); 687 688#endif /* EFSYS_OPT_NAMES */ 689 690extern __checkReturn efx_rc_t 691efx_mon_stats_update( 692 __in efx_nic_t *enp, 693 __in efsys_mem_t *esmp, 694 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 695 696#endif /* EFSYS_OPT_MON_STATS */ 697 698extern void 699efx_mon_fini( 700 __in efx_nic_t *enp); 701 702/* PHY */ 703 704#define PMA_PMD_MMD 1 705#define PCS_MMD 3 706#define PHY_XS_MMD 4 707#define DTE_XS_MMD 5 708#define AN_MMD 7 709#define CL22EXT_MMD 29 710 711#define MAXMMD ((1 << 5) - 1) 712 713extern __checkReturn efx_rc_t 714efx_phy_verify( 715 __in efx_nic_t *enp); 716 717#if EFSYS_OPT_PHY_LED_CONTROL 718 719typedef enum efx_phy_led_mode_e { 720 EFX_PHY_LED_DEFAULT = 0, 721 EFX_PHY_LED_OFF, 722 EFX_PHY_LED_ON, 723 EFX_PHY_LED_FLASH, 724 EFX_PHY_LED_NMODES 725} efx_phy_led_mode_t; 726 727extern __checkReturn efx_rc_t 728efx_phy_led_set( 729 __in efx_nic_t *enp, 730 __in efx_phy_led_mode_t mode); 731 732#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 733 734extern __checkReturn efx_rc_t 735efx_port_init( 736 __in efx_nic_t *enp); 737 738#if EFSYS_OPT_LOOPBACK 739 740typedef enum efx_loopback_type_e { 741 EFX_LOOPBACK_OFF = 0, 742 EFX_LOOPBACK_DATA = 1, 743 EFX_LOOPBACK_GMAC = 2, 744 EFX_LOOPBACK_XGMII = 3, 745 EFX_LOOPBACK_XGXS = 4, 746 EFX_LOOPBACK_XAUI = 5, 747 EFX_LOOPBACK_GMII = 6, 748 EFX_LOOPBACK_SGMII = 7, 749 EFX_LOOPBACK_XGBR = 8, 750 EFX_LOOPBACK_XFI = 9, 751 EFX_LOOPBACK_XAUI_FAR = 10, 752 EFX_LOOPBACK_GMII_FAR = 11, 753 EFX_LOOPBACK_SGMII_FAR = 12, 754 EFX_LOOPBACK_XFI_FAR = 13, 755 EFX_LOOPBACK_GPHY = 14, 756 EFX_LOOPBACK_PHY_XS = 15, 757 EFX_LOOPBACK_PCS = 16, 758 EFX_LOOPBACK_PMA_PMD = 17, 759 EFX_LOOPBACK_XPORT = 18, 760 EFX_LOOPBACK_XGMII_WS = 19, 761 EFX_LOOPBACK_XAUI_WS = 20, 762 EFX_LOOPBACK_XAUI_WS_FAR = 21, 763 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 764 EFX_LOOPBACK_GMII_WS = 23, 765 EFX_LOOPBACK_XFI_WS = 24, 766 EFX_LOOPBACK_XFI_WS_FAR = 25, 767 EFX_LOOPBACK_PHYXS_WS = 26, 768 EFX_LOOPBACK_PMA_INT = 27, 769 EFX_LOOPBACK_SD_NEAR = 28, 770 EFX_LOOPBACK_SD_FAR = 29, 771 EFX_LOOPBACK_PMA_INT_WS = 30, 772 EFX_LOOPBACK_SD_FEP2_WS = 31, 773 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 774 EFX_LOOPBACK_SD_FEP_WS = 33, 775 EFX_LOOPBACK_SD_FES_WS = 34, 776 EFX_LOOPBACK_NTYPES 777} efx_loopback_type_t; 778 779typedef enum efx_loopback_kind_e { 780 EFX_LOOPBACK_KIND_OFF = 0, 781 EFX_LOOPBACK_KIND_ALL, 782 EFX_LOOPBACK_KIND_MAC, 783 EFX_LOOPBACK_KIND_PHY, 784 EFX_LOOPBACK_NKINDS 785} efx_loopback_kind_t; 786 787extern void 788efx_loopback_mask( 789 __in efx_loopback_kind_t loopback_kind, 790 __out efx_qword_t *maskp); 791 792extern __checkReturn efx_rc_t 793efx_port_loopback_set( 794 __in efx_nic_t *enp, 795 __in efx_link_mode_t link_mode, 796 __in efx_loopback_type_t type); 797 798#if EFSYS_OPT_NAMES 799 800extern __checkReturn const char * 801efx_loopback_type_name( 802 __in efx_nic_t *enp, 803 __in efx_loopback_type_t type); 804 805#endif /* EFSYS_OPT_NAMES */ 806 807#endif /* EFSYS_OPT_LOOPBACK */ 808 809extern __checkReturn efx_rc_t 810efx_port_poll( 811 __in efx_nic_t *enp, 812 __out_opt efx_link_mode_t *link_modep); 813 814extern void 815efx_port_fini( 816 __in efx_nic_t *enp); 817 818typedef enum efx_phy_cap_type_e { 819 EFX_PHY_CAP_INVALID = 0, 820 EFX_PHY_CAP_10HDX, 821 EFX_PHY_CAP_10FDX, 822 EFX_PHY_CAP_100HDX, 823 EFX_PHY_CAP_100FDX, 824 EFX_PHY_CAP_1000HDX, 825 EFX_PHY_CAP_1000FDX, 826 EFX_PHY_CAP_10000FDX, 827 EFX_PHY_CAP_PAUSE, 828 EFX_PHY_CAP_ASYM, 829 EFX_PHY_CAP_AN, 830 EFX_PHY_CAP_40000FDX, 831 EFX_PHY_CAP_NTYPES 832} efx_phy_cap_type_t; 833 834 835#define EFX_PHY_CAP_CURRENT 0x00000000 836#define EFX_PHY_CAP_DEFAULT 0x00000001 837#define EFX_PHY_CAP_PERM 0x00000002 838 839extern void 840efx_phy_adv_cap_get( 841 __in efx_nic_t *enp, 842 __in uint32_t flag, 843 __out uint32_t *maskp); 844 845extern __checkReturn efx_rc_t 846efx_phy_adv_cap_set( 847 __in efx_nic_t *enp, 848 __in uint32_t mask); 849 850extern void 851efx_phy_lp_cap_get( 852 __in efx_nic_t *enp, 853 __out uint32_t *maskp); 854 855extern __checkReturn efx_rc_t 856efx_phy_oui_get( 857 __in efx_nic_t *enp, 858 __out uint32_t *ouip); 859 860typedef enum efx_phy_media_type_e { 861 EFX_PHY_MEDIA_INVALID = 0, 862 EFX_PHY_MEDIA_XAUI, 863 EFX_PHY_MEDIA_CX4, 864 EFX_PHY_MEDIA_KX4, 865 EFX_PHY_MEDIA_XFP, 866 EFX_PHY_MEDIA_SFP_PLUS, 867 EFX_PHY_MEDIA_BASE_T, 868 EFX_PHY_MEDIA_QSFP_PLUS, 869 EFX_PHY_MEDIA_NTYPES 870} efx_phy_media_type_t; 871 872/* Get the type of medium currently used. If the board has ports for 873 * modules, a module is present, and we recognise the media type of 874 * the module, then this will be the media type of the module. 875 * Otherwise it will be the media type of the port. 876 */ 877extern void 878efx_phy_media_type_get( 879 __in efx_nic_t *enp, 880 __out efx_phy_media_type_t *typep); 881 882#if EFSYS_OPT_PHY_STATS 883 884/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 885typedef enum efx_phy_stat_e { 886 EFX_PHY_STAT_OUI, 887 EFX_PHY_STAT_PMA_PMD_LINK_UP, 888 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 889 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 890 EFX_PHY_STAT_PMA_PMD_REV_A, 891 EFX_PHY_STAT_PMA_PMD_REV_B, 892 EFX_PHY_STAT_PMA_PMD_REV_C, 893 EFX_PHY_STAT_PMA_PMD_REV_D, 894 EFX_PHY_STAT_PCS_LINK_UP, 895 EFX_PHY_STAT_PCS_RX_FAULT, 896 EFX_PHY_STAT_PCS_TX_FAULT, 897 EFX_PHY_STAT_PCS_BER, 898 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 899 EFX_PHY_STAT_PHY_XS_LINK_UP, 900 EFX_PHY_STAT_PHY_XS_RX_FAULT, 901 EFX_PHY_STAT_PHY_XS_TX_FAULT, 902 EFX_PHY_STAT_PHY_XS_ALIGN, 903 EFX_PHY_STAT_PHY_XS_SYNC_A, 904 EFX_PHY_STAT_PHY_XS_SYNC_B, 905 EFX_PHY_STAT_PHY_XS_SYNC_C, 906 EFX_PHY_STAT_PHY_XS_SYNC_D, 907 EFX_PHY_STAT_AN_LINK_UP, 908 EFX_PHY_STAT_AN_MASTER, 909 EFX_PHY_STAT_AN_LOCAL_RX_OK, 910 EFX_PHY_STAT_AN_REMOTE_RX_OK, 911 EFX_PHY_STAT_CL22EXT_LINK_UP, 912 EFX_PHY_STAT_SNR_A, 913 EFX_PHY_STAT_SNR_B, 914 EFX_PHY_STAT_SNR_C, 915 EFX_PHY_STAT_SNR_D, 916 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 917 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 918 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 919 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 920 EFX_PHY_STAT_AN_COMPLETE, 921 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 922 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 923 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 924 EFX_PHY_STAT_PCS_FW_VERSION_0, 925 EFX_PHY_STAT_PCS_FW_VERSION_1, 926 EFX_PHY_STAT_PCS_FW_VERSION_2, 927 EFX_PHY_STAT_PCS_FW_VERSION_3, 928 EFX_PHY_STAT_PCS_FW_BUILD_YY, 929 EFX_PHY_STAT_PCS_FW_BUILD_MM, 930 EFX_PHY_STAT_PCS_FW_BUILD_DD, 931 EFX_PHY_STAT_PCS_OP_MODE, 932 EFX_PHY_NSTATS 933} efx_phy_stat_t; 934 935/* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 936 937#if EFSYS_OPT_NAMES 938 939extern const char * 940efx_phy_stat_name( 941 __in efx_nic_t *enp, 942 __in efx_phy_stat_t stat); 943 944#endif /* EFSYS_OPT_NAMES */ 945 946#define EFX_PHY_STATS_SIZE 0x100 947 948extern __checkReturn efx_rc_t 949efx_phy_stats_update( 950 __in efx_nic_t *enp, 951 __in efsys_mem_t *esmp, 952 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 953 954#endif /* EFSYS_OPT_PHY_STATS */ 955 956#if EFSYS_OPT_PHY_PROPS 957 958#if EFSYS_OPT_NAMES 959 960extern const char * 961efx_phy_prop_name( 962 __in efx_nic_t *enp, 963 __in unsigned int id); 964 965#endif /* EFSYS_OPT_NAMES */ 966 967#define EFX_PHY_PROP_DEFAULT 0x00000001 968 969extern __checkReturn efx_rc_t 970efx_phy_prop_get( 971 __in efx_nic_t *enp, 972 __in unsigned int id, 973 __in uint32_t flags, 974 __out uint32_t *valp); 975 976extern __checkReturn efx_rc_t 977efx_phy_prop_set( 978 __in efx_nic_t *enp, 979 __in unsigned int id, 980 __in uint32_t val); 981 982#endif /* EFSYS_OPT_PHY_PROPS */ 983 984#if EFSYS_OPT_BIST 985 986typedef enum efx_bist_type_e { 987 EFX_BIST_TYPE_UNKNOWN, 988 EFX_BIST_TYPE_PHY_NORMAL, 989 EFX_BIST_TYPE_PHY_CABLE_SHORT, 990 EFX_BIST_TYPE_PHY_CABLE_LONG, 991 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 992 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/ 993 EFX_BIST_TYPE_REG, /* Test the register memories */ 994 EFX_BIST_TYPE_NTYPES, 995} efx_bist_type_t; 996 997typedef enum efx_bist_result_e { 998 EFX_BIST_RESULT_UNKNOWN, 999 EFX_BIST_RESULT_RUNNING, 1000 EFX_BIST_RESULT_PASSED, 1001 EFX_BIST_RESULT_FAILED, 1002} efx_bist_result_t; 1003 1004typedef enum efx_phy_cable_status_e { 1005 EFX_PHY_CABLE_STATUS_OK, 1006 EFX_PHY_CABLE_STATUS_INVALID, 1007 EFX_PHY_CABLE_STATUS_OPEN, 1008 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1009 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1010 EFX_PHY_CABLE_STATUS_BUSY, 1011} efx_phy_cable_status_t; 1012 1013typedef enum efx_bist_value_e { 1014 EFX_BIST_PHY_CABLE_LENGTH_A, 1015 EFX_BIST_PHY_CABLE_LENGTH_B, 1016 EFX_BIST_PHY_CABLE_LENGTH_C, 1017 EFX_BIST_PHY_CABLE_LENGTH_D, 1018 EFX_BIST_PHY_CABLE_STATUS_A, 1019 EFX_BIST_PHY_CABLE_STATUS_B, 1020 EFX_BIST_PHY_CABLE_STATUS_C, 1021 EFX_BIST_PHY_CABLE_STATUS_D, 1022 EFX_BIST_FAULT_CODE, 1023 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1024 * response. */ 1025 EFX_BIST_MEM_TEST, 1026 EFX_BIST_MEM_ADDR, 1027 EFX_BIST_MEM_BUS, 1028 EFX_BIST_MEM_EXPECT, 1029 EFX_BIST_MEM_ACTUAL, 1030 EFX_BIST_MEM_ECC, 1031 EFX_BIST_MEM_ECC_PARITY, 1032 EFX_BIST_MEM_ECC_FATAL, 1033 EFX_BIST_NVALUES, 1034} efx_bist_value_t; 1035 1036extern __checkReturn efx_rc_t 1037efx_bist_enable_offline( 1038 __in efx_nic_t *enp); 1039 1040extern __checkReturn efx_rc_t 1041efx_bist_start( 1042 __in efx_nic_t *enp, 1043 __in efx_bist_type_t type); 1044 1045extern __checkReturn efx_rc_t 1046efx_bist_poll( 1047 __in efx_nic_t *enp, 1048 __in efx_bist_type_t type, 1049 __out efx_bist_result_t *resultp, 1050 __out_opt uint32_t *value_maskp, 1051 __out_ecount_opt(count) unsigned long *valuesp, 1052 __in size_t count); 1053 1054extern void 1055efx_bist_stop( 1056 __in efx_nic_t *enp, 1057 __in efx_bist_type_t type); 1058 1059#endif /* EFSYS_OPT_BIST */ 1060 1061#define EFX_FEATURE_IPV6 0x00000001 1062#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1063#define EFX_FEATURE_LINK_EVENTS 0x00000004 1064#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1065#define EFX_FEATURE_WOL 0x00000010 1066#define EFX_FEATURE_MCDI 0x00000020 1067#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1068#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1069#define EFX_FEATURE_TURBO 0x00000100 1070#define EFX_FEATURE_MCDI_DMA 0x00000200 1071#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1072#define EFX_FEATURE_PIO_BUFFERS 0x00000800 1073#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1074 1075typedef struct efx_nic_cfg_s { 1076 uint32_t enc_board_type; 1077 uint32_t enc_phy_type; 1078#if EFSYS_OPT_NAMES 1079 char enc_phy_name[21]; 1080#endif 1081 char enc_phy_revision[21]; 1082 efx_mon_type_t enc_mon_type; 1083#if EFSYS_OPT_MON_STATS 1084 uint32_t enc_mon_stat_dma_buf_size; 1085 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1086#endif 1087 unsigned int enc_features; 1088 uint8_t enc_mac_addr[6]; 1089 uint8_t enc_port; /* PHY port number */ 1090 uint32_t enc_func_flags; 1091 uint32_t enc_intr_vec_base; 1092 uint32_t enc_intr_limit; 1093 uint32_t enc_evq_limit; 1094 uint32_t enc_txq_limit; 1095 uint32_t enc_rxq_limit; 1096 uint32_t enc_buftbl_limit; 1097 uint32_t enc_piobuf_limit; 1098 uint32_t enc_piobuf_size; 1099 uint32_t enc_piobuf_min_alloc_size; 1100 uint32_t enc_evq_timer_quantum_ns; 1101 uint32_t enc_evq_timer_max_us; 1102 uint32_t enc_clk_mult; 1103 uint32_t enc_rx_prefix_size; 1104 uint32_t enc_rx_buf_align_start; 1105 uint32_t enc_rx_buf_align_end; 1106#if EFSYS_OPT_LOOPBACK 1107 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1108#endif /* EFSYS_OPT_LOOPBACK */ 1109#if EFSYS_OPT_PHY_FLAGS 1110 uint32_t enc_phy_flags_mask; 1111#endif /* EFSYS_OPT_PHY_FLAGS */ 1112#if EFSYS_OPT_PHY_LED_CONTROL 1113 uint32_t enc_led_mask; 1114#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1115#if EFSYS_OPT_PHY_STATS 1116 uint64_t enc_phy_stat_mask; 1117#endif /* EFSYS_OPT_PHY_STATS */ 1118#if EFSYS_OPT_PHY_PROPS 1119 unsigned int enc_phy_nprops; 1120#endif /* EFSYS_OPT_PHY_PROPS */ 1121#if EFSYS_OPT_SIENA 1122 uint8_t enc_mcdi_mdio_channel; 1123#if EFSYS_OPT_PHY_STATS 1124 uint32_t enc_mcdi_phy_stat_mask; 1125#endif /* EFSYS_OPT_PHY_STATS */ 1126#endif /* EFSYS_OPT_SIENA */ 1127#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 1128#if EFSYS_OPT_MON_STATS 1129 uint32_t *enc_mcdi_sensor_maskp; 1130 uint32_t enc_mcdi_sensor_mask_size; 1131#endif /* EFSYS_OPT_MON_STATS */ 1132#endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 1133#if EFSYS_OPT_BIST 1134 uint32_t enc_bist_mask; 1135#endif /* EFSYS_OPT_BIST */ 1136#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 1137 uint32_t enc_pf; 1138 uint32_t enc_vf; 1139 uint32_t enc_privilege_mask; 1140#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 1141 boolean_t enc_bug26807_workaround; 1142 boolean_t enc_bug35388_workaround; 1143 boolean_t enc_bug41750_workaround; 1144 boolean_t enc_rx_batching_enabled; 1145 /* Maximum number of descriptors completed in an rx event. */ 1146 uint32_t enc_rx_batch_max; 1147 /* Number of rx descriptors the hardware requires for a push. */ 1148 uint32_t enc_rx_push_align; 1149 /* 1150 * Maximum number of bytes into the packet the TCP header can start for 1151 * the hardware to apply TSO packet edits. 1152 */ 1153 uint32_t enc_tx_tso_tcp_header_offset_limit; 1154 boolean_t enc_fw_assisted_tso_enabled; 1155 boolean_t enc_hw_tx_insert_vlan_enabled; 1156 /* Datapath firmware vadapter/vport/vswitch support */ 1157 boolean_t enc_datapath_cap_evb; 1158 boolean_t enc_rx_disable_scatter_supported; 1159 boolean_t enc_allow_set_mac_with_installed_filters; 1160 /* External port identifier */ 1161 uint8_t enc_external_port; 1162 uint32_t enc_mcdi_max_payload_length; 1163} efx_nic_cfg_t; 1164 1165#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1166#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1167 1168#define EFX_PCI_FUNCTION(_encp) \ 1169 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1170 1171#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1172 1173extern const efx_nic_cfg_t * 1174efx_nic_cfg_get( 1175 __in efx_nic_t *enp); 1176 1177/* Driver resource limits (minimum required/maximum usable). */ 1178typedef struct efx_drv_limits_s 1179{ 1180 uint32_t edl_min_evq_count; 1181 uint32_t edl_max_evq_count; 1182 1183 uint32_t edl_min_rxq_count; 1184 uint32_t edl_max_rxq_count; 1185 1186 uint32_t edl_min_txq_count; 1187 uint32_t edl_max_txq_count; 1188 1189 /* PIO blocks (sub-allocated from piobuf) */ 1190 uint32_t edl_min_pio_alloc_size; 1191 uint32_t edl_max_pio_alloc_count; 1192} efx_drv_limits_t; 1193 1194extern __checkReturn efx_rc_t 1195efx_nic_set_drv_limits( 1196 __inout efx_nic_t *enp, 1197 __in efx_drv_limits_t *edlp); 1198 1199typedef enum efx_nic_region_e { 1200 EFX_REGION_VI, /* Memory BAR UC mapping */ 1201 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1202} efx_nic_region_t; 1203 1204extern __checkReturn efx_rc_t 1205efx_nic_get_bar_region( 1206 __in efx_nic_t *enp, 1207 __in efx_nic_region_t region, 1208 __out uint32_t *offsetp, 1209 __out size_t *sizep); 1210 1211extern __checkReturn efx_rc_t 1212efx_nic_get_vi_pool( 1213 __in efx_nic_t *enp, 1214 __out uint32_t *evq_countp, 1215 __out uint32_t *rxq_countp, 1216 __out uint32_t *txq_countp); 1217 1218 1219#if EFSYS_OPT_VPD 1220 1221typedef enum efx_vpd_tag_e { 1222 EFX_VPD_ID = 0x02, 1223 EFX_VPD_END = 0x0f, 1224 EFX_VPD_RO = 0x10, 1225 EFX_VPD_RW = 0x11, 1226} efx_vpd_tag_t; 1227 1228typedef uint16_t efx_vpd_keyword_t; 1229 1230typedef struct efx_vpd_value_s { 1231 efx_vpd_tag_t evv_tag; 1232 efx_vpd_keyword_t evv_keyword; 1233 uint8_t evv_length; 1234 uint8_t evv_value[0x100]; 1235} efx_vpd_value_t; 1236 1237 1238#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1239 1240extern __checkReturn efx_rc_t 1241efx_vpd_init( 1242 __in efx_nic_t *enp); 1243 1244extern __checkReturn efx_rc_t 1245efx_vpd_size( 1246 __in efx_nic_t *enp, 1247 __out size_t *sizep); 1248 1249extern __checkReturn efx_rc_t 1250efx_vpd_read( 1251 __in efx_nic_t *enp, 1252 __out_bcount(size) caddr_t data, 1253 __in size_t size); 1254 1255extern __checkReturn efx_rc_t 1256efx_vpd_verify( 1257 __in efx_nic_t *enp, 1258 __in_bcount(size) caddr_t data, 1259 __in size_t size); 1260 1261extern __checkReturn efx_rc_t 1262efx_vpd_reinit( 1263 __in efx_nic_t *enp, 1264 __in_bcount(size) caddr_t data, 1265 __in size_t size); 1266 1267extern __checkReturn efx_rc_t 1268efx_vpd_get( 1269 __in efx_nic_t *enp, 1270 __in_bcount(size) caddr_t data, 1271 __in size_t size, 1272 __inout efx_vpd_value_t *evvp); 1273 1274extern __checkReturn efx_rc_t 1275efx_vpd_set( 1276 __in efx_nic_t *enp, 1277 __inout_bcount(size) caddr_t data, 1278 __in size_t size, 1279 __in efx_vpd_value_t *evvp); 1280 1281extern __checkReturn efx_rc_t 1282efx_vpd_next( 1283 __in efx_nic_t *enp, 1284 __inout_bcount(size) caddr_t data, 1285 __in size_t size, 1286 __out efx_vpd_value_t *evvp, 1287 __inout unsigned int *contp); 1288 1289extern __checkReturn efx_rc_t 1290efx_vpd_write( 1291 __in efx_nic_t *enp, 1292 __in_bcount(size) caddr_t data, 1293 __in size_t size); 1294 1295extern void 1296efx_vpd_fini( 1297 __in efx_nic_t *enp); 1298 1299#endif /* EFSYS_OPT_VPD */ 1300 1301/* NVRAM */ 1302 1303#if EFSYS_OPT_NVRAM 1304 1305typedef enum efx_nvram_type_e { 1306 EFX_NVRAM_INVALID = 0, 1307 EFX_NVRAM_BOOTROM, 1308 EFX_NVRAM_BOOTROM_CFG, 1309 EFX_NVRAM_MC_FIRMWARE, 1310 EFX_NVRAM_MC_GOLDEN, 1311 EFX_NVRAM_PHY, 1312 EFX_NVRAM_NULLPHY, 1313 EFX_NVRAM_FPGA, 1314 EFX_NVRAM_FCFW, 1315 EFX_NVRAM_CPLD, 1316 EFX_NVRAM_FPGA_BACKUP, 1317 EFX_NVRAM_DYNAMIC_CFG, 1318 EFX_NVRAM_NTYPES, 1319} efx_nvram_type_t; 1320 1321extern __checkReturn efx_rc_t 1322efx_nvram_init( 1323 __in efx_nic_t *enp); 1324 1325#if EFSYS_OPT_DIAG 1326 1327extern __checkReturn efx_rc_t 1328efx_nvram_test( 1329 __in efx_nic_t *enp); 1330 1331#endif /* EFSYS_OPT_DIAG */ 1332 1333extern __checkReturn efx_rc_t 1334efx_nvram_size( 1335 __in efx_nic_t *enp, 1336 __in efx_nvram_type_t type, 1337 __out size_t *sizep); 1338 1339extern __checkReturn efx_rc_t 1340efx_nvram_rw_start( 1341 __in efx_nic_t *enp, 1342 __in efx_nvram_type_t type, 1343 __out_opt size_t *pref_chunkp); 1344 1345extern void 1346efx_nvram_rw_finish( 1347 __in efx_nic_t *enp, 1348 __in efx_nvram_type_t type); 1349 1350extern __checkReturn efx_rc_t 1351efx_nvram_get_version( 1352 __in efx_nic_t *enp, 1353 __in efx_nvram_type_t type, 1354 __out uint32_t *subtypep, 1355 __out_ecount(4) uint16_t version[4]); 1356 1357extern __checkReturn efx_rc_t 1358efx_nvram_read_chunk( 1359 __in efx_nic_t *enp, 1360 __in efx_nvram_type_t type, 1361 __in unsigned int offset, 1362 __out_bcount(size) caddr_t data, 1363 __in size_t size); 1364 1365extern __checkReturn efx_rc_t 1366efx_nvram_set_version( 1367 __in efx_nic_t *enp, 1368 __in efx_nvram_type_t type, 1369 __in_ecount(4) uint16_t version[4]); 1370 1371/* Validate contents of TLV formatted partition */ 1372extern __checkReturn efx_rc_t 1373efx_nvram_tlv_validate( 1374 __in efx_nic_t *enp, 1375 __in uint32_t partn, 1376 __in_bcount(partn_size) caddr_t partn_data, 1377 __in size_t partn_size); 1378 1379extern __checkReturn efx_rc_t 1380efx_nvram_erase( 1381 __in efx_nic_t *enp, 1382 __in efx_nvram_type_t type); 1383 1384extern __checkReturn efx_rc_t 1385efx_nvram_write_chunk( 1386 __in efx_nic_t *enp, 1387 __in efx_nvram_type_t type, 1388 __in unsigned int offset, 1389 __in_bcount(size) caddr_t data, 1390 __in size_t size); 1391 1392extern void 1393efx_nvram_fini( 1394 __in efx_nic_t *enp); 1395 1396#endif /* EFSYS_OPT_NVRAM */ 1397 1398#if EFSYS_OPT_BOOTCFG 1399 1400extern efx_rc_t 1401efx_bootcfg_read( 1402 __in efx_nic_t *enp, 1403 __out_bcount(size) caddr_t data, 1404 __in size_t size); 1405 1406extern efx_rc_t 1407efx_bootcfg_write( 1408 __in efx_nic_t *enp, 1409 __in_bcount(size) caddr_t data, 1410 __in size_t size); 1411 1412#endif /* EFSYS_OPT_BOOTCFG */ 1413 1414#if EFSYS_OPT_WOL 1415 1416typedef enum efx_wol_type_e { 1417 EFX_WOL_TYPE_INVALID, 1418 EFX_WOL_TYPE_MAGIC, 1419 EFX_WOL_TYPE_BITMAP, 1420 EFX_WOL_TYPE_LINK, 1421 EFX_WOL_NTYPES, 1422} efx_wol_type_t; 1423 1424typedef enum efx_lightsout_offload_type_e { 1425 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID, 1426 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP, 1427 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS, 1428} efx_lightsout_offload_type_t; 1429 1430#define EFX_WOL_BITMAP_MASK_SIZE (48) 1431#define EFX_WOL_BITMAP_VALUE_SIZE (128) 1432 1433typedef union efx_wol_param_u { 1434 struct { 1435 uint8_t mac_addr[6]; 1436 } ewp_magic; 1437 struct { 1438 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */ 1439 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */ 1440 uint8_t value_len; 1441 } ewp_bitmap; 1442} efx_wol_param_t; 1443 1444typedef union efx_lightsout_offload_param_u { 1445 struct { 1446 uint8_t mac_addr[6]; 1447 uint32_t ip; 1448 } elop_arp; 1449 struct { 1450 uint8_t mac_addr[6]; 1451 uint32_t solicited_node[4]; 1452 uint32_t ip[4]; 1453 } elop_ns; 1454} efx_lightsout_offload_param_t; 1455 1456extern __checkReturn efx_rc_t 1457efx_wol_init( 1458 __in efx_nic_t *enp); 1459 1460extern __checkReturn efx_rc_t 1461efx_wol_filter_clear( 1462 __in efx_nic_t *enp); 1463 1464extern __checkReturn efx_rc_t 1465efx_wol_filter_add( 1466 __in efx_nic_t *enp, 1467 __in efx_wol_type_t type, 1468 __in efx_wol_param_t *paramp, 1469 __out uint32_t *filter_idp); 1470 1471extern __checkReturn efx_rc_t 1472efx_wol_filter_remove( 1473 __in efx_nic_t *enp, 1474 __in uint32_t filter_id); 1475 1476extern __checkReturn efx_rc_t 1477efx_lightsout_offload_add( 1478 __in efx_nic_t *enp, 1479 __in efx_lightsout_offload_type_t type, 1480 __in efx_lightsout_offload_param_t *paramp, 1481 __out uint32_t *filter_idp); 1482 1483extern __checkReturn efx_rc_t 1484efx_lightsout_offload_remove( 1485 __in efx_nic_t *enp, 1486 __in efx_lightsout_offload_type_t type, 1487 __in uint32_t filter_id); 1488 1489extern void 1490efx_wol_fini( 1491 __in efx_nic_t *enp); 1492 1493#endif /* EFSYS_OPT_WOL */ 1494 1495#if EFSYS_OPT_DIAG 1496 1497typedef enum efx_pattern_type_t { 1498 EFX_PATTERN_BYTE_INCREMENT = 0, 1499 EFX_PATTERN_ALL_THE_SAME, 1500 EFX_PATTERN_BIT_ALTERNATE, 1501 EFX_PATTERN_BYTE_ALTERNATE, 1502 EFX_PATTERN_BYTE_CHANGING, 1503 EFX_PATTERN_BIT_SWEEP, 1504 EFX_PATTERN_NTYPES 1505} efx_pattern_type_t; 1506 1507typedef void 1508(*efx_sram_pattern_fn_t)( 1509 __in size_t row, 1510 __in boolean_t negate, 1511 __out efx_qword_t *eqp); 1512 1513extern __checkReturn efx_rc_t 1514efx_sram_test( 1515 __in efx_nic_t *enp, 1516 __in efx_pattern_type_t type); 1517 1518#endif /* EFSYS_OPT_DIAG */ 1519 1520extern __checkReturn efx_rc_t 1521efx_sram_buf_tbl_set( 1522 __in efx_nic_t *enp, 1523 __in uint32_t id, 1524 __in efsys_mem_t *esmp, 1525 __in size_t n); 1526 1527extern void 1528efx_sram_buf_tbl_clear( 1529 __in efx_nic_t *enp, 1530 __in uint32_t id, 1531 __in size_t n); 1532 1533#define EFX_BUF_TBL_SIZE 0x20000 1534 1535#define EFX_BUF_SIZE 4096 1536 1537/* EV */ 1538 1539typedef struct efx_evq_s efx_evq_t; 1540 1541#if EFSYS_OPT_QSTATS 1542 1543/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1544typedef enum efx_ev_qstat_e { 1545 EV_ALL, 1546 EV_RX, 1547 EV_RX_OK, 1548 EV_RX_FRM_TRUNC, 1549 EV_RX_TOBE_DISC, 1550 EV_RX_PAUSE_FRM_ERR, 1551 EV_RX_BUF_OWNER_ID_ERR, 1552 EV_RX_IPV4_HDR_CHKSUM_ERR, 1553 EV_RX_TCP_UDP_CHKSUM_ERR, 1554 EV_RX_ETH_CRC_ERR, 1555 EV_RX_IP_FRAG_ERR, 1556 EV_RX_MCAST_PKT, 1557 EV_RX_MCAST_HASH_MATCH, 1558 EV_RX_TCP_IPV4, 1559 EV_RX_TCP_IPV6, 1560 EV_RX_UDP_IPV4, 1561 EV_RX_UDP_IPV6, 1562 EV_RX_OTHER_IPV4, 1563 EV_RX_OTHER_IPV6, 1564 EV_RX_NON_IP, 1565 EV_RX_BATCH, 1566 EV_TX, 1567 EV_TX_WQ_FF_FULL, 1568 EV_TX_PKT_ERR, 1569 EV_TX_PKT_TOO_BIG, 1570 EV_TX_UNEXPECTED, 1571 EV_GLOBAL, 1572 EV_GLOBAL_MNT, 1573 EV_DRIVER, 1574 EV_DRIVER_SRM_UPD_DONE, 1575 EV_DRIVER_TX_DESCQ_FLS_DONE, 1576 EV_DRIVER_RX_DESCQ_FLS_DONE, 1577 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1578 EV_DRIVER_RX_DSC_ERROR, 1579 EV_DRIVER_TX_DSC_ERROR, 1580 EV_DRV_GEN, 1581 EV_MCDI_RESPONSE, 1582 EV_NQSTATS 1583} efx_ev_qstat_t; 1584 1585/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1586 1587#endif /* EFSYS_OPT_QSTATS */ 1588 1589extern __checkReturn efx_rc_t 1590efx_ev_init( 1591 __in efx_nic_t *enp); 1592 1593extern void 1594efx_ev_fini( 1595 __in efx_nic_t *enp); 1596 1597#define EFX_EVQ_MAXNEVS 32768 1598#define EFX_EVQ_MINNEVS 512 1599 1600#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1601#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1602 1603extern __checkReturn efx_rc_t 1604efx_ev_qcreate( 1605 __in efx_nic_t *enp, 1606 __in unsigned int index, 1607 __in efsys_mem_t *esmp, 1608 __in size_t n, 1609 __in uint32_t id, 1610 __deref_out efx_evq_t **eepp); 1611 1612extern void 1613efx_ev_qpost( 1614 __in efx_evq_t *eep, 1615 __in uint16_t data); 1616 1617typedef __checkReturn boolean_t 1618(*efx_initialized_ev_t)( 1619 __in_opt void *arg); 1620 1621#define EFX_PKT_UNICAST 0x0004 1622#define EFX_PKT_START 0x0008 1623 1624#define EFX_PKT_VLAN_TAGGED 0x0010 1625#define EFX_CKSUM_TCPUDP 0x0020 1626#define EFX_CKSUM_IPV4 0x0040 1627#define EFX_PKT_CONT 0x0080 1628 1629#define EFX_CHECK_VLAN 0x0100 1630#define EFX_PKT_TCP 0x0200 1631#define EFX_PKT_UDP 0x0400 1632#define EFX_PKT_IPV4 0x0800 1633 1634#define EFX_PKT_IPV6 0x1000 1635#define EFX_PKT_PREFIX_LEN 0x2000 1636#define EFX_ADDR_MISMATCH 0x4000 1637#define EFX_DISCARD 0x8000 1638 1639#define EFX_EV_RX_NLABELS 32 1640#define EFX_EV_TX_NLABELS 32 1641 1642typedef __checkReturn boolean_t 1643(*efx_rx_ev_t)( 1644 __in_opt void *arg, 1645 __in uint32_t label, 1646 __in uint32_t id, 1647 __in uint32_t size, 1648 __in uint16_t flags); 1649 1650typedef __checkReturn boolean_t 1651(*efx_tx_ev_t)( 1652 __in_opt void *arg, 1653 __in uint32_t label, 1654 __in uint32_t id); 1655 1656#define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1657#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1658#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1659#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1660#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1661#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1662#define EFX_EXCEPTION_RX_ERROR 0x00000007 1663#define EFX_EXCEPTION_TX_ERROR 0x00000008 1664#define EFX_EXCEPTION_EV_ERROR 0x00000009 1665 1666typedef __checkReturn boolean_t 1667(*efx_exception_ev_t)( 1668 __in_opt void *arg, 1669 __in uint32_t label, 1670 __in uint32_t data); 1671 1672typedef __checkReturn boolean_t 1673(*efx_rxq_flush_done_ev_t)( 1674 __in_opt void *arg, 1675 __in uint32_t rxq_index); 1676 1677typedef __checkReturn boolean_t 1678(*efx_rxq_flush_failed_ev_t)( 1679 __in_opt void *arg, 1680 __in uint32_t rxq_index); 1681 1682typedef __checkReturn boolean_t 1683(*efx_txq_flush_done_ev_t)( 1684 __in_opt void *arg, 1685 __in uint32_t txq_index); 1686 1687typedef __checkReturn boolean_t 1688(*efx_software_ev_t)( 1689 __in_opt void *arg, 1690 __in uint16_t magic); 1691 1692typedef __checkReturn boolean_t 1693(*efx_sram_ev_t)( 1694 __in_opt void *arg, 1695 __in uint32_t code); 1696 1697#define EFX_SRAM_CLEAR 0 1698#define EFX_SRAM_UPDATE 1 1699#define EFX_SRAM_ILLEGAL_CLEAR 2 1700 1701typedef __checkReturn boolean_t 1702(*efx_wake_up_ev_t)( 1703 __in_opt void *arg, 1704 __in uint32_t label); 1705 1706typedef __checkReturn boolean_t 1707(*efx_timer_ev_t)( 1708 __in_opt void *arg, 1709 __in uint32_t label); 1710 1711typedef __checkReturn boolean_t 1712(*efx_link_change_ev_t)( 1713 __in_opt void *arg, 1714 __in efx_link_mode_t link_mode); 1715 1716#if EFSYS_OPT_MON_STATS 1717 1718typedef __checkReturn boolean_t 1719(*efx_monitor_ev_t)( 1720 __in_opt void *arg, 1721 __in efx_mon_stat_t id, 1722 __in efx_mon_stat_value_t value); 1723 1724#endif /* EFSYS_OPT_MON_STATS */ 1725 1726#if EFSYS_OPT_MAC_STATS 1727 1728typedef __checkReturn boolean_t 1729(*efx_mac_stats_ev_t)( 1730 __in_opt void *arg, 1731 __in uint32_t generation 1732 ); 1733 1734#endif /* EFSYS_OPT_MAC_STATS */ 1735 1736typedef struct efx_ev_callbacks_s { 1737 efx_initialized_ev_t eec_initialized; 1738 efx_rx_ev_t eec_rx; 1739 efx_tx_ev_t eec_tx; 1740 efx_exception_ev_t eec_exception; 1741 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1742 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1743 efx_txq_flush_done_ev_t eec_txq_flush_done; 1744 efx_software_ev_t eec_software; 1745 efx_sram_ev_t eec_sram; 1746 efx_wake_up_ev_t eec_wake_up; 1747 efx_timer_ev_t eec_timer; 1748 efx_link_change_ev_t eec_link_change; 1749#if EFSYS_OPT_MON_STATS 1750 efx_monitor_ev_t eec_monitor; 1751#endif /* EFSYS_OPT_MON_STATS */ 1752#if EFSYS_OPT_MAC_STATS 1753 efx_mac_stats_ev_t eec_mac_stats; 1754#endif /* EFSYS_OPT_MAC_STATS */ 1755} efx_ev_callbacks_t; 1756 1757extern __checkReturn boolean_t 1758efx_ev_qpending( 1759 __in efx_evq_t *eep, 1760 __in unsigned int count); 1761 1762#if EFSYS_OPT_EV_PREFETCH 1763 1764extern void 1765efx_ev_qprefetch( 1766 __in efx_evq_t *eep, 1767 __in unsigned int count); 1768 1769#endif /* EFSYS_OPT_EV_PREFETCH */ 1770 1771extern void 1772efx_ev_qpoll( 1773 __in efx_evq_t *eep, 1774 __inout unsigned int *countp, 1775 __in const efx_ev_callbacks_t *eecp, 1776 __in_opt void *arg); 1777 1778extern __checkReturn efx_rc_t 1779efx_ev_qmoderate( 1780 __in efx_evq_t *eep, 1781 __in unsigned int us); 1782 1783extern __checkReturn efx_rc_t 1784efx_ev_qprime( 1785 __in efx_evq_t *eep, 1786 __in unsigned int count); 1787 1788#if EFSYS_OPT_QSTATS 1789 1790#if EFSYS_OPT_NAMES 1791 1792extern const char * 1793efx_ev_qstat_name( 1794 __in efx_nic_t *enp, 1795 __in unsigned int id); 1796 1797#endif /* EFSYS_OPT_NAMES */ 1798 1799extern void 1800efx_ev_qstats_update( 1801 __in efx_evq_t *eep, 1802 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1803 1804#endif /* EFSYS_OPT_QSTATS */ 1805 1806extern void 1807efx_ev_qdestroy( 1808 __in efx_evq_t *eep); 1809 1810/* RX */ 1811 1812extern __checkReturn efx_rc_t 1813efx_rx_init( 1814 __inout efx_nic_t *enp); 1815 1816extern void 1817efx_rx_fini( 1818 __in efx_nic_t *enp); 1819 1820#if EFSYS_OPT_RX_SCATTER 1821 __checkReturn efx_rc_t 1822efx_rx_scatter_enable( 1823 __in efx_nic_t *enp, 1824 __in unsigned int buf_size); 1825#endif /* EFSYS_OPT_RX_SCATTER */ 1826 1827#if EFSYS_OPT_RX_SCALE 1828 1829typedef enum efx_rx_hash_alg_e { 1830 EFX_RX_HASHALG_LFSR = 0, 1831 EFX_RX_HASHALG_TOEPLITZ 1832} efx_rx_hash_alg_t; 1833 1834typedef enum efx_rx_hash_type_e { 1835 EFX_RX_HASH_IPV4 = 0, 1836 EFX_RX_HASH_TCPIPV4, 1837 EFX_RX_HASH_IPV6, 1838 EFX_RX_HASH_TCPIPV6, 1839} efx_rx_hash_type_t; 1840 1841typedef enum efx_rx_hash_support_e { 1842 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 1843 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 1844} efx_rx_hash_support_t; 1845 1846#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1847#define EFX_MAXRSS 64 /* RX indirection entry range */ 1848#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1849 1850typedef enum efx_rx_scale_support_e { 1851 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */ 1852 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 1853 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 1854} efx_rx_scale_support_t; 1855 1856extern __checkReturn efx_rc_t 1857efx_rx_hash_support_get( 1858 __in efx_nic_t *enp, 1859 __out efx_rx_hash_support_t *supportp); 1860 1861 1862extern __checkReturn efx_rc_t 1863efx_rx_scale_support_get( 1864 __in efx_nic_t *enp, 1865 __out efx_rx_scale_support_t *supportp); 1866 1867extern __checkReturn efx_rc_t 1868efx_rx_scale_mode_set( 1869 __in efx_nic_t *enp, 1870 __in efx_rx_hash_alg_t alg, 1871 __in efx_rx_hash_type_t type, 1872 __in boolean_t insert); 1873 1874extern __checkReturn efx_rc_t 1875efx_rx_scale_tbl_set( 1876 __in efx_nic_t *enp, 1877 __in_ecount(n) unsigned int *table, 1878 __in size_t n); 1879 1880extern __checkReturn efx_rc_t 1881efx_rx_scale_key_set( 1882 __in efx_nic_t *enp, 1883 __in_ecount(n) uint8_t *key, 1884 __in size_t n); 1885 1886extern __checkReturn uint32_t 1887efx_psuedo_hdr_hash_get( 1888 __in efx_nic_t *enp, 1889 __in efx_rx_hash_alg_t func, 1890 __in uint8_t *buffer); 1891 1892#endif /* EFSYS_OPT_RX_SCALE */ 1893 1894extern __checkReturn efx_rc_t 1895efx_psuedo_hdr_pkt_length_get( 1896 __in efx_nic_t *enp, 1897 __in uint8_t *buffer, 1898 __out uint16_t *pkt_lengthp); 1899 1900#define EFX_RXQ_MAXNDESCS 4096 1901#define EFX_RXQ_MINNDESCS 512 1902 1903#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1904#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1905#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1906#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1907 1908typedef enum efx_rxq_type_e { 1909 EFX_RXQ_TYPE_DEFAULT, 1910 EFX_RXQ_TYPE_SCATTER, 1911 EFX_RXQ_NTYPES 1912} efx_rxq_type_t; 1913 1914extern __checkReturn efx_rc_t 1915efx_rx_qcreate( 1916 __in efx_nic_t *enp, 1917 __in unsigned int index, 1918 __in unsigned int label, 1919 __in efx_rxq_type_t type, 1920 __in efsys_mem_t *esmp, 1921 __in size_t n, 1922 __in uint32_t id, 1923 __in efx_evq_t *eep, 1924 __deref_out efx_rxq_t **erpp); 1925 1926typedef struct efx_buffer_s { 1927 efsys_dma_addr_t eb_addr; 1928 size_t eb_size; 1929 boolean_t eb_eop; 1930} efx_buffer_t; 1931 1932typedef struct efx_desc_s { 1933 efx_qword_t ed_eq; 1934} efx_desc_t; 1935 1936extern void 1937efx_rx_qpost( 1938 __in efx_rxq_t *erp, 1939 __in_ecount(n) efsys_dma_addr_t *addrp, 1940 __in size_t size, 1941 __in unsigned int n, 1942 __in unsigned int completed, 1943 __in unsigned int added); 1944 1945extern void 1946efx_rx_qpush( 1947 __in efx_rxq_t *erp, 1948 __in unsigned int added, 1949 __inout unsigned int *pushedp); 1950 1951extern __checkReturn efx_rc_t 1952efx_rx_qflush( 1953 __in efx_rxq_t *erp); 1954 1955extern void 1956efx_rx_qenable( 1957 __in efx_rxq_t *erp); 1958 1959extern void 1960efx_rx_qdestroy( 1961 __in efx_rxq_t *erp); 1962 1963/* TX */ 1964 1965typedef struct efx_txq_s efx_txq_t; 1966 1967#if EFSYS_OPT_QSTATS 1968 1969/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 1970typedef enum efx_tx_qstat_e { 1971 TX_POST, 1972 TX_POST_PIO, 1973 TX_NQSTATS 1974} efx_tx_qstat_t; 1975 1976/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 1977 1978#endif /* EFSYS_OPT_QSTATS */ 1979 1980extern __checkReturn efx_rc_t 1981efx_tx_init( 1982 __in efx_nic_t *enp); 1983 1984extern void 1985efx_tx_fini( 1986 __in efx_nic_t *enp); 1987 1988#define EFX_BUG35388_WORKAROUND(_encp) \ 1989 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0)) 1990 1991#define EFX_TXQ_MAXNDESCS(_encp) \ 1992 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096) 1993 1994#define EFX_TXQ_MINNDESCS 512 1995 1996#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1997#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1998#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1999#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2000 2001#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2002 2003#define EFX_TXQ_CKSUM_IPV4 0x0001 2004#define EFX_TXQ_CKSUM_TCPUDP 0x0002 2005 2006extern __checkReturn efx_rc_t 2007efx_tx_qcreate( 2008 __in efx_nic_t *enp, 2009 __in unsigned int index, 2010 __in unsigned int label, 2011 __in efsys_mem_t *esmp, 2012 __in size_t n, 2013 __in uint32_t id, 2014 __in uint16_t flags, 2015 __in efx_evq_t *eep, 2016 __deref_out efx_txq_t **etpp, 2017 __out unsigned int *addedp); 2018 2019extern __checkReturn efx_rc_t 2020efx_tx_qpost( 2021 __in efx_txq_t *etp, 2022 __in_ecount(n) efx_buffer_t *eb, 2023 __in unsigned int n, 2024 __in unsigned int completed, 2025 __inout unsigned int *addedp); 2026 2027extern __checkReturn efx_rc_t 2028efx_tx_qpace( 2029 __in efx_txq_t *etp, 2030 __in unsigned int ns); 2031 2032extern void 2033efx_tx_qpush( 2034 __in efx_txq_t *etp, 2035 __in unsigned int added, 2036 __in unsigned int pushed); 2037 2038extern __checkReturn efx_rc_t 2039efx_tx_qflush( 2040 __in efx_txq_t *etp); 2041 2042extern void 2043efx_tx_qenable( 2044 __in efx_txq_t *etp); 2045 2046extern __checkReturn efx_rc_t 2047efx_tx_qpio_enable( 2048 __in efx_txq_t *etp); 2049 2050extern void 2051efx_tx_qpio_disable( 2052 __in efx_txq_t *etp); 2053 2054extern __checkReturn efx_rc_t 2055efx_tx_qpio_write( 2056 __in efx_txq_t *etp, 2057 __in_ecount(buf_length) uint8_t *buffer, 2058 __in size_t buf_length, 2059 __in size_t pio_buf_offset); 2060 2061extern __checkReturn efx_rc_t 2062efx_tx_qpio_post( 2063 __in efx_txq_t *etp, 2064 __in size_t pkt_length, 2065 __in unsigned int completed, 2066 __inout unsigned int *addedp); 2067 2068extern __checkReturn efx_rc_t 2069efx_tx_qdesc_post( 2070 __in efx_txq_t *etp, 2071 __in_ecount(n) efx_desc_t *ed, 2072 __in unsigned int n, 2073 __in unsigned int completed, 2074 __inout unsigned int *addedp); 2075 2076extern void 2077efx_tx_qdesc_dma_create( 2078 __in efx_txq_t *etp, 2079 __in efsys_dma_addr_t addr, 2080 __in size_t size, 2081 __in boolean_t eop, 2082 __out efx_desc_t *edp); 2083 2084extern void 2085efx_tx_qdesc_tso_create( 2086 __in efx_txq_t *etp, 2087 __in uint16_t ipv4_id, 2088 __in uint32_t tcp_seq, 2089 __in uint8_t tcp_flags, 2090 __out efx_desc_t *edp); 2091 2092extern void 2093efx_tx_qdesc_vlantci_create( 2094 __in efx_txq_t *etp, 2095 __in uint16_t tci, 2096 __out efx_desc_t *edp); 2097 2098#if EFSYS_OPT_QSTATS 2099 2100#if EFSYS_OPT_NAMES 2101 2102extern const char * 2103efx_tx_qstat_name( 2104 __in efx_nic_t *etp, 2105 __in unsigned int id); 2106 2107#endif /* EFSYS_OPT_NAMES */ 2108 2109extern void 2110efx_tx_qstats_update( 2111 __in efx_txq_t *etp, 2112 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2113 2114#endif /* EFSYS_OPT_QSTATS */ 2115 2116extern void 2117efx_tx_qdestroy( 2118 __in efx_txq_t *etp); 2119 2120 2121/* FILTER */ 2122 2123#if EFSYS_OPT_FILTER 2124 2125#define EFX_ETHER_TYPE_IPV4 0x0800 2126#define EFX_ETHER_TYPE_IPV6 0x86DD 2127 2128#define EFX_IPPROTO_TCP 6 2129#define EFX_IPPROTO_UDP 17 2130 2131typedef enum efx_filter_flag_e { 2132 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across 2133 * multiple queues */ 2134 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */ 2135 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter 2136 * (priority EFX_FILTER_PRI_AUTO). 2137 * May only be set by the filter 2138 * implementation for each type. 2139 * A removal request will 2140 * restore the automatic filter 2141 * in its place. */ 2142 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */ 2143 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */ 2144} efx_filter_flag_t; 2145 2146typedef enum efx_filter_match_flags_e { 2147 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host 2148 * address */ 2149 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host 2150 * address */ 2151 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */ 2152 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */ 2153 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */ 2154 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */ 2155 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */ 2156 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */ 2157 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */ 2158 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport 2159 * protocol */ 2160 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address 2161 * I/G bit. Used for RX default 2162 * unicast and multicast/ 2163 * broadcast filters. */ 2164} efx_filter_match_flags_t; 2165 2166typedef enum efx_filter_priority_s { 2167 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2168 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2169 * address list or hardware 2170 * requirements. This may only be used 2171 * by the filter implementation for 2172 * each NIC type. */ 2173 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2174 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2175 * client (e.g. SR-IOV, HyperV VMQ etc.) 2176 */ 2177} efx_filter_priority_t; 2178 2179/* 2180 * FIXME: All these fields are assumed to be in little-endian byte order. 2181 * It may be better for some to be big-endian. See bug42804. 2182 */ 2183 2184typedef struct efx_filter_spec_s { 2185 uint32_t efs_match_flags:12; 2186 uint32_t efs_priority:2; 2187 uint32_t efs_flags:6; 2188 uint32_t efs_dmaq_id:12; 2189 uint32_t efs_rss_context; 2190 uint16_t efs_outer_vid; 2191 uint16_t efs_inner_vid; 2192 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2193 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2194 uint16_t efs_ether_type; 2195 uint8_t efs_ip_proto; 2196 uint16_t efs_loc_port; 2197 uint16_t efs_rem_port; 2198 efx_oword_t efs_rem_host; 2199 efx_oword_t efs_loc_host; 2200} efx_filter_spec_t; 2201 2202 2203/* Default values for use in filter specifications */ 2204#define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff 2205#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2206#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2207 2208extern __checkReturn efx_rc_t 2209efx_filter_init( 2210 __in efx_nic_t *enp); 2211 2212extern void 2213efx_filter_fini( 2214 __in efx_nic_t *enp); 2215 2216extern __checkReturn efx_rc_t 2217efx_filter_insert( 2218 __in efx_nic_t *enp, 2219 __inout efx_filter_spec_t *spec); 2220 2221extern __checkReturn efx_rc_t 2222efx_filter_remove( 2223 __in efx_nic_t *enp, 2224 __inout efx_filter_spec_t *spec); 2225 2226extern __checkReturn efx_rc_t 2227efx_filter_restore( 2228 __in efx_nic_t *enp); 2229 2230extern __checkReturn efx_rc_t 2231efx_filter_supported_filters( 2232 __in efx_nic_t *enp, 2233 __out uint32_t *list, 2234 __out size_t *length); 2235 2236extern void 2237efx_filter_spec_init_rx( 2238 __out efx_filter_spec_t *spec, 2239 __in efx_filter_priority_t priority, 2240 __in efx_filter_flag_t flags, 2241 __in efx_rxq_t *erp); 2242 2243extern void 2244efx_filter_spec_init_tx( 2245 __out efx_filter_spec_t *spec, 2246 __in efx_txq_t *etp); 2247 2248extern __checkReturn efx_rc_t 2249efx_filter_spec_set_ipv4_local( 2250 __inout efx_filter_spec_t *spec, 2251 __in uint8_t proto, 2252 __in uint32_t host, 2253 __in uint16_t port); 2254 2255extern __checkReturn efx_rc_t 2256efx_filter_spec_set_ipv4_full( 2257 __inout efx_filter_spec_t *spec, 2258 __in uint8_t proto, 2259 __in uint32_t lhost, 2260 __in uint16_t lport, 2261 __in uint32_t rhost, 2262 __in uint16_t rport); 2263 2264extern __checkReturn efx_rc_t 2265efx_filter_spec_set_eth_local( 2266 __inout efx_filter_spec_t *spec, 2267 __in uint16_t vid, 2268 __in const uint8_t *addr); 2269 2270extern __checkReturn efx_rc_t 2271efx_filter_spec_set_uc_def( 2272 __inout efx_filter_spec_t *spec); 2273 2274extern __checkReturn efx_rc_t 2275efx_filter_spec_set_mc_def( 2276 __inout efx_filter_spec_t *spec); 2277 2278#endif /* EFSYS_OPT_FILTER */ 2279 2280/* HASH */ 2281 2282extern __checkReturn uint32_t 2283efx_hash_dwords( 2284 __in_ecount(count) uint32_t const *input, 2285 __in size_t count, 2286 __in uint32_t init); 2287 2288extern __checkReturn uint32_t 2289efx_hash_bytes( 2290 __in_ecount(length) uint8_t const *input, 2291 __in size_t length, 2292 __in uint32_t init); 2293 2294 2295#ifdef __cplusplus 2296} 2297#endif 2298 2299#endif /* _SYS_EFX_H */ 2300